1//===------- X86InstrOperands.td - X86 Operand Definitions --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 10// the index operand of an address, to conform to x86 encoding restrictions. 11def ptr_rc_nosp : PointerLikeRegClass<1>; 12 13// *mem - Operand definitions for the funky X86 addressing mode operands. 14// 15def X86MemAsmOperand : AsmOperandClass { 16 let Name = "Mem"; 17} 18let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { 19 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 20 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 21 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 22 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 23 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 24 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 25 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 26 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 27 // Gather mem operands 28 def X86Mem32_RC128Operand : AsmOperandClass { let Name = "Mem32_RC128"; } 29 def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } 30 def X86Mem32_RC256Operand : AsmOperandClass { let Name = "Mem32_RC256"; } 31 def X86Mem64_RC256Operand : AsmOperandClass { let Name = "Mem64_RC256"; } 32 33 def X86Mem32_RC128XOperand : AsmOperandClass { let Name = "Mem32_RC128X"; } 34 def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } 35 def X86Mem32_RC256XOperand : AsmOperandClass { let Name = "Mem32_RC256X"; } 36 def X86Mem64_RC256XOperand : AsmOperandClass { let Name = "Mem64_RC256X"; } 37 def X86Mem32_RC512Operand : AsmOperandClass { let Name = "Mem32_RC512"; } 38 def X86Mem64_RC512Operand : AsmOperandClass { let Name = "Mem64_RC512"; } 39 40 def X86Mem512_GR16Operand : AsmOperandClass { let Name = "Mem512_GR16"; } 41 def X86Mem512_GR32Operand : AsmOperandClass { let Name = "Mem512_GR32"; } 42 def X86Mem512_GR64Operand : AsmOperandClass { let Name = "Mem512_GR64"; } 43 44 def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; } 45} 46 47def X86AbsMemAsmOperand : AsmOperandClass { 48 let Name = "AbsMem"; 49 let SuperClasses = [X86MemAsmOperand]; 50} 51 52class X86MemOperand<string printMethod, 53 AsmOperandClass parserMatchClass = X86MemAsmOperand, 54 int size = 0> : Operand<iPTR> { 55 let PrintMethod = printMethod; 56 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); 57 let ParserMatchClass = parserMatchClass; 58 let OperandType = "OPERAND_MEMORY"; 59 int Size = size; 60} 61 62// Gather mem operands 63class X86VMemOperand<RegisterClass RC, string printMethod, 64 AsmOperandClass parserMatchClass, int size = 0> 65 : X86MemOperand<printMethod, parserMatchClass, size> { 66 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); 67} 68 69def anymem : X86MemOperand<"printMemReference">; 70 71// FIXME: Right now we allow any size during parsing, but we might want to 72// restrict to only unsized memory. 73def opaquemem : X86MemOperand<"printMemReference">; 74 75def sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>; 76 77def i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8>; 78def i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; 79def i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; 80def i64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; 81def i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; 82def i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; 83def i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; 84def f16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand, 16>; 85def f32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32>; 86def f64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64>; 87def f80mem : X86MemOperand<"printtbytemem", X86Mem80AsmOperand, 80>; 88def f128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand, 128>; 89def f256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand, 256>; 90def f512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand, 512>; 91 92// 32/64 mode specific mem operands 93def i512mem_GR16 : X86MemOperand<"printzmmwordmem", X86Mem512_GR16Operand, 512>; 94def i512mem_GR32 : X86MemOperand<"printzmmwordmem", X86Mem512_GR32Operand, 512>; 95def i512mem_GR64 : X86MemOperand<"printzmmwordmem", X86Mem512_GR64Operand, 512>; 96 97// Gather mem operands 98def vx32mem : X86VMemOperand<VR128, "printdwordmem", X86Mem32_RC128Operand, 32>; 99def vx64mem : X86VMemOperand<VR128, "printqwordmem", X86Mem64_RC128Operand, 64>; 100def vy32mem : X86VMemOperand<VR256, "printdwordmem", X86Mem32_RC256Operand, 32>; 101def vy64mem : X86VMemOperand<VR256, "printqwordmem", X86Mem64_RC256Operand, 64>; 102 103def vx32xmem : X86VMemOperand<VR128X, "printdwordmem", X86Mem32_RC128XOperand, 32>; 104def vx64xmem : X86VMemOperand<VR128X, "printqwordmem", X86Mem64_RC128XOperand, 64>; 105def vy32xmem : X86VMemOperand<VR256X, "printdwordmem", X86Mem32_RC256XOperand, 32>; 106def vy64xmem : X86VMemOperand<VR256X, "printqwordmem", X86Mem64_RC256XOperand, 64>; 107def vz32mem : X86VMemOperand<VR512, "printdwordmem", X86Mem32_RC512Operand, 32>; 108def vz64mem : X86VMemOperand<VR512, "printqwordmem", X86Mem64_RC512Operand, 64>; 109 110def shmem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>; 111def ssmem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; 112def sdmem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; 113 114// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead 115// of a plain GPR, so that it doesn't potentially require a REX prefix. 116def ptr_rc_norex : PointerLikeRegClass<2>; 117def ptr_rc_norex_nosp : PointerLikeRegClass<3>; 118 119def i8mem_NOREX : X86MemOperand<"printbytemem", X86Mem8AsmOperand, 8> { 120 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, 121 SEGMENT_REG); 122} 123 124// GPRs available for tailcall. 125// It represents GR32_TC, GR64_TC or GR64_TCW64. 126def ptr_rc_tailcall : PointerLikeRegClass<4>; 127 128// Special i32mem for addresses of load folding tail calls. These are not 129// allowed to use callee-saved registers since they must be scheduled 130// after callee-saved register are popped. 131def i32mem_TC : X86MemOperand<"printdwordmem", X86Mem32AsmOperand, 32> { 132 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 133 i32imm, SEGMENT_REG); 134} 135 136// Special i64mem for addresses of load folding tail calls. These are not 137// allowed to use callee-saved registers since they must be scheduled 138// after callee-saved register are popped. 139def i64mem_TC : X86MemOperand<"printqwordmem", X86Mem64AsmOperand, 64> { 140 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 141 ptr_rc_tailcall, i32imm, SEGMENT_REG); 142} 143 144// Special parser to detect 16-bit mode to select 16-bit displacement. 145def X86AbsMem16AsmOperand : AsmOperandClass { 146 let Name = "AbsMem16"; 147 let RenderMethod = "addAbsMemOperands"; 148 let SuperClasses = [X86AbsMemAsmOperand]; 149} 150 151// Branch targets print as pc-relative values. 152class BranchTargetOperand<ValueType ty> : Operand<ty> { 153 let OperandType = "OPERAND_PCREL"; 154 let PrintMethod = "printPCRelImm"; 155 let ParserMatchClass = X86AbsMemAsmOperand; 156} 157 158def i32imm_brtarget : BranchTargetOperand<i32>; 159def i16imm_brtarget : BranchTargetOperand<i16>; 160 161// 64-bits but only 32 bits are significant, and those bits are treated as being 162// pc relative. 163def i64i32imm_brtarget : BranchTargetOperand<i64>; 164 165def brtarget : BranchTargetOperand<OtherVT>; 166def brtarget8 : BranchTargetOperand<OtherVT>; 167def brtarget16 : BranchTargetOperand<OtherVT> { 168 let ParserMatchClass = X86AbsMem16AsmOperand; 169} 170def brtarget32 : BranchTargetOperand<OtherVT>; 171 172let RenderMethod = "addSrcIdxOperands" in { 173 def X86SrcIdx8Operand : AsmOperandClass { 174 let Name = "SrcIdx8"; 175 let SuperClasses = [X86Mem8AsmOperand]; 176 } 177 def X86SrcIdx16Operand : AsmOperandClass { 178 let Name = "SrcIdx16"; 179 let SuperClasses = [X86Mem16AsmOperand]; 180 } 181 def X86SrcIdx32Operand : AsmOperandClass { 182 let Name = "SrcIdx32"; 183 let SuperClasses = [X86Mem32AsmOperand]; 184 } 185 def X86SrcIdx64Operand : AsmOperandClass { 186 let Name = "SrcIdx64"; 187 let SuperClasses = [X86Mem64AsmOperand]; 188 } 189} // RenderMethod = "addSrcIdxOperands" 190 191let RenderMethod = "addDstIdxOperands" in { 192 def X86DstIdx8Operand : AsmOperandClass { 193 let Name = "DstIdx8"; 194 let SuperClasses = [X86Mem8AsmOperand]; 195 } 196 def X86DstIdx16Operand : AsmOperandClass { 197 let Name = "DstIdx16"; 198 let SuperClasses = [X86Mem16AsmOperand]; 199 } 200 def X86DstIdx32Operand : AsmOperandClass { 201 let Name = "DstIdx32"; 202 let SuperClasses = [X86Mem32AsmOperand]; 203 } 204 def X86DstIdx64Operand : AsmOperandClass { 205 let Name = "DstIdx64"; 206 let SuperClasses = [X86Mem64AsmOperand]; 207 } 208} // RenderMethod = "addDstIdxOperands" 209 210let RenderMethod = "addMemOffsOperands" in { 211 def X86MemOffs16_8AsmOperand : AsmOperandClass { 212 let Name = "MemOffs16_8"; 213 let SuperClasses = [X86Mem8AsmOperand]; 214 } 215 def X86MemOffs16_16AsmOperand : AsmOperandClass { 216 let Name = "MemOffs16_16"; 217 let SuperClasses = [X86Mem16AsmOperand]; 218 } 219 def X86MemOffs16_32AsmOperand : AsmOperandClass { 220 let Name = "MemOffs16_32"; 221 let SuperClasses = [X86Mem32AsmOperand]; 222 } 223 def X86MemOffs32_8AsmOperand : AsmOperandClass { 224 let Name = "MemOffs32_8"; 225 let SuperClasses = [X86Mem8AsmOperand]; 226 } 227 def X86MemOffs32_16AsmOperand : AsmOperandClass { 228 let Name = "MemOffs32_16"; 229 let SuperClasses = [X86Mem16AsmOperand]; 230 } 231 def X86MemOffs32_32AsmOperand : AsmOperandClass { 232 let Name = "MemOffs32_32"; 233 let SuperClasses = [X86Mem32AsmOperand]; 234 } 235 def X86MemOffs32_64AsmOperand : AsmOperandClass { 236 let Name = "MemOffs32_64"; 237 let SuperClasses = [X86Mem64AsmOperand]; 238 } 239 def X86MemOffs64_8AsmOperand : AsmOperandClass { 240 let Name = "MemOffs64_8"; 241 let SuperClasses = [X86Mem8AsmOperand]; 242 } 243 def X86MemOffs64_16AsmOperand : AsmOperandClass { 244 let Name = "MemOffs64_16"; 245 let SuperClasses = [X86Mem16AsmOperand]; 246 } 247 def X86MemOffs64_32AsmOperand : AsmOperandClass { 248 let Name = "MemOffs64_32"; 249 let SuperClasses = [X86Mem32AsmOperand]; 250 } 251 def X86MemOffs64_64AsmOperand : AsmOperandClass { 252 let Name = "MemOffs64_64"; 253 let SuperClasses = [X86Mem64AsmOperand]; 254 } 255} // RenderMethod = "addMemOffsOperands" 256 257class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 258 : X86MemOperand<printMethod, parserMatchClass> { 259 let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); 260} 261 262class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 263 : X86MemOperand<printMethod, parserMatchClass> { 264 let MIOperandInfo = (ops ptr_rc); 265} 266 267def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 268def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 269def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 270def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 271def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 272def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 273def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 274def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 275 276class X86MemOffsOperand<Operand immOperand, string printMethod, 277 AsmOperandClass parserMatchClass> 278 : X86MemOperand<printMethod, parserMatchClass> { 279 let MIOperandInfo = (ops immOperand, SEGMENT_REG); 280} 281 282def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 283 X86MemOffs16_8AsmOperand>; 284def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 285 X86MemOffs16_16AsmOperand>; 286def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 287 X86MemOffs16_32AsmOperand>; 288def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 289 X86MemOffs32_8AsmOperand>; 290def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 291 X86MemOffs32_16AsmOperand>; 292def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 293 X86MemOffs32_32AsmOperand>; 294def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 295 X86MemOffs32_64AsmOperand>; 296def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 297 X86MemOffs64_8AsmOperand>; 298def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 299 X86MemOffs64_16AsmOperand>; 300def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 301 X86MemOffs64_32AsmOperand>; 302def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 303 X86MemOffs64_64AsmOperand>; 304 305def ccode : Operand<i8> { 306 let PrintMethod = "printCondCode"; 307 let OperandNamespace = "X86"; 308 let OperandType = "OPERAND_COND_CODE"; 309} 310 311class ImmSExtAsmOperandClass : AsmOperandClass { 312 let SuperClasses = [ImmAsmOperand]; 313 let RenderMethod = "addImmOperands"; 314} 315 316def X86GR32orGR64AsmOperand : AsmOperandClass { 317 let Name = "GR32orGR64"; 318} 319def GR32orGR64 : RegisterOperand<GR32> { 320 let ParserMatchClass = X86GR32orGR64AsmOperand; 321} 322 323def X86GR16orGR32orGR64AsmOperand : AsmOperandClass { 324 let Name = "GR16orGR32orGR64"; 325} 326def GR16orGR32orGR64 : RegisterOperand<GR16> { 327 let ParserMatchClass = X86GR16orGR32orGR64AsmOperand; 328} 329 330def AVX512RCOperand : AsmOperandClass { 331 let Name = "AVX512RC"; 332} 333def AVX512RC : Operand<i32> { 334 let PrintMethod = "printRoundingControl"; 335 let OperandNamespace = "X86"; 336 let OperandType = "OPERAND_ROUNDING_CONTROL"; 337 let ParserMatchClass = AVX512RCOperand; 338} 339 340// Sign-extended immediate classes. We don't need to define the full lattice 341// here because there is no instruction with an ambiguity between ImmSExti64i32 342// and ImmSExti32i8. 343// 344// The strange ranges come from the fact that the assembler always works with 345// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 346// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 347 348// [0, 0x7FFFFFFF] | 349// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 350def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 351 let Name = "ImmSExti64i32"; 352} 353 354// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 355// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 356def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 357 let Name = "ImmSExti16i8"; 358 let SuperClasses = [ImmSExti64i32AsmOperand]; 359} 360 361// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 362// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 363def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 364 let Name = "ImmSExti32i8"; 365} 366 367// [0, 0x0000007F] | 368// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 369def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 370 let Name = "ImmSExti64i8"; 371 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 372 ImmSExti64i32AsmOperand]; 373} 374 375// 4-bit immediate used by some XOP instructions 376// [0, 0xF] 377def ImmUnsignedi4AsmOperand : AsmOperandClass { 378 let Name = "ImmUnsignedi4"; 379 let RenderMethod = "addImmOperands"; 380 let DiagnosticType = "InvalidImmUnsignedi4"; 381} 382 383// Unsigned immediate used by SSE/AVX instructions 384// [0, 0xFF] 385// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 386def ImmUnsignedi8AsmOperand : AsmOperandClass { 387 let Name = "ImmUnsignedi8"; 388 let RenderMethod = "addImmOperands"; 389} 390 391// A couple of more descriptive operand definitions. 392// 16-bits but only 8 bits are significant. 393def i16i8imm : Operand<i16> { 394 let ParserMatchClass = ImmSExti16i8AsmOperand; 395 let OperandType = "OPERAND_IMMEDIATE"; 396} 397// 32-bits but only 8 bits are significant. 398def i32i8imm : Operand<i32> { 399 let ParserMatchClass = ImmSExti32i8AsmOperand; 400 let OperandType = "OPERAND_IMMEDIATE"; 401} 402 403// 64-bits but only 32 bits are significant. 404def i64i32imm : Operand<i64> { 405 let ParserMatchClass = ImmSExti64i32AsmOperand; 406 let OperandType = "OPERAND_IMMEDIATE"; 407} 408 409// 64-bits but only 8 bits are significant. 410def i64i8imm : Operand<i64> { 411 let ParserMatchClass = ImmSExti64i8AsmOperand; 412 let OperandType = "OPERAND_IMMEDIATE"; 413} 414 415// Unsigned 4-bit immediate used by some XOP instructions. 416def u4imm : Operand<i8> { 417 let PrintMethod = "printU8Imm"; 418 let ParserMatchClass = ImmUnsignedi4AsmOperand; 419 let OperandType = "OPERAND_IMMEDIATE"; 420} 421 422def cflags : Operand<i8> { 423 let PrintMethod = "printCondFlags"; 424 let ParserMatchClass = ImmUnsignedi4AsmOperand; 425 let OperandType = "OPERAND_IMMEDIATE"; 426} 427 428// Unsigned 8-bit immediate used by SSE/AVX instructions. 429def u8imm : Operand<i8> { 430 let PrintMethod = "printU8Imm"; 431 let ParserMatchClass = ImmUnsignedi8AsmOperand; 432 let OperandType = "OPERAND_IMMEDIATE"; 433} 434 435// 16-bit immediate but only 8-bits are significant and they are unsigned. 436// Used by BT instructions. 437def i16u8imm : Operand<i16> { 438 let PrintMethod = "printU8Imm"; 439 let ParserMatchClass = ImmUnsignedi8AsmOperand; 440 let OperandType = "OPERAND_IMMEDIATE"; 441} 442 443// 32-bit immediate but only 8-bits are significant and they are unsigned. 444// Used by some SSE/AVX instructions that use intrinsics. 445def i32u8imm : Operand<i32> { 446 let PrintMethod = "printU8Imm"; 447 let ParserMatchClass = ImmUnsignedi8AsmOperand; 448 let OperandType = "OPERAND_IMMEDIATE"; 449} 450 451// 64-bit immediate but only 8-bits are significant and they are unsigned. 452// Used by BT instructions. 453def i64u8imm : Operand<i64> { 454 let PrintMethod = "printU8Imm"; 455 let ParserMatchClass = ImmUnsignedi8AsmOperand; 456 let OperandType = "OPERAND_IMMEDIATE"; 457} 458 459def lea64_32mem : Operand<i32> { 460 let PrintMethod = "printMemReference"; 461 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 462 let ParserMatchClass = X86MemAsmOperand; 463} 464 465// Memory operands that use 64-bit pointers in both ILP32 and LP64. 466def lea64mem : Operand<i64> { 467 let PrintMethod = "printMemReference"; 468 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 469 let ParserMatchClass = X86MemAsmOperand; 470} 471 472let RenderMethod = "addMaskPairOperands" in { 473 def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; } 474 def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; } 475 def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; } 476 def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; } 477 def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; } 478} 479 480def VK1Pair : RegisterOperand<VK1PAIR, "printVKPair"> { 481 let ParserMatchClass = VK1PairAsmOperand; 482} 483 484def VK2Pair : RegisterOperand<VK2PAIR, "printVKPair"> { 485 let ParserMatchClass = VK2PairAsmOperand; 486} 487 488def VK4Pair : RegisterOperand<VK4PAIR, "printVKPair"> { 489 let ParserMatchClass = VK4PairAsmOperand; 490} 491 492def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> { 493 let ParserMatchClass = VK8PairAsmOperand; 494} 495 496def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> { 497 let ParserMatchClass = VK16PairAsmOperand; 498} 499 500let RenderMethod = "addTILEPairOperands" in 501 def TILEPairAsmOperand : AsmOperandClass { let Name = "TILEPair"; } 502 503def TILEPair : RegisterOperand<TILEPAIR, "printTILEPair"> { 504 let ParserMatchClass = TILEPairAsmOperand; 505} 506