1 //===- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "X86CallLowering.h"
16 #include "X86CallingConv.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
26 #include "llvm/CodeGen/GlobalISel/Utils.h"
27 #include "llvm/CodeGen/LowLevelType.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineMemOperand.h"
33 #include "llvm/CodeGen/MachineOperand.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/TargetInstrInfo.h"
36 #include "llvm/CodeGen/TargetSubtargetInfo.h"
37 #include "llvm/CodeGen/ValueTypes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/MC/MCRegisterInfo.h"
43 #include "llvm/Support/LowLevelTypeImpl.h"
44 #include "llvm/Support/MachineValueType.h"
45 #include <cassert>
46 #include <cstdint>
47
48 using namespace llvm;
49
X86CallLowering(const X86TargetLowering & TLI)50 X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
51 : CallLowering(&TLI) {}
52
53 namespace {
54
55 struct X86OutgoingValueAssigner : public CallLowering::OutgoingValueAssigner {
56 private:
57 uint64_t StackSize = 0;
58 unsigned NumXMMRegs = 0;
59
60 public:
getStackSize__anond7df946f0111::X86OutgoingValueAssigner61 uint64_t getStackSize() { return StackSize; }
getNumXmmRegs__anond7df946f0111::X86OutgoingValueAssigner62 unsigned getNumXmmRegs() { return NumXMMRegs; }
63
X86OutgoingValueAssigner__anond7df946f0111::X86OutgoingValueAssigner64 X86OutgoingValueAssigner(CCAssignFn *AssignFn_)
65 : CallLowering::OutgoingValueAssigner(AssignFn_) {}
66
assignArg__anond7df946f0111::X86OutgoingValueAssigner67 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
68 CCValAssign::LocInfo LocInfo,
69 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
70 CCState &State) override {
71 bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
72 StackSize = State.getNextStackOffset();
73
74 static const MCPhysReg XMMArgRegs[] = {X86::XMM0, X86::XMM1, X86::XMM2,
75 X86::XMM3, X86::XMM4, X86::XMM5,
76 X86::XMM6, X86::XMM7};
77 if (!Info.IsFixed)
78 NumXMMRegs = State.getFirstUnallocated(XMMArgRegs);
79
80 return Res;
81 }
82 };
83
84 struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
X86OutgoingValueHandler__anond7df946f0111::X86OutgoingValueHandler85 X86OutgoingValueHandler(MachineIRBuilder &MIRBuilder,
86 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
87 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB),
88 DL(MIRBuilder.getMF().getDataLayout()),
89 STI(MIRBuilder.getMF().getSubtarget<X86Subtarget>()) {}
90
getStackAddress__anond7df946f0111::X86OutgoingValueHandler91 Register getStackAddress(uint64_t Size, int64_t Offset,
92 MachinePointerInfo &MPO,
93 ISD::ArgFlagsTy Flags) override {
94 LLT p0 = LLT::pointer(0, DL.getPointerSizeInBits(0));
95 LLT SType = LLT::scalar(DL.getPointerSizeInBits(0));
96 auto SPReg =
97 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister());
98
99 auto OffsetReg = MIRBuilder.buildConstant(SType, Offset);
100
101 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
102
103 MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
104 return AddrReg.getReg(0);
105 }
106
assignValueToReg__anond7df946f0111::X86OutgoingValueHandler107 void assignValueToReg(Register ValVReg, Register PhysReg,
108 CCValAssign &VA) override {
109 MIB.addUse(PhysReg, RegState::Implicit);
110 Register ExtReg = extendRegister(ValVReg, VA);
111 MIRBuilder.buildCopy(PhysReg, ExtReg);
112 }
113
assignValueToAddress__anond7df946f0111::X86OutgoingValueHandler114 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
115 MachinePointerInfo &MPO, CCValAssign &VA) override {
116 MachineFunction &MF = MIRBuilder.getMF();
117 Register ExtReg = extendRegister(ValVReg, VA);
118
119 auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore,
120 VA.getLocVT().getStoreSize(),
121 inferAlignFromPtrInfo(MF, MPO));
122 MIRBuilder.buildStore(ExtReg, Addr, *MMO);
123 }
124
125 protected:
126 MachineInstrBuilder &MIB;
127 const DataLayout &DL;
128 const X86Subtarget &STI;
129 };
130
131 } // end anonymous namespace
132
lowerReturn(MachineIRBuilder & MIRBuilder,const Value * Val,ArrayRef<Register> VRegs,FunctionLoweringInfo & FLI) const133 bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
134 const Value *Val, ArrayRef<Register> VRegs,
135 FunctionLoweringInfo &FLI) const {
136 assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
137 "Return value without a vreg");
138 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
139
140 if (!VRegs.empty()) {
141 MachineFunction &MF = MIRBuilder.getMF();
142 const Function &F = MF.getFunction();
143 MachineRegisterInfo &MRI = MF.getRegInfo();
144 const DataLayout &DL = MF.getDataLayout();
145
146 ArgInfo OrigRetInfo(VRegs, Val->getType());
147 setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
148
149 SmallVector<ArgInfo, 4> SplitRetInfos;
150 splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, F.getCallingConv());
151
152 X86OutgoingValueAssigner Assigner(RetCC_X86);
153 X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
154 if (!determineAndHandleAssignments(Handler, Assigner, SplitRetInfos,
155 MIRBuilder, F.getCallingConv(),
156 F.isVarArg()))
157 return false;
158 }
159
160 MIRBuilder.insertInstr(MIB);
161 return true;
162 }
163
164 namespace {
165
166 struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
X86IncomingValueHandler__anond7df946f0211::X86IncomingValueHandler167 X86IncomingValueHandler(MachineIRBuilder &MIRBuilder,
168 MachineRegisterInfo &MRI)
169 : IncomingValueHandler(MIRBuilder, MRI),
170 DL(MIRBuilder.getMF().getDataLayout()) {}
171
getStackAddress__anond7df946f0211::X86IncomingValueHandler172 Register getStackAddress(uint64_t Size, int64_t Offset,
173 MachinePointerInfo &MPO,
174 ISD::ArgFlagsTy Flags) override {
175 auto &MFI = MIRBuilder.getMF().getFrameInfo();
176
177 // Byval is assumed to be writable memory, but other stack passed arguments
178 // are not.
179 const bool IsImmutable = !Flags.isByVal();
180
181 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
182 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
183
184 return MIRBuilder
185 .buildFrameIndex(LLT::pointer(0, DL.getPointerSizeInBits(0)), FI)
186 .getReg(0);
187 }
188
assignValueToAddress__anond7df946f0211::X86IncomingValueHandler189 void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
190 MachinePointerInfo &MPO, CCValAssign &VA) override {
191 MachineFunction &MF = MIRBuilder.getMF();
192 auto *MMO = MF.getMachineMemOperand(
193 MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
194 inferAlignFromPtrInfo(MF, MPO));
195 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
196 }
197
assignValueToReg__anond7df946f0211::X86IncomingValueHandler198 void assignValueToReg(Register ValVReg, Register PhysReg,
199 CCValAssign &VA) override {
200 markPhysRegUsed(PhysReg);
201 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
202 }
203
204 /// How the physical register gets marked varies between formal
205 /// parameters (it's a basic-block live-in), and a call instruction
206 /// (it's an implicit-def of the BL).
207 virtual void markPhysRegUsed(unsigned PhysReg) = 0;
208
209 protected:
210 const DataLayout &DL;
211 };
212
213 struct FormalArgHandler : public X86IncomingValueHandler {
FormalArgHandler__anond7df946f0211::FormalArgHandler214 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
215 : X86IncomingValueHandler(MIRBuilder, MRI) {}
216
markPhysRegUsed__anond7df946f0211::FormalArgHandler217 void markPhysRegUsed(unsigned PhysReg) override {
218 MIRBuilder.getMRI()->addLiveIn(PhysReg);
219 MIRBuilder.getMBB().addLiveIn(PhysReg);
220 }
221 };
222
223 struct CallReturnHandler : public X86IncomingValueHandler {
CallReturnHandler__anond7df946f0211::CallReturnHandler224 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
225 MachineInstrBuilder &MIB)
226 : X86IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
227
markPhysRegUsed__anond7df946f0211::CallReturnHandler228 void markPhysRegUsed(unsigned PhysReg) override {
229 MIB.addDef(PhysReg, RegState::Implicit);
230 }
231
232 protected:
233 MachineInstrBuilder &MIB;
234 };
235
236 } // end anonymous namespace
237
lowerFormalArguments(MachineIRBuilder & MIRBuilder,const Function & F,ArrayRef<ArrayRef<Register>> VRegs,FunctionLoweringInfo & FLI) const238 bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
239 const Function &F,
240 ArrayRef<ArrayRef<Register>> VRegs,
241 FunctionLoweringInfo &FLI) const {
242 if (F.arg_empty())
243 return true;
244
245 // TODO: handle variadic function
246 if (F.isVarArg())
247 return false;
248
249 MachineFunction &MF = MIRBuilder.getMF();
250 MachineRegisterInfo &MRI = MF.getRegInfo();
251 auto DL = MF.getDataLayout();
252
253 SmallVector<ArgInfo, 8> SplitArgs;
254 unsigned Idx = 0;
255 for (const auto &Arg : F.args()) {
256 // TODO: handle not simple cases.
257 if (Arg.hasAttribute(Attribute::ByVal) ||
258 Arg.hasAttribute(Attribute::InReg) ||
259 Arg.hasAttribute(Attribute::StructRet) ||
260 Arg.hasAttribute(Attribute::SwiftSelf) ||
261 Arg.hasAttribute(Attribute::SwiftError) ||
262 Arg.hasAttribute(Attribute::Nest) || VRegs[Idx].size() > 1)
263 return false;
264
265 ArgInfo OrigArg(VRegs[Idx], Arg.getType());
266 setArgFlags(OrigArg, Idx + AttributeList::FirstArgIndex, DL, F);
267 splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
268 Idx++;
269 }
270
271 MachineBasicBlock &MBB = MIRBuilder.getMBB();
272 if (!MBB.empty())
273 MIRBuilder.setInstr(*MBB.begin());
274
275 X86OutgoingValueAssigner Assigner(CC_X86);
276 FormalArgHandler Handler(MIRBuilder, MRI);
277 if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
278 F.getCallingConv(), F.isVarArg()))
279 return false;
280
281 // Move back to the end of the basic block.
282 MIRBuilder.setMBB(MBB);
283
284 return true;
285 }
286
lowerCall(MachineIRBuilder & MIRBuilder,CallLoweringInfo & Info) const287 bool X86CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
288 CallLoweringInfo &Info) const {
289 MachineFunction &MF = MIRBuilder.getMF();
290 const Function &F = MF.getFunction();
291 MachineRegisterInfo &MRI = MF.getRegInfo();
292 const DataLayout &DL = F.getParent()->getDataLayout();
293 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
294 const TargetInstrInfo &TII = *STI.getInstrInfo();
295 const X86RegisterInfo *TRI = STI.getRegisterInfo();
296
297 // Handle only Linux C, X86_64_SysV calling conventions for now.
298 if (!STI.isTargetLinux() || !(Info.CallConv == CallingConv::C ||
299 Info.CallConv == CallingConv::X86_64_SysV))
300 return false;
301
302 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
303 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
304
305 // Create a temporarily-floating call instruction so we can add the implicit
306 // uses of arg registers.
307 bool Is64Bit = STI.is64Bit();
308 unsigned CallOpc = Info.Callee.isReg()
309 ? (Is64Bit ? X86::CALL64r : X86::CALL32r)
310 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
311
312 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc)
313 .add(Info.Callee)
314 .addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
315
316 SmallVector<ArgInfo, 8> SplitArgs;
317 for (const auto &OrigArg : Info.OrigArgs) {
318
319 // TODO: handle not simple cases.
320 if (OrigArg.Flags[0].isByVal())
321 return false;
322
323 if (OrigArg.Regs.size() > 1)
324 return false;
325
326 splitToValueTypes(OrigArg, SplitArgs, DL, Info.CallConv);
327 }
328 // Do the actual argument marshalling.
329 X86OutgoingValueAssigner Assigner(CC_X86);
330 X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB);
331 if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
332 Info.CallConv, Info.IsVarArg))
333 return false;
334
335 bool IsFixed = Info.OrigArgs.empty() ? true : Info.OrigArgs.back().IsFixed;
336 if (STI.is64Bit() && !IsFixed && !STI.isCallingConvWin64(Info.CallConv)) {
337 // From AMD64 ABI document:
338 // For calls that may call functions that use varargs or stdargs
339 // (prototype-less calls or calls to functions containing ellipsis (...) in
340 // the declaration) %al is used as hidden argument to specify the number
341 // of SSE registers used. The contents of %al do not need to match exactly
342 // the number of registers, but must be an ubound on the number of SSE
343 // registers used and is in the range 0 - 8 inclusive.
344
345 MIRBuilder.buildInstr(X86::MOV8ri)
346 .addDef(X86::AL)
347 .addImm(Assigner.getNumXmmRegs());
348 MIB.addUse(X86::AL, RegState::Implicit);
349 }
350
351 // Now we can add the actual call instruction to the correct basic block.
352 MIRBuilder.insertInstr(MIB);
353
354 // If Callee is a reg, since it is used by a target specific
355 // instruction, it must have a register class matching the
356 // constraint of that instruction.
357 if (Info.Callee.isReg())
358 MIB->getOperand(0).setReg(constrainOperandRegClass(
359 MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(),
360 *MF.getSubtarget().getRegBankInfo(), *MIB, MIB->getDesc(), Info.Callee,
361 0));
362
363 // Finally we can copy the returned value back into its virtual-register. In
364 // symmetry with the arguments, the physical register must be an
365 // implicit-define of the call instruction.
366
367 if (!Info.OrigRet.Ty->isVoidTy()) {
368 if (Info.OrigRet.Regs.size() > 1)
369 return false;
370
371 SplitArgs.clear();
372 SmallVector<Register, 8> NewRegs;
373
374 splitToValueTypes(Info.OrigRet, SplitArgs, DL, Info.CallConv);
375
376 X86OutgoingValueAssigner Assigner(RetCC_X86);
377 CallReturnHandler Handler(MIRBuilder, MRI, MIB);
378 if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
379 Info.CallConv, Info.IsVarArg))
380 return false;
381
382 if (!NewRegs.empty())
383 MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs);
384 }
385
386 CallSeqStart.addImm(Assigner.getStackSize())
387 .addImm(0 /* see getFrameTotalSize */)
388 .addImm(0 /* see getFrameAdjustment */);
389
390 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
391 MIRBuilder.buildInstr(AdjStackUp)
392 .addImm(Assigner.getStackSize())
393 .addImm(0 /* NumBytesForCalleeToPop */);
394
395 return true;
396 }
397