1 //===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file includes code for rendering MCInst instances as AT&T-style 10 // assembly. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86ATTInstPrinter.h" 15 #include "X86BaseInfo.h" 16 #include "X86InstComments.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrAnalysis.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/Format.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <cassert> 26 #include <cinttypes> 27 #include <cstdint> 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "asm-printer" 32 33 // Include the auto-generated portion of the assembly writer. 34 #define PRINT_ALIAS_INSTR 35 #include "X86GenAsmWriter.inc" 36 37 void X86ATTInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) { 38 markup(OS, Markup::Register) << '%' << getRegisterName(Reg); 39 } 40 41 void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address, 42 StringRef Annot, const MCSubtargetInfo &STI, 43 raw_ostream &OS) { 44 // If verbose assembly is enabled, we can print some informative comments. 45 if (CommentStream) 46 HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII); 47 48 printInstFlags(MI, OS, STI); 49 50 // Output CALLpcrel32 as "callq" in 64-bit mode. 51 // In Intel annotation it's always emitted as "call". 52 // 53 // TODO: Probably this hack should be redesigned via InstAlias in 54 // InstrInfo.td as soon as Requires clause is supported properly 55 // for InstAlias. 56 if (MI->getOpcode() == X86::CALLpcrel32 && 57 (STI.hasFeature(X86::Is64Bit))) { 58 OS << "\tcallq\t"; 59 printPCRelImm(MI, Address, 0, OS); 60 } 61 // data16 and data32 both have the same encoding of 0x66. While data32 is 62 // valid only in 16 bit systems, data16 is valid in the rest. 63 // There seems to be some lack of support of the Requires clause that causes 64 // 0x66 to be interpreted as "data16" by the asm printer. 65 // Thus we add an adjustment here in order to print the "right" instruction. 66 else if (MI->getOpcode() == X86::DATA16_PREFIX && 67 STI.hasFeature(X86::Is16Bit)) { 68 OS << "\tdata32"; 69 } 70 // Try to print any aliases first. 71 else if (!printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS)) 72 printInstruction(MI, Address, OS); 73 74 // Next always print the annotation. 75 printAnnotation(OS, Annot); 76 } 77 78 bool X86ATTInstPrinter::printVecCompareInstr(const MCInst *MI, 79 raw_ostream &OS) { 80 if (MI->getNumOperands() == 0 || 81 !MI->getOperand(MI->getNumOperands() - 1).isImm()) 82 return false; 83 84 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); 85 86 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 87 88 // Custom print the vector compare instructions to get the immediate 89 // translated into the mnemonic. 90 switch (MI->getOpcode()) { 91 case X86::CMPPDrmi: case X86::CMPPDrri: 92 case X86::CMPPSrmi: case X86::CMPPSrri: 93 case X86::CMPSDrmi: case X86::CMPSDrri: 94 case X86::CMPSDrmi_Int: case X86::CMPSDrri_Int: 95 case X86::CMPSSrmi: case X86::CMPSSrri: 96 case X86::CMPSSrmi_Int: case X86::CMPSSrri_Int: 97 if (Imm >= 0 && Imm <= 7) { 98 OS << '\t'; 99 printCMPMnemonic(MI, /*IsVCMP*/false, OS); 100 101 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { 102 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) 103 printdwordmem(MI, 2, OS); 104 else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD) 105 printqwordmem(MI, 2, OS); 106 else 107 printxmmwordmem(MI, 2, OS); 108 } else 109 printOperand(MI, 2, OS); 110 111 // Skip operand 1 as its tied to the dest. 112 113 OS << ", "; 114 printOperand(MI, 0, OS); 115 return true; 116 } 117 break; 118 119 case X86::VCMPPDrmi: case X86::VCMPPDrri: 120 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: 121 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri: 122 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri: 123 case X86::VCMPPDZrmi: case X86::VCMPPDZrri: 124 case X86::VCMPPSrmi: case X86::VCMPPSrri: 125 case X86::VCMPPSYrmi: case X86::VCMPPSYrri: 126 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri: 127 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri: 128 case X86::VCMPPSZrmi: case X86::VCMPPSZrri: 129 case X86::VCMPSDrmi: case X86::VCMPSDrri: 130 case X86::VCMPSDZrmi: case X86::VCMPSDZrri: 131 case X86::VCMPSDrmi_Int: case X86::VCMPSDrri_Int: 132 case X86::VCMPSDZrmi_Int: case X86::VCMPSDZrri_Int: 133 case X86::VCMPSSrmi: case X86::VCMPSSrri: 134 case X86::VCMPSSZrmi: case X86::VCMPSSZrri: 135 case X86::VCMPSSrmi_Int: case X86::VCMPSSrri_Int: 136 case X86::VCMPSSZrmi_Int: case X86::VCMPSSZrri_Int: 137 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik: 138 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik: 139 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik: 140 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik: 141 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik: 142 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik: 143 case X86::VCMPSDZrmik_Int: case X86::VCMPSDZrrik_Int: 144 case X86::VCMPSSZrmik_Int: case X86::VCMPSSZrrik_Int: 145 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik: 146 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik: 147 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik: 148 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik: 149 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik: 150 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik: 151 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk: 152 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk: 153 case X86::VCMPSDZrrib_Int: case X86::VCMPSDZrribk_Int: 154 case X86::VCMPSSZrrib_Int: case X86::VCMPSSZrribk_Int: 155 case X86::VCMPPHZ128rmi: case X86::VCMPPHZ128rri: 156 case X86::VCMPPHZ256rmi: case X86::VCMPPHZ256rri: 157 case X86::VCMPPHZrmi: case X86::VCMPPHZrri: 158 case X86::VCMPSHZrmi: case X86::VCMPSHZrri: 159 case X86::VCMPSHZrmi_Int: case X86::VCMPSHZrri_Int: 160 case X86::VCMPPHZ128rmik: case X86::VCMPPHZ128rrik: 161 case X86::VCMPPHZ256rmik: case X86::VCMPPHZ256rrik: 162 case X86::VCMPPHZrmik: case X86::VCMPPHZrrik: 163 case X86::VCMPSHZrmik_Int: case X86::VCMPSHZrrik_Int: 164 case X86::VCMPPHZ128rmbi: case X86::VCMPPHZ128rmbik: 165 case X86::VCMPPHZ256rmbi: case X86::VCMPPHZ256rmbik: 166 case X86::VCMPPHZrmbi: case X86::VCMPPHZrmbik: 167 case X86::VCMPPHZrrib: case X86::VCMPPHZrribk: 168 case X86::VCMPSHZrrib_Int: case X86::VCMPSHZrribk_Int: 169 case X86::VCMPBF16Z128rmi: case X86::VCMPBF16Z128rri: 170 case X86::VCMPBF16Z256rmi: case X86::VCMPBF16Z256rri: 171 case X86::VCMPBF16Zrmi: case X86::VCMPBF16Zrri: 172 case X86::VCMPBF16Z128rmik: case X86::VCMPBF16Z128rrik: 173 case X86::VCMPBF16Z256rmik: case X86::VCMPBF16Z256rrik: 174 case X86::VCMPBF16Zrmik: case X86::VCMPBF16Zrrik: 175 case X86::VCMPBF16Z128rmbi: case X86::VCMPBF16Z128rmbik: 176 case X86::VCMPBF16Z256rmbi: case X86::VCMPBF16Z256rmbik: 177 case X86::VCMPBF16Zrmbi: case X86::VCMPBF16Zrmbik: 178 if (Imm >= 0 && Imm <= 31) { 179 OS << '\t'; 180 printCMPMnemonic(MI, /*IsVCMP*/true, OS); 181 182 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; 183 184 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { 185 if (Desc.TSFlags & X86II::EVEX_B) { 186 // Broadcast form. 187 // Load size is word for TA map. Otherwise it is based on W-bit. 188 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { 189 assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); 190 printwordmem(MI, CurOp--, OS); 191 } else if (Desc.TSFlags & X86II::REX_W) { 192 printqwordmem(MI, CurOp--, OS); 193 } else { 194 printdwordmem(MI, CurOp--, OS); 195 } 196 197 // Print the number of elements broadcasted. 198 unsigned NumElts; 199 if (Desc.TSFlags & X86II::EVEX_L2) 200 NumElts = (Desc.TSFlags & X86II::REX_W) ? 8 : 16; 201 else if (Desc.TSFlags & X86II::VEX_L) 202 NumElts = (Desc.TSFlags & X86II::REX_W) ? 4 : 8; 203 else 204 NumElts = (Desc.TSFlags & X86II::REX_W) ? 2 : 4; 205 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { 206 assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); 207 NumElts *= 2; 208 } 209 OS << "{1to" << NumElts << "}"; 210 } else { 211 if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS) { 212 if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) 213 printwordmem(MI, CurOp--, OS); 214 else 215 printdwordmem(MI, CurOp--, OS); 216 } else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD && 217 (Desc.TSFlags & X86II::OpMapMask) != X86II::TA) { 218 printqwordmem(MI, CurOp--, OS); 219 } else if (Desc.TSFlags & X86II::EVEX_L2) { 220 printzmmwordmem(MI, CurOp--, OS); 221 } else if (Desc.TSFlags & X86II::VEX_L) { 222 printymmwordmem(MI, CurOp--, OS); 223 } else { 224 printxmmwordmem(MI, CurOp--, OS); 225 } 226 } 227 } else { 228 if (Desc.TSFlags & X86II::EVEX_B) 229 OS << "{sae}, "; 230 printOperand(MI, CurOp--, OS); 231 } 232 233 OS << ", "; 234 printOperand(MI, CurOp--, OS); 235 OS << ", "; 236 printOperand(MI, 0, OS); 237 if (CurOp > 0) { 238 // Print mask operand. 239 OS << " {"; 240 printOperand(MI, CurOp--, OS); 241 OS << "}"; 242 } 243 244 return true; 245 } 246 break; 247 248 case X86::VPCOMBmi: case X86::VPCOMBri: 249 case X86::VPCOMDmi: case X86::VPCOMDri: 250 case X86::VPCOMQmi: case X86::VPCOMQri: 251 case X86::VPCOMUBmi: case X86::VPCOMUBri: 252 case X86::VPCOMUDmi: case X86::VPCOMUDri: 253 case X86::VPCOMUQmi: case X86::VPCOMUQri: 254 case X86::VPCOMUWmi: case X86::VPCOMUWri: 255 case X86::VPCOMWmi: case X86::VPCOMWri: 256 if (Imm >= 0 && Imm <= 7) { 257 OS << '\t'; 258 printVPCOMMnemonic(MI, OS); 259 260 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) 261 printxmmwordmem(MI, 2, OS); 262 else 263 printOperand(MI, 2, OS); 264 265 OS << ", "; 266 printOperand(MI, 1, OS); 267 OS << ", "; 268 printOperand(MI, 0, OS); 269 return true; 270 } 271 break; 272 273 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: 274 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: 275 case X86::VPCMPBZrmi: case X86::VPCMPBZrri: 276 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri: 277 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri: 278 case X86::VPCMPDZrmi: case X86::VPCMPDZrri: 279 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri: 280 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri: 281 case X86::VPCMPQZrmi: case X86::VPCMPQZrri: 282 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri: 283 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri: 284 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri: 285 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri: 286 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri: 287 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri: 288 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri: 289 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri: 290 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri: 291 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri: 292 case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri: 293 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri: 294 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri: 295 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri: 296 case X86::VPCMPWZrmi: case X86::VPCMPWZrri: 297 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik: 298 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik: 299 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik: 300 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik: 301 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik: 302 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik: 303 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik: 304 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik: 305 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik: 306 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik: 307 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik: 308 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik: 309 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik: 310 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik: 311 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik: 312 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik: 313 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik: 314 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik: 315 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik: 316 case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik: 317 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik: 318 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik: 319 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik: 320 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik: 321 case X86::VPCMPDZ128rmbi: case X86::VPCMPDZ128rmbik: 322 case X86::VPCMPDZ256rmbi: case X86::VPCMPDZ256rmbik: 323 case X86::VPCMPDZrmbi: case X86::VPCMPDZrmbik: 324 case X86::VPCMPQZ128rmbi: case X86::VPCMPQZ128rmbik: 325 case X86::VPCMPQZ256rmbi: case X86::VPCMPQZ256rmbik: 326 case X86::VPCMPQZrmbi: case X86::VPCMPQZrmbik: 327 case X86::VPCMPUDZ128rmbi: case X86::VPCMPUDZ128rmbik: 328 case X86::VPCMPUDZ256rmbi: case X86::VPCMPUDZ256rmbik: 329 case X86::VPCMPUDZrmbi: case X86::VPCMPUDZrmbik: 330 case X86::VPCMPUQZ128rmbi: case X86::VPCMPUQZ128rmbik: 331 case X86::VPCMPUQZ256rmbi: case X86::VPCMPUQZ256rmbik: 332 case X86::VPCMPUQZrmbi: case X86::VPCMPUQZrmbik: 333 if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) { 334 OS << '\t'; 335 printVPCMPMnemonic(MI, OS); 336 337 unsigned CurOp = (Desc.TSFlags & X86II::EVEX_K) ? 3 : 2; 338 339 if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) { 340 if (Desc.TSFlags & X86II::EVEX_B) { 341 // Broadcast form. 342 // Load size is based on W-bit as only D and Q are supported. 343 if (Desc.TSFlags & X86II::REX_W) 344 printqwordmem(MI, CurOp--, OS); 345 else 346 printdwordmem(MI, CurOp--, OS); 347 348 // Print the number of elements broadcasted. 349 unsigned NumElts; 350 if (Desc.TSFlags & X86II::EVEX_L2) 351 NumElts = (Desc.TSFlags & X86II::REX_W) ? 8 : 16; 352 else if (Desc.TSFlags & X86II::VEX_L) 353 NumElts = (Desc.TSFlags & X86II::REX_W) ? 4 : 8; 354 else 355 NumElts = (Desc.TSFlags & X86II::REX_W) ? 2 : 4; 356 OS << "{1to" << NumElts << "}"; 357 } else { 358 if (Desc.TSFlags & X86II::EVEX_L2) 359 printzmmwordmem(MI, CurOp--, OS); 360 else if (Desc.TSFlags & X86II::VEX_L) 361 printymmwordmem(MI, CurOp--, OS); 362 else 363 printxmmwordmem(MI, CurOp--, OS); 364 } 365 } else { 366 printOperand(MI, CurOp--, OS); 367 } 368 369 OS << ", "; 370 printOperand(MI, CurOp--, OS); 371 OS << ", "; 372 printOperand(MI, 0, OS); 373 if (CurOp > 0) { 374 // Print mask operand. 375 OS << " {"; 376 printOperand(MI, CurOp--, OS); 377 OS << "}"; 378 } 379 380 return true; 381 } 382 break; 383 } 384 385 return false; 386 } 387 388 void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 389 raw_ostream &O) { 390 const MCOperand &Op = MI->getOperand(OpNo); 391 if (Op.isReg()) { 392 printRegName(O, Op.getReg()); 393 } else if (Op.isImm()) { 394 // Print immediates as signed values. 395 int64_t Imm = Op.getImm(); 396 markup(O, Markup::Immediate) << '$' << formatImm(Imm); 397 398 // TODO: This should be in a helper function in the base class, so it can 399 // be used by other printers. 400 401 // If there are no instruction-specific comments, add a comment clarifying 402 // the hex value of the immediate operand when it isn't in the range 403 // [-256,255]. 404 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) { 405 // Don't print unnecessary hex sign bits. 406 if (Imm == (int16_t)(Imm)) 407 *CommentStream << format("imm = 0x%" PRIX16 "\n", (uint16_t)Imm); 408 else if (Imm == (int32_t)(Imm)) 409 *CommentStream << format("imm = 0x%" PRIX32 "\n", (uint32_t)Imm); 410 else 411 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Imm); 412 } 413 } else { 414 assert(Op.isExpr() && "unknown operand kind in printOperand"); 415 WithMarkup M = markup(O, Markup::Immediate); 416 O << '$'; 417 Op.getExpr()->print(O, &MAI); 418 } 419 } 420 421 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, 422 raw_ostream &O) { 423 // Do not print the exact form of the memory operand if it references a known 424 // binary object. 425 if (SymbolizeOperands && MIA) { 426 uint64_t Target; 427 if (MIA->evaluateBranch(*MI, 0, 0, Target)) 428 return; 429 if (MIA->evaluateMemoryOperandAddress(*MI, /*STI=*/nullptr, 0, 0)) 430 return; 431 } 432 433 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); 434 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); 435 const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp); 436 437 WithMarkup M = markup(O, Markup::Memory); 438 439 // If this has a segment register, print it. 440 printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O); 441 442 if (DispSpec.isImm()) { 443 int64_t DispVal = DispSpec.getImm(); 444 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) 445 O << formatImm(DispVal); 446 } else { 447 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?"); 448 DispSpec.getExpr()->print(O, &MAI); 449 } 450 451 if (IndexReg.getReg() || BaseReg.getReg()) { 452 O << '('; 453 if (BaseReg.getReg()) 454 printOperand(MI, Op + X86::AddrBaseReg, O); 455 456 if (IndexReg.getReg()) { 457 O << ','; 458 printOperand(MI, Op + X86::AddrIndexReg, O); 459 unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm(); 460 if (ScaleVal != 1) { 461 O << ','; 462 markup(O, Markup::Immediate) << ScaleVal; // never printed in hex. 463 } 464 } 465 O << ')'; 466 } 467 } 468 469 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op, 470 raw_ostream &O) { 471 WithMarkup M = markup(O, Markup::Memory); 472 473 // If this has a segment register, print it. 474 printOptionalSegReg(MI, Op + 1, O); 475 476 O << "("; 477 printOperand(MI, Op, O); 478 O << ")"; 479 } 480 481 void X86ATTInstPrinter::printDstIdx(const MCInst *MI, unsigned Op, 482 raw_ostream &O) { 483 WithMarkup M = markup(O, Markup::Memory); 484 485 O << "%es:("; 486 printOperand(MI, Op, O); 487 O << ")"; 488 } 489 490 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op, 491 raw_ostream &O) { 492 const MCOperand &DispSpec = MI->getOperand(Op); 493 494 WithMarkup M = markup(O, Markup::Memory); 495 496 // If this has a segment register, print it. 497 printOptionalSegReg(MI, Op + 1, O); 498 499 if (DispSpec.isImm()) { 500 O << formatImm(DispSpec.getImm()); 501 } else { 502 assert(DispSpec.isExpr() && "non-immediate displacement?"); 503 DispSpec.getExpr()->print(O, &MAI); 504 } 505 } 506 507 void X86ATTInstPrinter::printU8Imm(const MCInst *MI, unsigned Op, 508 raw_ostream &O) { 509 if (MI->getOperand(Op).isExpr()) 510 return printOperand(MI, Op, O); 511 512 markup(O, Markup::Immediate) 513 << '$' << formatImm(MI->getOperand(Op).getImm() & 0xff); 514 } 515 516 void X86ATTInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo, 517 raw_ostream &OS) { 518 MCRegister Reg = MI->getOperand(OpNo).getReg(); 519 // Override the default printing to print st(0) instead st. 520 if (Reg == X86::ST0) 521 markup(OS, Markup::Register) << "%st(0)"; 522 else 523 printRegName(OS, Reg); 524 } 525