1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb-2 IT blocks ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "ARM.h" 10 #include "ARMMachineFunctionInfo.h" 11 #include "ARMSubtarget.h" 12 #include "Thumb2InstrInfo.h" 13 #include "llvm/ADT/SmallSet.h" 14 #include "llvm/ADT/SmallVector.h" 15 #include "llvm/ADT/Statistic.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineFunctionPass.h" 20 #include "llvm/CodeGen/MachineInstr.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineInstrBundle.h" 23 #include "llvm/CodeGen/MachineOperand.h" 24 #include "llvm/IR/DebugLoc.h" 25 #include "llvm/MC/MCInstrDesc.h" 26 #include <cassert> 27 #include <new> 28 29 using namespace llvm; 30 31 #define DEBUG_TYPE "thumb2-it" 32 #define PASS_NAME "Thumb IT blocks insertion pass" 33 34 STATISTIC(NumITs, "Number of IT blocks inserted"); 35 STATISTIC(NumMovedInsts, "Number of predicated instructions moved"); 36 37 using RegisterSet = SmallSet<unsigned, 4>; 38 39 namespace { 40 41 class Thumb2ITBlock : public MachineFunctionPass { 42 public: 43 static char ID; 44 45 bool restrictIT; 46 const Thumb2InstrInfo *TII; 47 const TargetRegisterInfo *TRI; 48 ARMFunctionInfo *AFI; 49 50 Thumb2ITBlock() : MachineFunctionPass(ID) {} 51 52 bool runOnMachineFunction(MachineFunction &Fn) override; 53 54 MachineFunctionProperties getRequiredProperties() const override { 55 return MachineFunctionProperties().set( 56 MachineFunctionProperties::Property::NoVRegs); 57 } 58 59 StringRef getPassName() const override { 60 return PASS_NAME; 61 } 62 63 private: 64 bool MoveCopyOutOfITBlock(MachineInstr *MI, 65 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 66 RegisterSet &Defs, RegisterSet &Uses); 67 bool InsertITInstructions(MachineBasicBlock &Block); 68 }; 69 70 char Thumb2ITBlock::ID = 0; 71 72 } // end anonymous namespace 73 74 INITIALIZE_PASS(Thumb2ITBlock, DEBUG_TYPE, PASS_NAME, false, false) 75 76 /// TrackDefUses - Tracking what registers are being defined and used by 77 /// instructions in the IT block. This also tracks "dependencies", i.e. uses 78 /// in the IT block that are defined before the IT instruction. 79 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, 80 const TargetRegisterInfo *TRI) { 81 using RegList = SmallVector<unsigned, 4>; 82 RegList LocalDefs; 83 RegList LocalUses; 84 85 for (auto &MO : MI->operands()) { 86 if (!MO.isReg()) 87 continue; 88 Register Reg = MO.getReg(); 89 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP) 90 continue; 91 if (MO.isUse()) 92 LocalUses.push_back(Reg); 93 else 94 LocalDefs.push_back(Reg); 95 } 96 97 auto InsertUsesDefs = [&](RegList &Regs, RegisterSet &UsesDefs) { 98 for (unsigned Reg : Regs) 99 for (MCPhysReg Subreg : TRI->subregs_inclusive(Reg)) 100 UsesDefs.insert(Subreg); 101 }; 102 103 InsertUsesDefs(LocalDefs, Defs); 104 InsertUsesDefs(LocalUses, Uses); 105 } 106 107 /// Clear kill flags for any uses in the given set. This will likely 108 /// conservatively remove more kill flags than are necessary, but removing them 109 /// is safer than incorrect kill flags remaining on instructions. 110 static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) { 111 for (MachineOperand &MO : MI->operands()) { 112 if (!MO.isReg() || MO.isDef() || !MO.isKill()) 113 continue; 114 if (!Uses.count(MO.getReg())) 115 continue; 116 MO.setIsKill(false); 117 } 118 } 119 120 static bool isCopy(MachineInstr *MI) { 121 switch (MI->getOpcode()) { 122 default: 123 return false; 124 case ARM::MOVr: 125 case ARM::MOVr_TC: 126 case ARM::tMOVr: 127 case ARM::t2MOVr: 128 return true; 129 } 130 } 131 132 bool 133 Thumb2ITBlock::MoveCopyOutOfITBlock(MachineInstr *MI, 134 ARMCC::CondCodes CC, ARMCC::CondCodes OCC, 135 RegisterSet &Defs, RegisterSet &Uses) { 136 if (!isCopy(MI)) 137 return false; 138 // llvm models select's as two-address instructions. That means a copy 139 // is inserted before a t2MOVccr, etc. If the copy is scheduled in 140 // between selects we would end up creating multiple IT blocks. 141 assert(MI->getOperand(0).getSubReg() == 0 && 142 MI->getOperand(1).getSubReg() == 0 && 143 "Sub-register indices still around?"); 144 145 Register DstReg = MI->getOperand(0).getReg(); 146 Register SrcReg = MI->getOperand(1).getReg(); 147 148 // First check if it's safe to move it. 149 if (Uses.count(DstReg) || Defs.count(SrcReg)) 150 return false; 151 152 // If the CPSR is defined by this copy, then we don't want to move it. E.g., 153 // if we have: 154 // 155 // movs r1, r1 156 // rsb r1, 0 157 // movs r2, r2 158 // rsb r2, 0 159 // 160 // we don't want this to be converted to: 161 // 162 // movs r1, r1 163 // movs r2, r2 164 // itt mi 165 // rsb r1, 0 166 // rsb r2, 0 167 // 168 const MCInstrDesc &MCID = MI->getDesc(); 169 if (MI->hasOptionalDef() && 170 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) 171 return false; 172 173 // Then peek at the next instruction to see if it's predicated on CC or OCC. 174 // If not, then there is nothing to be gained by moving the copy. 175 MachineBasicBlock::iterator I = MI; 176 ++I; 177 MachineBasicBlock::iterator E = MI->getParent()->end(); 178 179 while (I != E && I->isDebugInstr()) 180 ++I; 181 182 if (I != E) { 183 Register NPredReg; 184 ARMCC::CondCodes NCC = getITInstrPredicate(*I, NPredReg); 185 if (NCC == CC || NCC == OCC) 186 return true; 187 } 188 return false; 189 } 190 191 bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) { 192 bool Modified = false; 193 RegisterSet Defs, Uses; 194 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 195 196 while (MBBI != E) { 197 MachineInstr *MI = &*MBBI; 198 DebugLoc dl = MI->getDebugLoc(); 199 Register PredReg; 200 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg); 201 if (CC == ARMCC::AL) { 202 ++MBBI; 203 continue; 204 } 205 206 Defs.clear(); 207 Uses.clear(); 208 TrackDefUses(MI, Defs, Uses, TRI); 209 210 // Insert an IT instruction. 211 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT)) 212 .addImm(CC); 213 214 // Add implicit use of ITSTATE to IT block instructions. 215 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 216 true/*isImp*/, false/*isKill*/)); 217 218 MachineInstr *LastITMI = MI; 219 MachineBasicBlock::iterator InsertPos = MIB.getInstr(); 220 ++MBBI; 221 222 // Form IT block. 223 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); 224 unsigned Mask = 0, Pos = 3; 225 226 // IT blocks are limited to one conditional op if -arm-restrict-it 227 // is set: skip the loop 228 if (!restrictIT) { 229 LLVM_DEBUG(dbgs() << "Allowing complex IT block\n"); 230 // Branches, including tricky ones like LDM_RET, need to end an IT 231 // block so check the instruction we just put in the block. 232 for (; MBBI != E && Pos && 233 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { 234 if (MBBI->isDebugInstr()) 235 continue; 236 237 MachineInstr *NMI = &*MBBI; 238 MI = NMI; 239 240 Register NPredReg; 241 ARMCC::CondCodes NCC = getITInstrPredicate(*NMI, NPredReg); 242 if (NCC == CC || NCC == OCC) { 243 Mask |= ((NCC ^ CC) & 1) << Pos; 244 // Add implicit use of ITSTATE. 245 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 246 true/*isImp*/, false/*isKill*/)); 247 LastITMI = NMI; 248 } else { 249 if (NCC == ARMCC::AL && 250 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { 251 --MBBI; 252 MBB.remove(NMI); 253 MBB.insert(InsertPos, NMI); 254 ClearKillFlags(MI, Uses); 255 ++NumMovedInsts; 256 continue; 257 } 258 break; 259 } 260 TrackDefUses(NMI, Defs, Uses, TRI); 261 --Pos; 262 } 263 } 264 265 // Finalize IT mask. 266 Mask |= (1 << Pos); 267 MIB.addImm(Mask); 268 269 // Last instruction in IT block kills ITSTATE. 270 LastITMI->findRegisterUseOperand(ARM::ITSTATE, /*TRI=*/nullptr) 271 ->setIsKill(); 272 273 // Finalize the bundle. 274 finalizeBundle(MBB, InsertPos.getInstrIterator(), 275 ++LastITMI->getIterator()); 276 277 Modified = true; 278 ++NumITs; 279 } 280 281 return Modified; 282 } 283 284 bool Thumb2ITBlock::runOnMachineFunction(MachineFunction &Fn) { 285 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>(); 286 if (!STI.isThumb2()) 287 return false; 288 AFI = Fn.getInfo<ARMFunctionInfo>(); 289 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo()); 290 TRI = STI.getRegisterInfo(); 291 restrictIT = STI.restrictIT(); 292 293 if (!AFI->isThumbFunction()) 294 return false; 295 296 bool Modified = false; 297 for (auto &MBB : Fn ) 298 Modified |= InsertITInstructions(MBB); 299 300 if (Modified) 301 AFI->setHasITBlocks(true); 302 303 return Modified; 304 } 305 306 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks 307 /// insertion pass. 308 FunctionPass *llvm::createThumb2ITBlockPass() { return new Thumb2ITBlock(); } 309