1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SparcTargetMachine.h"
14 #include "SparcTargetObjectFile.h"
15 #include "Sparc.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/Support/TargetRegistry.h"
19 using namespace llvm;
20
LLVMInitializeSparcTarget()21 extern "C" void LLVMInitializeSparcTarget() {
22 // Register the target.
23 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
24 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
25 }
26
27 /// SparcTargetMachine ctor - Create an ILP32 architecture model
28 ///
SparcTargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL,bool is64bit)29 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
30 StringRef CPU, StringRef FS,
31 const TargetOptions &Options,
32 Reloc::Model RM, CodeModel::Model CM,
33 CodeGenOpt::Level OL,
34 bool is64bit)
35 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
36 TLOF(make_unique<SparcELFTargetObjectFile>()),
37 Subtarget(TT, CPU, FS, *this, is64bit) {
38 initAsmInfo();
39 }
40
~SparcTargetMachine()41 SparcTargetMachine::~SparcTargetMachine() {}
42
43 namespace {
44 /// Sparc Code Generator Pass Configuration Options.
45 class SparcPassConfig : public TargetPassConfig {
46 public:
SparcPassConfig(SparcTargetMachine * TM,PassManagerBase & PM)47 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
48 : TargetPassConfig(TM, PM) {}
49
getSparcTargetMachine() const50 SparcTargetMachine &getSparcTargetMachine() const {
51 return getTM<SparcTargetMachine>();
52 }
53
54 void addIRPasses() override;
55 bool addInstSelector() override;
56 void addPreEmitPass() override;
57 };
58 } // namespace
59
createPassConfig(PassManagerBase & PM)60 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
61 return new SparcPassConfig(this, PM);
62 }
63
addIRPasses()64 void SparcPassConfig::addIRPasses() {
65 addPass(createAtomicExpandPass(&getSparcTargetMachine()));
66
67 TargetPassConfig::addIRPasses();
68 }
69
addInstSelector()70 bool SparcPassConfig::addInstSelector() {
71 addPass(createSparcISelDag(getSparcTargetMachine()));
72 return false;
73 }
74
addPreEmitPass()75 void SparcPassConfig::addPreEmitPass(){
76 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
77 }
78
anchor()79 void SparcV8TargetMachine::anchor() { }
80
SparcV8TargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)81 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
82 StringRef TT, StringRef CPU,
83 StringRef FS,
84 const TargetOptions &Options,
85 Reloc::Model RM,
86 CodeModel::Model CM,
87 CodeGenOpt::Level OL)
88 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
89 }
90
anchor()91 void SparcV9TargetMachine::anchor() { }
92
SparcV9TargetMachine(const Target & T,StringRef TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Reloc::Model RM,CodeModel::Model CM,CodeGenOpt::Level OL)93 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
94 StringRef TT, StringRef CPU,
95 StringRef FS,
96 const TargetOptions &Options,
97 Reloc::Model RM,
98 CodeModel::Model CM,
99 CodeGenOpt::Level OL)
100 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
101 }
102