1 //===-- SerialSnippetGenerator.cpp ------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "SerialSnippetGenerator.h" 10 11 #include "CodeTemplate.h" 12 #include "MCInstrDescView.h" 13 #include "Target.h" 14 #include <algorithm> 15 #include <numeric> 16 #include <vector> 17 18 namespace llvm { 19 namespace exegesis { 20 21 struct ExecutionClass { 22 ExecutionMode Mask; 23 const char *Description; 24 } static const kExecutionClasses[] = { 25 {ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS | 26 ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS, 27 "Repeating a single implicitly serial instruction"}, 28 {ExecutionMode::SERIAL_VIA_EXPLICIT_REGS, 29 "Repeating a single explicitly serial instruction"}, 30 {ExecutionMode::SERIAL_VIA_MEMORY_INSTR | 31 ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR, 32 "Repeating two instructions"}, 33 }; 34 35 static constexpr size_t kMaxAliasingInstructions = 10; 36 37 static std::vector<const Instruction *> 38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr, 39 size_t MaxAliasingInstructions, 40 const BitVector &ForbiddenRegisters) { 41 const auto &ET = State.getExegesisTarget(); 42 const auto AvailableFeatures = State.getSubtargetInfo().getFeatureBits(); 43 // Randomly iterate the set of instructions. 44 std::vector<unsigned> Opcodes; 45 Opcodes.resize(State.getInstrInfo().getNumOpcodes()); 46 std::iota(Opcodes.begin(), Opcodes.end(), 0U); 47 llvm::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator()); 48 49 std::vector<const Instruction *> AliasingInstructions; 50 for (const unsigned OtherOpcode : Opcodes) { 51 if (!ET.isOpcodeAvailable(OtherOpcode, AvailableFeatures)) 52 continue; 53 if (OtherOpcode == Instr->Description.getOpcode()) 54 continue; 55 const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode); 56 if (OtherInstr.hasMemoryOperands()) 57 continue; 58 if (!ET.allowAsBackToBack(OtherInstr)) 59 continue; 60 if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters)) 61 AliasingInstructions.push_back(&OtherInstr); 62 if (AliasingInstructions.size() >= MaxAliasingInstructions) 63 break; 64 } 65 return AliasingInstructions; 66 } 67 68 static ExecutionMode getExecutionModes(const Instruction &Instr, 69 const BitVector &ForbiddenRegisters) { 70 ExecutionMode EM = ExecutionMode::UNKNOWN; 71 if (Instr.hasAliasingImplicitRegisters()) 72 EM |= ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS; 73 if (Instr.hasTiedRegisters()) 74 EM |= ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS; 75 if (Instr.hasMemoryOperands()) 76 EM |= ExecutionMode::SERIAL_VIA_MEMORY_INSTR; 77 if (Instr.hasAliasingNotMemoryRegisters(ForbiddenRegisters)) 78 EM |= ExecutionMode::SERIAL_VIA_EXPLICIT_REGS; 79 if (Instr.hasOneUseOrOneDef()) 80 EM |= ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR; 81 return EM; 82 } 83 84 static void appendCodeTemplates(const LLVMState &State, 85 InstructionTemplate Variant, 86 const BitVector &ForbiddenRegisters, 87 ExecutionMode ExecutionModeBit, 88 StringRef ExecutionClassDescription, 89 std::vector<CodeTemplate> &CodeTemplates) { 90 assert(isEnumValue(ExecutionModeBit) && "Bit must be a power of two"); 91 switch (ExecutionModeBit) { 92 case ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS: 93 // Nothing to do, the instruction is always serial. 94 [[fallthrough]]; 95 case ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS: { 96 // Picking whatever value for the tied variable will make the instruction 97 // serial. 98 CodeTemplate CT; 99 CT.Execution = ExecutionModeBit; 100 CT.Info = std::string(ExecutionClassDescription); 101 CT.Instructions.push_back(std::move(Variant)); 102 CodeTemplates.push_back(std::move(CT)); 103 return; 104 } 105 case ExecutionMode::SERIAL_VIA_MEMORY_INSTR: { 106 // Select back-to-back memory instruction. 107 // TODO: Implement me. 108 return; 109 } 110 case ExecutionMode::SERIAL_VIA_EXPLICIT_REGS: { 111 // Making the execution of this instruction serial by selecting one def 112 // register to alias with one use register. 113 const AliasingConfigurations SelfAliasing( 114 Variant.getInstr(), Variant.getInstr(), ForbiddenRegisters); 115 assert(!SelfAliasing.empty() && !SelfAliasing.hasImplicitAliasing() && 116 "Instr must alias itself explicitly"); 117 // This is a self aliasing instruction so defs and uses are from the same 118 // instance, hence twice Variant in the following call. 119 setRandomAliasing(SelfAliasing, Variant, Variant); 120 CodeTemplate CT; 121 CT.Execution = ExecutionModeBit; 122 CT.Info = std::string(ExecutionClassDescription); 123 CT.Instructions.push_back(std::move(Variant)); 124 CodeTemplates.push_back(std::move(CT)); 125 return; 126 } 127 case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR: { 128 const Instruction &Instr = Variant.getInstr(); 129 // Select back-to-back non-memory instruction. 130 for (const auto *OtherInstr : computeAliasingInstructions( 131 State, &Instr, kMaxAliasingInstructions, ForbiddenRegisters)) { 132 const AliasingConfigurations Forward(Instr, *OtherInstr, 133 ForbiddenRegisters); 134 const AliasingConfigurations Back(*OtherInstr, Instr, ForbiddenRegisters); 135 InstructionTemplate ThisIT(Variant); 136 InstructionTemplate OtherIT(OtherInstr); 137 if (!Forward.hasImplicitAliasing()) 138 setRandomAliasing(Forward, ThisIT, OtherIT); 139 else if (!Back.hasImplicitAliasing()) 140 setRandomAliasing(Back, OtherIT, ThisIT); 141 CodeTemplate CT; 142 CT.Execution = ExecutionModeBit; 143 CT.Info = std::string(ExecutionClassDescription); 144 CT.Instructions.push_back(std::move(ThisIT)); 145 CT.Instructions.push_back(std::move(OtherIT)); 146 CodeTemplates.push_back(std::move(CT)); 147 } 148 return; 149 } 150 default: 151 llvm_unreachable("Unhandled enum value"); 152 } 153 } 154 155 SerialSnippetGenerator::~SerialSnippetGenerator() = default; 156 157 Expected<std::vector<CodeTemplate>> 158 SerialSnippetGenerator::generateCodeTemplates( 159 InstructionTemplate Variant, const BitVector &ForbiddenRegisters) const { 160 std::vector<CodeTemplate> Results; 161 const ExecutionMode EM = 162 getExecutionModes(Variant.getInstr(), ForbiddenRegisters); 163 for (const auto EC : kExecutionClasses) { 164 for (const auto ExecutionModeBit : getExecutionModeBits(EM & EC.Mask)) 165 appendCodeTemplates(State, Variant, ForbiddenRegisters, ExecutionModeBit, 166 EC.Description, Results); 167 if (!Results.empty()) 168 break; 169 } 170 if (Results.empty()) 171 return make_error<Failure>( 172 "No strategy found to make the execution serial"); 173 return std::move(Results); 174 } 175 176 } // namespace exegesis 177 } // namespace llvm 178