1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// SI DAG Lowering interface definition 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 15 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H 16 17 #include "AMDGPUISelLowering.h" 18 #include "AMDGPUArgumentUsageInfo.h" 19 20 namespace llvm { 21 22 class GCNSubtarget; 23 class SIMachineFunctionInfo; 24 class SIRegisterInfo; 25 26 namespace AMDGPU { 27 struct ImageDimIntrinsicInfo; 28 } 29 30 class SITargetLowering final : public AMDGPUTargetLowering { 31 private: 32 const GCNSubtarget *Subtarget; 33 34 public: 35 MVT getRegisterTypeForCallingConv(LLVMContext &Context, 36 CallingConv::ID CC, 37 EVT VT) const override; 38 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 39 CallingConv::ID CC, 40 EVT VT) const override; 41 42 unsigned getVectorTypeBreakdownForCallingConv( 43 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, 44 unsigned &NumIntermediates, MVT &RegisterVT) const override; 45 46 private: 47 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL, 48 SDValue Chain, uint64_t Offset) const; 49 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const; 50 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, 51 const SDLoc &SL, SDValue Chain, 52 uint64_t Offset, Align Alignment, 53 bool Signed, 54 const ISD::InputArg *Arg = nullptr) const; 55 56 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, 57 const SDLoc &SL, SDValue Chain, 58 const ISD::InputArg &Arg) const; 59 SDValue getPreloadedValue(SelectionDAG &DAG, 60 const SIMachineFunctionInfo &MFI, 61 EVT VT, 62 AMDGPUFunctionArgInfo::PreloadedValue) const; 63 64 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 65 SelectionDAG &DAG) const override; 66 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 67 MVT VT, unsigned Offset) const; 68 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr, 69 SelectionDAG &DAG, bool WithChain) const; 70 SDValue lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc, SDValue Offset, 71 SDValue CachePolicy, SelectionDAG &DAG) const; 72 73 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 74 unsigned NewOpcode) const; 75 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG, 76 unsigned NewOpcode) const; 77 78 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 79 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 80 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 81 82 // The raw.tbuffer and struct.tbuffer intrinsics have two offset args: offset 83 // (the offset that is included in bounds checking and swizzling, to be split 84 // between the instruction's voffset and immoffset fields) and soffset (the 85 // offset that is excluded from bounds checking and swizzling, to go in the 86 // instruction's soffset field). This function takes the first kind of 87 // offset and figures out how to split it between voffset and immoffset. 88 std::pair<SDValue, SDValue> splitBufferOffsets(SDValue Offset, 89 SelectionDAG &DAG) const; 90 91 SDValue widenLoad(LoadSDNode *Ld, DAGCombinerInfo &DCI) const; 92 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 93 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 94 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const; 95 SDValue lowerFastUnsafeFDIV64(SDValue Op, SelectionDAG &DAG) const; 96 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const; 97 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const; 98 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 99 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 100 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 101 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 102 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 103 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 104 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 105 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 106 SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M, 107 SelectionDAG &DAG, ArrayRef<SDValue> Ops, 108 bool IsIntrinsic = false) const; 109 110 SDValue lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, 111 ArrayRef<SDValue> Ops) const; 112 113 // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to 114 // dwordx4 if on SI. 115 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, 116 ArrayRef<SDValue> Ops, EVT MemVT, 117 MachineMemOperand *MMO, SelectionDAG &DAG) const; 118 119 SDValue handleD16VData(SDValue VData, SelectionDAG &DAG, 120 bool ImageStore = false) const; 121 122 /// Converts \p Op, which must be of floating point type, to the 123 /// floating point type \p VT, by either extending or truncating it. 124 SDValue getFPExtOrFPRound(SelectionDAG &DAG, 125 SDValue Op, 126 const SDLoc &DL, 127 EVT VT) const; 128 129 SDValue convertArgType( 130 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, 131 bool Signed, const ISD::InputArg *Arg = nullptr) const; 132 133 /// Custom lowering for ISD::FP_ROUND for MVT::f16. 134 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 135 SDValue lowerFMINNUM_FMAXNUM(SDValue Op, SelectionDAG &DAG) const; 136 SDValue lowerXMULO(SDValue Op, SelectionDAG &DAG) const; 137 138 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL, 139 SelectionDAG &DAG) const; 140 141 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const; 142 SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 143 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 144 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 145 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 146 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 147 148 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const; 149 SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const; 150 SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const; 151 SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const; 152 SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const; 153 154 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 155 156 SDValue performUCharToFloatCombine(SDNode *N, 157 DAGCombinerInfo &DCI) const; 158 SDValue performSHLPtrCombine(SDNode *N, 159 unsigned AS, 160 EVT MemVT, 161 DAGCombinerInfo &DCI) const; 162 163 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const; 164 165 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL, 166 unsigned Opc, SDValue LHS, 167 const ConstantSDNode *CRHS) const; 168 169 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 170 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 171 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const; 172 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const; 173 SDValue performSignExtendInRegCombine(SDNode *N, DAGCombinerInfo &DCI) const; 174 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 175 SDValue getCanonicalConstantFP(SelectionDAG &DAG, const SDLoc &SL, EVT VT, 176 const APFloat &C) const; 177 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const; 178 179 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 180 SDValue Op0, SDValue Op1) const; 181 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, 182 SDValue Op0, SDValue Op1, bool Signed) const; 183 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const; 184 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 185 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const; 186 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 187 SDValue performInsertVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const; 188 189 SDValue reassociateScalarOps(SDNode *N, SelectionDAG &DAG) const; 190 unsigned getFusedOpcode(const SelectionDAG &DAG, 191 const SDNode *N0, const SDNode *N1) const; 192 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 193 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const; 194 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 195 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const; 196 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const; 197 SDValue performFMACombine(SDNode *N, DAGCombinerInfo &DCI) const; 198 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 199 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const; 200 SDValue performClampCombine(SDNode *N, DAGCombinerInfo &DCI) const; 201 SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const; 202 203 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 204 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 205 206 unsigned isCFIntrinsic(const SDNode *Intr) const; 207 208 public: 209 /// \returns True if fixup needs to be emitted for given global value \p GV, 210 /// false otherwise. 211 bool shouldEmitFixup(const GlobalValue *GV) const; 212 213 /// \returns True if GOT relocation needs to be emitted for given global value 214 /// \p GV, false otherwise. 215 bool shouldEmitGOTReloc(const GlobalValue *GV) const; 216 217 /// \returns True if PC-relative relocation needs to be emitted for given 218 /// global value \p GV, false otherwise. 219 bool shouldEmitPCReloc(const GlobalValue *GV) const; 220 221 /// \returns true if this should use a literal constant for an LDS address, 222 /// and not emit a relocation for an LDS global. 223 bool shouldUseLDSConstAddress(const GlobalValue *GV) const; 224 225 /// Check if EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT (<n x e>, var-idx) should be 226 /// expanded into a set of cmp/select instructions. 227 static bool shouldExpandVectorDynExt(unsigned EltSize, unsigned NumElem, 228 bool IsDivergentIdx); 229 230 private: 231 // Analyze a combined offset from an amdgcn_buffer_ intrinsic and store the 232 // three offsets (voffset, soffset and instoffset) into the SDValue[3] array 233 // pointed to by Offsets. 234 /// \returns 0 If there is a non-constant offset or if the offset is 0. 235 /// Otherwise returns the constant offset. 236 unsigned setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, 237 SDValue *Offsets, Align Alignment = Align(4)) const; 238 239 // Handle 8 bit and 16 bit buffer loads 240 SDValue handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, 241 ArrayRef<SDValue> Ops, MemSDNode *M) const; 242 243 // Handle 8 bit and 16 bit buffer stores 244 SDValue handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, 245 SDLoc DL, SDValue Ops[], 246 MemSDNode *M) const; 247 248 public: 249 SITargetLowering(const TargetMachine &tm, const GCNSubtarget &STI); 250 251 const GCNSubtarget *getSubtarget() const; 252 253 bool isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, EVT DestVT, 254 EVT SrcVT) const override; 255 256 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override; 257 258 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, 259 MachineFunction &MF, 260 unsigned IntrinsicID) const override; 261 262 bool getAddrModeArguments(IntrinsicInst * /*I*/, 263 SmallVectorImpl<Value*> &/*Ops*/, 264 Type *&/*AccessTy*/) const override; 265 266 bool isLegalGlobalAddressingMode(const AddrMode &AM) const; 267 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 268 unsigned AS, 269 Instruction *I = nullptr) const override; 270 271 bool canMergeStoresTo(unsigned AS, EVT MemVT, 272 const SelectionDAG &DAG) const override; 273 274 bool allowsMisalignedMemoryAccessesImpl( 275 unsigned Size, unsigned AddrSpace, Align Alignment, 276 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 277 bool *IsFast = nullptr) const; 278 279 bool allowsMisalignedMemoryAccesses( 280 LLT Ty, unsigned AddrSpace, Align Alignment, 281 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 282 bool *IsFast = nullptr) const override { 283 if (IsFast) 284 *IsFast = false; 285 return allowsMisalignedMemoryAccessesImpl(Ty.getSizeInBits(), AddrSpace, 286 Alignment, Flags, IsFast); 287 } 288 289 bool allowsMisalignedMemoryAccesses( 290 EVT VT, unsigned AS, Align Alignment, 291 MachineMemOperand::Flags Flags = MachineMemOperand::MONone, 292 bool *IsFast = nullptr) const override; 293 294 EVT getOptimalMemOpType(const MemOp &Op, 295 const AttributeList &FuncAttributes) const override; 296 297 bool isMemOpUniform(const SDNode *N) const; 298 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const; 299 300 static bool isNonGlobalAddrSpace(unsigned AS); 301 302 bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 303 304 TargetLoweringBase::LegalizeTypeAction 305 getPreferredVectorAction(MVT VT) const override; 306 307 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 308 Type *Ty) const override; 309 310 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override; 311 312 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 313 314 bool supportSplitCSR(MachineFunction *MF) const override; 315 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 316 void insertCopiesSplitCSR( 317 MachineBasicBlock *Entry, 318 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 319 320 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 321 bool isVarArg, 322 const SmallVectorImpl<ISD::InputArg> &Ins, 323 const SDLoc &DL, SelectionDAG &DAG, 324 SmallVectorImpl<SDValue> &InVals) const override; 325 326 bool CanLowerReturn(CallingConv::ID CallConv, 327 MachineFunction &MF, bool isVarArg, 328 const SmallVectorImpl<ISD::OutputArg> &Outs, 329 LLVMContext &Context) const override; 330 331 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, 332 const SmallVectorImpl<ISD::OutputArg> &Outs, 333 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL, 334 SelectionDAG &DAG) const override; 335 336 void passSpecialInputs( 337 CallLoweringInfo &CLI, 338 CCState &CCInfo, 339 const SIMachineFunctionInfo &Info, 340 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, 341 SmallVectorImpl<SDValue> &MemOpChains, 342 SDValue Chain) const; 343 344 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 345 CallingConv::ID CallConv, bool isVarArg, 346 const SmallVectorImpl<ISD::InputArg> &Ins, 347 const SDLoc &DL, SelectionDAG &DAG, 348 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 349 SDValue ThisVal) const; 350 351 bool mayBeEmittedAsTailCall(const CallInst *) const override; 352 353 bool isEligibleForTailCallOptimization( 354 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 355 const SmallVectorImpl<ISD::OutputArg> &Outs, 356 const SmallVectorImpl<SDValue> &OutVals, 357 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const; 358 359 SDValue LowerCall(CallLoweringInfo &CLI, 360 SmallVectorImpl<SDValue> &InVals) const override; 361 362 SDValue lowerDYNAMIC_STACKALLOCImpl(SDValue Op, SelectionDAG &DAG) const; 363 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 364 365 Register getRegisterByName(const char* RegName, LLT VT, 366 const MachineFunction &MF) const override; 367 368 MachineBasicBlock *splitKillBlock(MachineInstr &MI, 369 MachineBasicBlock *BB) const; 370 371 void bundleInstWithWaitcnt(MachineInstr &MI) const; 372 MachineBasicBlock *emitGWSMemViolTestLoop(MachineInstr &MI, 373 MachineBasicBlock *BB) const; 374 375 MachineBasicBlock * 376 EmitInstrWithCustomInserter(MachineInstr &MI, 377 MachineBasicBlock *BB) const override; 378 379 bool hasBitPreservingFPLogic(EVT VT) const override; 380 bool enableAggressiveFMAFusion(EVT VT) const override; 381 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 382 EVT VT) const override; 383 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 384 LLT getPreferredShiftAmountTy(LLT Ty) const override; 385 386 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 387 EVT VT) const override; 388 bool isFMADLegal(const SelectionDAG &DAG, const SDNode *N) const override; 389 390 SDValue splitUnaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 391 SDValue splitBinaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 392 SDValue splitTernaryVectorOp(SDValue Op, SelectionDAG &DAG) const; 393 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 394 395 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, 396 SelectionDAG &DAG) const override; 397 398 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 399 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 400 void AddIMGInit(MachineInstr &MI) const; 401 void AdjustInstrPostInstrSelection(MachineInstr &MI, 402 SDNode *Node) const override; 403 404 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 405 406 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, 407 SDValue Ptr) const; 408 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, 409 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const; 410 std::pair<unsigned, const TargetRegisterClass *> 411 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 412 StringRef Constraint, MVT VT) const override; 413 ConstraintType getConstraintType(StringRef Constraint) const override; 414 void LowerAsmOperandForConstraint(SDValue Op, 415 std::string &Constraint, 416 std::vector<SDValue> &Ops, 417 SelectionDAG &DAG) const override; 418 bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; 419 bool checkAsmConstraintVal(SDValue Op, 420 const std::string &Constraint, 421 uint64_t Val) const; 422 bool checkAsmConstraintValA(SDValue Op, 423 uint64_t Val, 424 unsigned MaxSize = 64) const; 425 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, 426 SDValue V) const; 427 428 void finalizeLowering(MachineFunction &MF) const override; 429 430 void computeKnownBitsForFrameIndex(int FrameIdx, 431 KnownBits &Known, 432 const MachineFunction &MF) const override; 433 void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis, Register R, 434 KnownBits &Known, 435 const APInt &DemandedElts, 436 const MachineRegisterInfo &MRI, 437 unsigned Depth = 0) const override; 438 439 Align computeKnownAlignForTargetInstr(GISelKnownBits &Analysis, Register R, 440 const MachineRegisterInfo &MRI, 441 unsigned Depth = 0) const override; 442 bool isSDNodeSourceOfDivergence(const SDNode *N, 443 FunctionLoweringInfo *FLI, LegacyDivergenceAnalysis *DA) const override; 444 445 bool isCanonicalized(SelectionDAG &DAG, SDValue Op, 446 unsigned MaxDepth = 5) const; 447 bool isCanonicalized(Register Reg, MachineFunction &MF, 448 unsigned MaxDepth = 5) const; 449 bool denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const; 450 bool denormalsEnabledForType(LLT Ty, MachineFunction &MF) const; 451 452 bool isKnownNeverNaNForTargetNode(SDValue Op, 453 const SelectionDAG &DAG, 454 bool SNaN = false, 455 unsigned Depth = 0) const override; 456 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override; 457 458 virtual const TargetRegisterClass * 459 getRegClassFor(MVT VT, bool isDivergent) const override; 460 virtual bool requiresUniformRegister(MachineFunction &MF, 461 const Value *V) const override; 462 Align getPrefLoopAlignment(MachineLoop *ML) const override; 463 464 void allocateHSAUserSGPRs(CCState &CCInfo, 465 MachineFunction &MF, 466 const SIRegisterInfo &TRI, 467 SIMachineFunctionInfo &Info) const; 468 469 void allocateSystemSGPRs(CCState &CCInfo, 470 MachineFunction &MF, 471 SIMachineFunctionInfo &Info, 472 CallingConv::ID CallConv, 473 bool IsShader) const; 474 475 void allocateSpecialEntryInputVGPRs(CCState &CCInfo, 476 MachineFunction &MF, 477 const SIRegisterInfo &TRI, 478 SIMachineFunctionInfo &Info) const; 479 void allocateSpecialInputSGPRs( 480 CCState &CCInfo, 481 MachineFunction &MF, 482 const SIRegisterInfo &TRI, 483 SIMachineFunctionInfo &Info) const; 484 485 void allocateSpecialInputVGPRs(CCState &CCInfo, 486 MachineFunction &MF, 487 const SIRegisterInfo &TRI, 488 SIMachineFunctionInfo &Info) const; 489 void allocateSpecialInputVGPRsFixed(CCState &CCInfo, 490 MachineFunction &MF, 491 const SIRegisterInfo &TRI, 492 SIMachineFunctionInfo &Info) const; 493 494 std::pair<InstructionCost, MVT> getTypeLegalizationCost(const DataLayout &DL, 495 Type *Ty) const; 496 }; 497 498 } // End namespace llvm 499 500 #endif 501