xref: /llvm-project/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp (revision bb3f5e1fed7c6ba733b7f273e93f5d3930976185)
1 //===-- R600TargetMachine.cpp - TargetMachine for hw codegen targets-------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file contains both AMDGPU-R600 target machine and the CodeGen pass
11 /// builder. The target machine contains all of the hardware specific
12 /// information needed to emit code for R600 GPUs and the CodeGen pass builder
13 /// handles the pass pipeline for new pass manager.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "R600TargetMachine.h"
18 #include "R600.h"
19 #include "R600MachineFunctionInfo.h"
20 #include "R600MachineScheduler.h"
21 #include "R600TargetTransformInfo.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include <optional>
24 
25 using namespace llvm;
26 
27 static cl::opt<bool>
28     EnableR600StructurizeCFG("r600-ir-structurize",
29                              cl::desc("Use StructurizeCFG IR pass"),
30                              cl::init(true));
31 
32 static cl::opt<bool> EnableR600IfConvert("r600-if-convert",
33                                          cl::desc("Use if conversion pass"),
34                                          cl::ReallyHidden, cl::init(true));
35 
36 static cl::opt<bool, true> EnableAMDGPUFunctionCallsOpt(
37     "amdgpu-function-calls", cl::desc("Enable AMDGPU function call support"),
38     cl::location(AMDGPUTargetMachine::EnableFunctionCalls), cl::init(true),
39     cl::Hidden);
40 
41 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
42   return new ScheduleDAGMILive(C, std::make_unique<R600SchedStrategy>());
43 }
44 
45 static MachineSchedRegistry R600SchedRegistry("r600",
46                                               "Run R600's custom scheduler",
47                                               createR600MachineScheduler);
48 
49 //===----------------------------------------------------------------------===//
50 // R600 Target Machine (R600 -> Cayman)
51 //===----------------------------------------------------------------------===//
52 
53 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
54                                      StringRef CPU, StringRef FS,
55                                      const TargetOptions &Options,
56                                      std::optional<Reloc::Model> RM,
57                                      std::optional<CodeModel::Model> CM,
58                                      CodeGenOptLevel OL, bool JIT)
59     : AMDGPUTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
60   setRequiresStructuredCFG(true);
61 
62   // Override the default since calls aren't supported for r600.
63   if (EnableFunctionCalls &&
64       EnableAMDGPUFunctionCallsOpt.getNumOccurrences() == 0)
65     EnableFunctionCalls = false;
66 }
67 
68 const TargetSubtargetInfo *
69 R600TargetMachine::getSubtargetImpl(const Function &F) const {
70   StringRef GPU = getGPUName(F);
71   StringRef FS = getFeatureString(F);
72 
73   SmallString<128> SubtargetKey(GPU);
74   SubtargetKey.append(FS);
75 
76   auto &I = SubtargetMap[SubtargetKey];
77   if (!I) {
78     // This needs to be done before we create a new subtarget since any
79     // creation will depend on the TM and the code generation flags on the
80     // function that reside in TargetOptions.
81     resetTargetOptions(F);
82     I = std::make_unique<R600Subtarget>(TargetTriple, GPU, FS, *this);
83   }
84 
85   return I.get();
86 }
87 
88 TargetTransformInfo
89 R600TargetMachine::getTargetTransformInfo(const Function &F) const {
90   return TargetTransformInfo(R600TTIImpl(this, F));
91 }
92 
93 namespace {
94 class R600PassConfig final : public AMDGPUPassConfig {
95 public:
96   R600PassConfig(TargetMachine &TM, PassManagerBase &PM)
97       : AMDGPUPassConfig(TM, PM) {}
98 
99   ScheduleDAGInstrs *
100   createMachineScheduler(MachineSchedContext *C) const override {
101     return createR600MachineScheduler(C);
102   }
103 
104   bool addPreISel() override;
105   bool addInstSelector() override;
106   void addPreRegAlloc() override;
107   void addPreSched2() override;
108   void addPreEmitPass() override;
109 };
110 } // namespace
111 
112 //===----------------------------------------------------------------------===//
113 // R600 Pass Setup
114 //===----------------------------------------------------------------------===//
115 
116 bool R600PassConfig::addPreISel() {
117   AMDGPUPassConfig::addPreISel();
118 
119   if (EnableR600StructurizeCFG)
120     addPass(createStructurizeCFGPass());
121   return false;
122 }
123 
124 bool R600PassConfig::addInstSelector() {
125   addPass(createR600ISelDag(getAMDGPUTargetMachine(), getOptLevel()));
126   return false;
127 }
128 
129 void R600PassConfig::addPreRegAlloc() { addPass(createR600VectorRegMerger()); }
130 
131 void R600PassConfig::addPreSched2() {
132   addPass(createR600EmitClauseMarkers());
133   if (EnableR600IfConvert)
134     addPass(&IfConverterID);
135   addPass(createR600ClauseMergePass());
136 }
137 
138 void R600PassConfig::addPreEmitPass() {
139   addPass(createR600MachineCFGStructurizerPass());
140   addPass(createR600ExpandSpecialInstrsPass());
141   addPass(&FinalizeMachineBundlesID);
142   addPass(createR600Packetizer());
143   addPass(createR600ControlFlowFinalizer());
144 }
145 
146 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
147   return new R600PassConfig(*this, PM);
148 }
149 
150 Error R600TargetMachine::buildCodeGenPipeline(
151     ModulePassManager &MPM, raw_pwrite_stream &Out, raw_pwrite_stream *DwoOut,
152     CodeGenFileType FileType, const CGPassBuilderOption &Opts,
153     PassInstrumentationCallbacks *PIC) {
154   R600CodeGenPassBuilder CGPB(*this, Opts, PIC);
155   return CGPB.buildPipeline(MPM, Out, DwoOut, FileType);
156 }
157 
158 MachineFunctionInfo *R600TargetMachine::createMachineFunctionInfo(
159     BumpPtrAllocator &Allocator, const Function &F,
160     const TargetSubtargetInfo *STI) const {
161   return R600MachineFunctionInfo::create<R600MachineFunctionInfo>(
162       Allocator, F, static_cast<const R600Subtarget *>(STI));
163 }
164 
165 //===----------------------------------------------------------------------===//
166 // R600 CodeGen Pass Builder interface.
167 //===----------------------------------------------------------------------===//
168 
169 R600CodeGenPassBuilder::R600CodeGenPassBuilder(
170     R600TargetMachine &TM, const CGPassBuilderOption &Opts,
171     PassInstrumentationCallbacks *PIC)
172     : CodeGenPassBuilder(TM, Opts, PIC) {
173   Opt.RequiresCodeGenSCCOrder = true;
174 }
175 
176 void R600CodeGenPassBuilder::addPreISel(AddIRPass &addPass) const {
177   // TODO: Add passes pre instruction selection.
178 }
179 
180 void R600CodeGenPassBuilder::addAsmPrinter(AddMachinePass &addPass,
181                                            CreateMCStreamer) const {
182   // TODO: Add AsmPrinter.
183 }
184 
185 Error R600CodeGenPassBuilder::addInstSelector(AddMachinePass &) const {
186   // TODO: Add instruction selector.
187   return Error::success();
188 }
189