1 //===-- ProcfsTests.cpp ---------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "Procfs.h"
10
11 #include "lldb/Host/linux/Support.h"
12
13 #include "gmock/gmock.h"
14 #include "gtest/gtest.h"
15
16 using namespace lldb_private;
17 using namespace process_linux;
18 using namespace llvm;
19
TEST(Perf,HardcodedLogicalCoreIDs)20 TEST(Perf, HardcodedLogicalCoreIDs) {
21 Expected<std::vector<lldb::cpu_id_t>> cpu_ids =
22 GetAvailableLogicalCoreIDs(R"(processor : 13
23 vendor_id : GenuineIntel
24 cpu family : 6
25 model : 85
26 model name : Intel(R) Xeon(R) Gold 6138 CPU @ 2.00GHz
27 stepping : 4
28 microcode : 0x2000065
29 cpu MHz : 2886.370
30 cache size : 28160 KB
31 physical id : 1
32 siblings : 40
33 core id : 19
34 cpu cores : 20
35 apicid : 103
36 initial apicid : 103
37 fpu : yes
38 fpu_exception : yes
39 cpuid level : 22
40 power management:
41
42 processor : 24
43 vendor_id : GenuineIntel
44 cpu family : 6
45 model : 85
46 model name : Intel(R) Xeon(R) Gold 6138 CPU @ 2.00GHz
47 stepping : 4
48 microcode : 0x2000065
49 cpu MHz : 2768.494
50 cache size : 28160 KB
51 physical id : 1
52 siblings : 40
53 core id : 20
54 cpu cores : 20
55 apicid : 105
56 power management:
57
58 processor : 35
59 vendor_id : GenuineIntel
60 cpu family : 6
61 model : 85
62 model name : Intel(R) Xeon(R) Gold 6138 CPU @ 2.00GHz
63 stepping : 4
64 microcode : 0x2000065
65 cpu MHz : 2884.703
66 cache size : 28160 KB
67 physical id : 1
68 siblings : 40
69 core id : 24
70 cpu cores : 20
71 apicid : 113
72
73 processor : 79
74 vendor_id : GenuineIntel
75 cpu family : 6
76 model : 85
77 model name : Intel(R) Xeon(R) Gold 6138 CPU @ 2.00GHz
78 stepping : 4
79 microcode : 0x2000065
80 cpu MHz : 3073.955
81 cache size : 28160 KB
82 physical id : 1
83 siblings : 40
84 core id : 28
85 cpu cores : 20
86 apicid : 121
87 power management:
88 )");
89
90 ASSERT_TRUE((bool)cpu_ids);
91 ASSERT_THAT(*cpu_ids, ::testing::ElementsAre(13, 24, 35, 79));
92 }
93
TEST(Perf,RealLogicalCoreIDs)94 TEST(Perf, RealLogicalCoreIDs) {
95 // We first check we can read /proc/cpuinfo
96 auto buffer_or_error = errorOrToExpected(getProcFile("cpuinfo"));
97 if (!buffer_or_error)
98 GTEST_SKIP() << toString(buffer_or_error.takeError());
99
100 // At this point we shouldn't fail parsing the core ids
101 Expected<ArrayRef<lldb::cpu_id_t>> cpu_ids = GetAvailableLogicalCoreIDs();
102 ASSERT_TRUE((bool)cpu_ids);
103 ASSERT_GT((int)cpu_ids->size(), 0) << "We must see at least one core";
104 }
105
TEST(Perf,RealPtraceScope)106 TEST(Perf, RealPtraceScope) {
107 // We first check we can read /proc/sys/kernel/yama/ptrace_scope
108 auto buffer_or_error =
109 errorOrToExpected(getProcFile("sys/kernel/yama/ptrace_scope"));
110 if (!buffer_or_error)
111 GTEST_SKIP() << toString(buffer_or_error.takeError());
112
113 // At this point we shouldn't fail parsing the ptrace_scope value.
114 Expected<int> ptrace_scope = GetPtraceScope();
115 ASSERT_TRUE((bool)ptrace_scope) << ptrace_scope.takeError();
116 ASSERT_GE(*ptrace_scope, 0)
117 << "Sensible values of ptrace_scope are between 0 and 3";
118 ASSERT_LE(*ptrace_scope, 3)
119 << "Sensible values of ptrace_scope are between 0 and 3";
120 }
121