1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is the top level entry point for the PowerPC target. 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing. 14// 15include "llvm/Target/Target.td" 16 17//===----------------------------------------------------------------------===// 18// PowerPC Subtarget features. 19// 20 21//===----------------------------------------------------------------------===// 22// CPU Directives // 23//===----------------------------------------------------------------------===// 24 25def Directive440 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_440", "">; 26def Directive601 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_601", "">; 27def Directive602 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_602", "">; 28def Directive603 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 29def Directive604 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 30def Directive620 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_603", "">; 31def Directive7400: SubtargetFeature<"", "CPUDirective", "PPC::DIR_7400", "">; 32def Directive750 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_750", "">; 33def Directive970 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_970", "">; 34def Directive32 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_32", "">; 35def Directive64 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_64", "">; 36def DirectiveA2 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_A2", "">; 37def DirectiveE500 : SubtargetFeature<"", "CPUDirective", 38 "PPC::DIR_E500", "">; 39def DirectiveE500mc : SubtargetFeature<"", "CPUDirective", 40 "PPC::DIR_E500mc", "">; 41def DirectiveE5500 : SubtargetFeature<"", "CPUDirective", 42 "PPC::DIR_E5500", "">; 43def DirectivePwr3: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR3", "">; 44def DirectivePwr4: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR4", "">; 45def DirectivePwr5: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5", "">; 46def DirectivePwr5x 47 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR5X", "">; 48def DirectivePwr6: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6", "">; 49def DirectivePwr6x 50 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR6X", "">; 51def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; 52def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; 53def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; 54def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; 55def DirectivePwrFuture 56 : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; 57 58def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true", 59 "Enable 64-bit instructions">; 60def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">; 61def FeatureModernAIXAs 62 : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true", 63 "AIX system assembler is modern enough to support new mnes">; 64def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true", 65 "Enable floating-point instructions">; 66def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", 67 "Enable 64-bit registers usage for ppc32 [beta]">; 68def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", 69 "Use condition-register bits individually">; 70def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", 71 "Enable classic FPU instructions", 72 [FeatureHardFloat]>; 73def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true", 74 "Enable Altivec instructions", 75 [FeatureFPU]>; 76def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true", 77 "Enable SPE instructions", 78 [FeatureHardFloat]>; 79def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true", 80 "Enable Embedded Floating-Point APU 2 instructions", 81 [FeatureSPE]>; 82def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true", 83 "Enable the MFOCRF instruction">; 84def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true", 85 "Enable the fsqrt instruction", 86 [FeatureFPU]>; 87def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true", 88 "Enable the fcpsgn instruction", 89 [FeatureFPU]>; 90def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true", 91 "Enable the fre instruction", 92 [FeatureFPU]>; 93def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true", 94 "Enable the fres instruction", 95 [FeatureFPU]>; 96def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true", 97 "Enable the frsqrte instruction", 98 [FeatureFPU]>; 99def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true", 100 "Enable the frsqrtes instruction", 101 [FeatureFPU]>; 102def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true", 103 "Assume higher precision reciprocal estimates">; 104def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", 105 "Enable the stfiwx instruction", 106 [FeatureFPU]>; 107def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true", 108 "Enable the lfiwax instruction", 109 [FeatureFPU]>; 110def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true", 111 "Enable the fri[mnpz] instructions", 112 [FeatureFPU]>; 113def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true", 114 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions", 115 [FeatureFPU]>; 116def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", 117 "Enable the isel instruction">; 118def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true", 119 "Enable the bpermd instruction">; 120def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true", 121 "Enable extended divide instructions">; 122def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true", 123 "Enable the ldbrx instruction">; 124def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true", 125 "Enable the cmpb instruction">; 126def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true", 127 "Enable icbt instruction">; 128def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", 129 "Enable Book E instructions", 130 [FeatureICBT]>; 131def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true", 132 "Has only the msync instruction instead of sync", 133 [FeatureBookE]>; 134def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true", 135 "Enable E500/E500mc instructions">; 136def FeatureSecurePlt : SubtargetFeature<"secure-plt","SecurePlt", "true", 137 "Enable secure plt mode">; 138def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true", 139 "Enable PPC 4xx instructions">; 140def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true", 141 "Enable PPC 6xx instructions">; 142def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true", 143 "Enable VSX instructions", 144 [FeatureAltivec]>; 145def FeatureTwoConstNR : 146 SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true", 147 "Requires two constant Newton-Raphson computation">; 148def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true", 149 "Enable POWER8 Altivec instructions", 150 [FeatureAltivec]>; 151def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true", 152 "Enable POWER8 Crypto instructions", 153 [FeatureP8Altivec]>; 154def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true", 155 "Enable POWER8 vector instructions", 156 [FeatureVSX, FeatureP8Altivec]>; 157def FeatureDirectMove : 158 SubtargetFeature<"direct-move", "HasDirectMove", "true", 159 "Enable Power8 direct move instructions", 160 [FeatureVSX]>; 161def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics", 162 "HasPartwordAtomics", "true", 163 "Enable l[bh]arx and st[bh]cx.">; 164def FeatureInvariantFunctionDescriptors : 165 SubtargetFeature<"invariant-function-descriptors", 166 "HasInvariantFunctionDescriptors", "true", 167 "Assume function descriptors are invariant">; 168def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true", 169 "Always use indirect calls">; 170def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", 171 "Enable Hardware Transactional Memory instructions">; 172def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", 173 "Implement mftb using the mfspr instruction">; 174def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", 175 "Target supports instruction fusion">; 176def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", 177 "HasAddiLoadFusion", "true", 178 "Power8 Addi-Load fusion", 179 [FeatureFusion]>; 180def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", 181 "HasAddisLoadFusion", "true", 182 "Power8 Addis-Load fusion", 183 [FeatureFusion]>; 184def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true", 185 "Target supports store clustering", 186 [FeatureFusion]>; 187def FeatureUnalignedFloats : 188 SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", 189 "true", "CPU does not trap on unaligned FP access">; 190def FeaturePPCPreRASched: 191 SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true", 192 "Use PowerPC pre-RA scheduling strategy">; 193def FeaturePPCPostRASched: 194 SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true", 195 "Use PowerPC post-RA scheduling strategy">; 196def FeatureFloat128 : 197 SubtargetFeature<"float128", "HasFloat128", "true", 198 "Enable the __float128 data type for IEEE-754R Binary128.", 199 [FeatureVSX]>; 200def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", 201 "POPCNTD_Fast", 202 "Enable the popcnt[dw] instructions">; 203// Note that for the a2 processor models we should not use popcnt[dw] by 204// default. These processors do support the instructions, but they're 205// microcoded, and the software emulation is about twice as fast. 206def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD", 207 "POPCNTD_Slow", 208 "Has slow popcnt[dw] instructions">; 209 210def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", 211 "Treat vector data stream cache control instructions as deprecated">; 212 213def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", 214 "true", 215 "Enable instructions in ISA 3.0.">; 216def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", 217 "true", 218 "Enable instructions in ISA 3.1.", 219 [FeatureISA3_0]>; 220def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", 221 "Enable POWER9 Altivec instructions", 222 [FeatureISA3_0, FeatureP8Altivec]>; 223def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", 224 "Enable POWER9 vector instructions", 225 [FeatureISA3_0, FeatureP8Vector, 226 FeatureP9Altivec]>; 227def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", 228 "true", 229 "Enable POWER10 vector instructions", 230 [FeatureISA3_1, FeatureP9Vector]>; 231// A separate feature for this even though it is equivalent to P9Vector 232// because this is a feature of the implementation rather than the architecture 233// and may go away with future CPU's. 234def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", 235 "VectorsUseTwoUnits", 236 "true", 237 "Vectors use two units">; 238def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", 239 "true", 240 "Enable prefixed instructions", 241 [FeatureISA3_0, FeatureP8Vector, 242 FeatureP9Altivec]>; 243def FeaturePCRelativeMemops : 244 SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", 245 "Enable PC relative Memory Ops", 246 [FeatureISA3_0, FeaturePrefixInstrs]>; 247def FeaturePairedVectorMemops: 248 SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", 249 "32Byte load and store instructions", 250 [FeatureISA3_0]>; 251def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", 252 "Enable MMA instructions", 253 [FeatureP8Vector, FeatureP9Altivec, 254 FeaturePairedVectorMemops]>; 255def FeatureROPProtect : 256 SubtargetFeature<"rop-protect", "HasROPProtect", "true", 257 "Add ROP protect">; 258 259def FeaturePrivileged : 260 SubtargetFeature<"privileged", "HasPrivileged", "true", 261 "Add privileged instructions">; 262 263def FeaturePredictableSelectIsExpensive : 264 SubtargetFeature<"predictable-select-expensive", 265 "PredictableSelectIsExpensive", 266 "true", 267 "Prefer likely predicted branches over selects">; 268 269// Since new processors generally contain a superset of features of those that 270// came before them, the idea is to make implementations of new processors 271// less error prone and easier to read. 272// Namely: 273// list<SubtargetFeature> P8InheritableFeatures = ... 274// list<SubtargetFeature> FutureProcessorAddtionalFeatures = 275// [ features that Power8 does not support but inheritable ] 276// list<SubtargetFeature> FutureProcessorSpecificFeatures = 277// [ features that Power8 does not support and not inheritable ] 278// list<SubtargetFeature> FutureProcessorInheritableFeatures = 279// !listconcat(P8InheritableFeatures, FutureProcessorAddtionalFeatures) 280// list<SubtargetFeature> FutureProcessorFeatures = 281// !listconcat(FutureProcessorInheritableFeatures, 282// FutureProcessorSpecificFeatures) 283 284// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as 285// well as providing a single point of definition if the feature set will be 286// used elsewhere. 287def ProcessorFeatures { 288 // Power7 289 list<SubtargetFeature> P7InheritableFeatures = [DirectivePwr7, 290 FeatureAltivec, 291 FeatureVSX, 292 FeatureMFOCRF, 293 FeatureFCPSGN, 294 FeatureFSqrt, 295 FeatureFRE, 296 FeatureFRES, 297 FeatureFRSQRTE, 298 FeatureFRSQRTES, 299 FeatureRecipPrec, 300 FeatureSTFIWX, 301 FeatureLFIWAX, 302 FeatureFPRND, 303 FeatureFPCVT, 304 FeatureISEL, 305 FeaturePOPCNTD, 306 FeatureCMPB, 307 FeatureLDBRX, 308 Feature64Bit, 309 /* Feature64BitRegs, */ 310 FeatureBPERMD, 311 FeatureExtDiv, 312 FeatureMFTB, 313 DeprecatedDST, 314 FeatureTwoConstNR, 315 FeatureUnalignedFloats]; 316 list<SubtargetFeature> P7SpecificFeatures = []; 317 list<SubtargetFeature> P7Features = 318 !listconcat(P7InheritableFeatures, P7SpecificFeatures); 319 320 // Power8 321 list<SubtargetFeature> P8AdditionalFeatures = 322 [DirectivePwr8, 323 FeatureP8Altivec, 324 FeatureP8Vector, 325 FeatureP8Crypto, 326 FeatureHTM, 327 FeatureDirectMove, 328 FeatureICBT, 329 FeaturePartwordAtomic, 330 FeaturePredictableSelectIsExpensive 331 ]; 332 333 list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, 334 FeatureAddisLoadFusion]; 335 list<SubtargetFeature> P8InheritableFeatures = 336 !listconcat(P7InheritableFeatures, P8AdditionalFeatures); 337 list<SubtargetFeature> P8Features = 338 !listconcat(P8InheritableFeatures, P8SpecificFeatures); 339 340 // Power9 341 list<SubtargetFeature> P9AdditionalFeatures = 342 [DirectivePwr9, 343 FeatureP9Altivec, 344 FeatureP9Vector, 345 FeaturePPCPreRASched, 346 FeaturePPCPostRASched, 347 FeatureISA3_0, 348 FeaturePredictableSelectIsExpensive 349 ]; 350 351 // Some features are unique to Power9 and there is no reason to assume 352 // they will be part of any future CPUs. One example is the narrower 353 // dispatch for vector operations than scalar ones. For the time being, 354 // this list also includes scheduling-related features since we do not have 355 // enough info to create custom scheduling strategies for future CPUs. 356 list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits]; 357 list<SubtargetFeature> P9InheritableFeatures = 358 !listconcat(P8InheritableFeatures, P9AdditionalFeatures); 359 list<SubtargetFeature> P9Features = 360 !listconcat(P9InheritableFeatures, P9SpecificFeatures); 361 362 // Power10 363 // For P10 CPU we assume that all of the existing features from Power9 364 // still exist with the exception of those we know are Power9 specific. 365 list<SubtargetFeature> FusionFeatures = [FeatureStoreFusion]; 366 list<SubtargetFeature> P10AdditionalFeatures = 367 !listconcat(FusionFeatures, [ 368 DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, 369 FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, 370 FeaturePairedVectorMemops]); 371 list<SubtargetFeature> P10SpecificFeatures = []; 372 list<SubtargetFeature> P10InheritableFeatures = 373 !listconcat(P9InheritableFeatures, P10AdditionalFeatures); 374 list<SubtargetFeature> P10Features = 375 !listconcat(P10InheritableFeatures, P10SpecificFeatures); 376 377 // Future 378 // For future CPU we assume that all of the existing features from Power10 379 // still exist with the exception of those we know are Power10 specific. 380 list<SubtargetFeature> FutureAdditionalFeatures = []; 381 list<SubtargetFeature> FutureSpecificFeatures = []; 382 list<SubtargetFeature> FutureInheritableFeatures = 383 !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); 384 list<SubtargetFeature> FutureFeatures = 385 !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); 386} 387 388// Note: Future features to add when support is extended to more 389// recent ISA levels: 390// 391// DFP p6, p6x, p7 decimal floating-point instructions 392// POPCNTB p5 through p7 popcntb and related instructions 393 394//===----------------------------------------------------------------------===// 395// Classes used for relation maps. 396//===----------------------------------------------------------------------===// 397// RecFormRel - Filter class used to relate non-record-form instructions with 398// their record-form variants. 399class RecFormRel; 400 401// AltVSXFMARel - Filter class used to relate the primary addend-killing VSX 402// FMA instruction forms with their corresponding factor-killing forms. 403class AltVSXFMARel { 404 bit IsVSXFMAAlt = 0; 405} 406 407//===----------------------------------------------------------------------===// 408// Relation Map Definitions. 409//===----------------------------------------------------------------------===// 410 411def getRecordFormOpcode : InstrMapping { 412 let FilterClass = "RecFormRel"; 413 // Instructions with the same BaseName and Interpretation64Bit values 414 // form a row. 415 let RowFields = ["BaseName", "Interpretation64Bit"]; 416 // Instructions with the same RC value form a column. 417 let ColFields = ["RC"]; 418 // The key column are the non-record-form instructions. 419 let KeyCol = ["0"]; 420 // Value columns RC=1 421 let ValueCols = [["1"]]; 422} 423 424def getNonRecordFormOpcode : InstrMapping { 425 let FilterClass = "RecFormRel"; 426 // Instructions with the same BaseName and Interpretation64Bit values 427 // form a row. 428 let RowFields = ["BaseName", "Interpretation64Bit"]; 429 // Instructions with the same RC value form a column. 430 let ColFields = ["RC"]; 431 // The key column are the record-form instructions. 432 let KeyCol = ["1"]; 433 // Value columns are RC=0 434 let ValueCols = [["0"]]; 435} 436 437def getAltVSXFMAOpcode : InstrMapping { 438 let FilterClass = "AltVSXFMARel"; 439 // Instructions with the same BaseName value form a row. 440 let RowFields = ["BaseName"]; 441 // Instructions with the same IsVSXFMAAlt value form a column. 442 let ColFields = ["IsVSXFMAAlt"]; 443 // The key column are the (default) addend-killing instructions. 444 let KeyCol = ["0"]; 445 // Value columns IsVSXFMAAlt=1 446 let ValueCols = [["1"]]; 447} 448 449//===----------------------------------------------------------------------===// 450// Register File Description 451//===----------------------------------------------------------------------===// 452 453include "PPCRegisterInfo.td" 454include "PPCSchedule.td" 455include "GISel/PPCRegisterBanks.td" 456 457//===----------------------------------------------------------------------===// 458// PowerPC processors supported. 459// 460 461def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, 462 FeatureMFTB]>; 463def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, 464 FeatureFRES, FeatureFRSQRTE, 465 FeatureICBT, FeatureBookE, 466 FeatureMSYNC, FeatureMFTB]>; 467def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, 468 FeatureFRES, FeatureFRSQRTE, 469 FeatureICBT, FeatureBookE, 470 FeatureMSYNC, FeatureMFTB]>; 471def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; 472def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, 473 FeatureMFTB]>; 474def : Processor<"603", G3Itineraries, [Directive603, 475 FeatureFRES, FeatureFRSQRTE, 476 FeatureMFTB]>; 477def : Processor<"603e", G3Itineraries, [Directive603, 478 FeatureFRES, FeatureFRSQRTE, 479 FeatureMFTB]>; 480def : Processor<"603ev", G3Itineraries, [Directive603, 481 FeatureFRES, FeatureFRSQRTE, 482 FeatureMFTB]>; 483def : Processor<"604", G3Itineraries, [Directive604, 484 FeatureFRES, FeatureFRSQRTE, 485 FeatureMFTB]>; 486def : Processor<"604e", G3Itineraries, [Directive604, 487 FeatureFRES, FeatureFRSQRTE, 488 FeatureMFTB]>; 489def : Processor<"620", G3Itineraries, [Directive620, 490 FeatureFRES, FeatureFRSQRTE, 491 FeatureMFTB]>; 492def : Processor<"750", G4Itineraries, [Directive750, 493 FeatureFRES, FeatureFRSQRTE, 494 FeatureMFTB]>; 495def : Processor<"g3", G3Itineraries, [Directive750, 496 FeatureFRES, FeatureFRSQRTE, 497 FeatureMFTB]>; 498def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, 499 FeatureFRES, FeatureFRSQRTE, 500 FeatureMFTB]>; 501def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, 502 FeatureFRES, FeatureFRSQRTE, 503 FeatureMFTB]>; 504def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, 505 FeatureFRES, FeatureFRSQRTE, 506 FeatureMFTB]>; 507def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, 508 FeatureFRES, FeatureFRSQRTE, 509 FeatureMFTB]>; 510 511def : ProcessorModel<"970", G5Model, 512 [Directive970, FeatureAltivec, 513 FeatureMFOCRF, FeatureFSqrt, 514 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, 515 Feature64Bit /*, Feature64BitRegs */, 516 FeatureMFTB]>; 517def : ProcessorModel<"g5", G5Model, 518 [Directive970, FeatureAltivec, 519 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, 520 FeatureFRES, FeatureFRSQRTE, 521 Feature64Bit /*, Feature64BitRegs */, 522 FeatureMFTB, DeprecatedDST]>; 523def : ProcessorModel<"e500", PPCE500Model, 524 [DirectiveE500, 525 FeatureICBT, FeatureBookE, 526 FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; 527def : ProcessorModel<"e500mc", PPCE500mcModel, 528 [DirectiveE500mc, 529 FeatureSTFIWX, FeatureICBT, FeatureBookE, 530 FeatureISEL, FeatureMFTB]>; 531def : ProcessorModel<"e5500", PPCE5500Model, 532 [DirectiveE5500, FeatureMFOCRF, Feature64Bit, 533 FeatureSTFIWX, FeatureICBT, FeatureBookE, 534 FeatureISEL, FeatureMFTB]>; 535def : ProcessorModel<"a2", PPCA2Model, 536 [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, 537 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 538 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 539 FeatureSTFIWX, FeatureLFIWAX, 540 FeatureFPRND, FeatureFPCVT, FeatureISEL, 541 FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, 542 Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>; 543def : ProcessorModel<"pwr3", G5Model, 544 [DirectivePwr3, FeatureAltivec, 545 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, 546 FeatureSTFIWX, Feature64Bit]>; 547def : ProcessorModel<"pwr4", G5Model, 548 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, 549 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, 550 FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; 551def : ProcessorModel<"pwr5", G5Model, 552 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, 553 FeatureFSqrt, FeatureFRE, FeatureFRES, 554 FeatureFRSQRTE, FeatureFRSQRTES, 555 FeatureSTFIWX, Feature64Bit, 556 FeatureMFTB, DeprecatedDST]>; 557def : ProcessorModel<"pwr5x", G5Model, 558 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 559 FeatureFSqrt, FeatureFRE, FeatureFRES, 560 FeatureFRSQRTE, FeatureFRSQRTES, 561 FeatureSTFIWX, FeatureFPRND, Feature64Bit, 562 FeatureMFTB, DeprecatedDST]>; 563def : ProcessorModel<"pwr6", G5Model, 564 [DirectivePwr6, FeatureAltivec, 565 FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, 566 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, 567 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 568 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, 569 FeatureMFTB, DeprecatedDST]>; 570def : ProcessorModel<"pwr6x", G5Model, 571 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, 572 FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, 573 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, 574 FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, 575 FeatureFPRND, Feature64Bit, 576 FeatureMFTB, DeprecatedDST]>; 577def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; 578def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; 579def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; 580// No scheduler model yet. 581def : ProcessorModel<"pwr10", P9Model, ProcessorFeatures.P10Features>; 582// No scheduler model for future CPU. 583def : ProcessorModel<"future", NoSchedModel, 584 ProcessorFeatures.FutureFeatures>; 585def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, 586 FeatureMFTB]>; 587def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, 588 FeatureMFTB]>; 589def : ProcessorModel<"ppc64", G5Model, 590 [Directive64, FeatureAltivec, 591 FeatureMFOCRF, FeatureFSqrt, FeatureFRES, 592 FeatureFRSQRTE, FeatureSTFIWX, 593 Feature64Bit /*, Feature64BitRegs */, 594 FeatureMFTB]>; 595def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; 596 597//===----------------------------------------------------------------------===// 598// Calling Conventions 599//===----------------------------------------------------------------------===// 600 601include "PPCCallingConv.td" 602 603def PPCInstrInfo : InstrInfo { 604 let isLittleEndianEncoding = 1; 605 606 // FIXME: Unset this when no longer needed! 607 let decodePositionallyEncodedOperands = 1; 608 609 let noNamedPositionallyEncodedOperands = 1; 610} 611 612def PPCAsmWriter : AsmWriter { 613 string AsmWriterClassName = "InstPrinter"; 614 int PassSubtarget = 1; 615 int Variant = 0; 616 bit isMCAsmWriter = 1; 617} 618 619def PPCAsmParser : AsmParser { 620 let ShouldEmitMatchRegisterName = 0; 621} 622 623def PPCAsmParserVariant : AsmParserVariant { 624 int Variant = 0; 625 626 // We do not use hard coded registers in asm strings. However, some 627 // InstAlias definitions use immediate literals. Set RegisterPrefix 628 // so that those are not misinterpreted as registers. 629 string RegisterPrefix = "%"; 630 string BreakCharacters = "."; 631} 632 633def PPC : Target { 634 // Information about the instructions. 635 let InstructionSet = PPCInstrInfo; 636 637 let AssemblyWriters = [PPCAsmWriter]; 638 let AssemblyParsers = [PPCAsmParser]; 639 let AssemblyParserVariants = [PPCAsmParserVariant]; 640 let AllowRegisterRenaming = 1; 641} 642 643//===----------------------------------------------------------------------===// 644// Pfm Counters 645//===----------------------------------------------------------------------===// 646 647include "PPCPfmCounters.td" 648