xref: /llvm-project/llvm/lib/Target/Mips/MipsMSAInstrInfo.td (revision b3230dd452bc8eb9ab4479cdb98f944838cb58b6) 
1//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes Mips MSA ASE instructions.
10//
11//===----------------------------------------------------------------------===//
12
13def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
14def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
15                                      SDTCisInt<1>,
16                                      SDTCisSameAs<1, 2>,
17                                      SDTCisVT<3, OtherVT>]>;
18def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
19                                       SDTCisFP<1>,
20                                       SDTCisSameAs<1, 2>,
21                                       SDTCisVT<3, OtherVT>]>;
22def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
23                                    SDTCisInt<1>, SDTCisVec<1>,
24                                    SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
25def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
26                                   SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
27def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
28                                   SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
29def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
30                                     SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
31                                     SDTCisVT<4, i32>]>;
32
33def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
34def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
35def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
36def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
37def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
38                      [SDNPCommutative, SDNPAssociative]>;
39def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
40def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
41def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
42def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
43def MipsILVL  : SDNode<"MipsISD::ILVL",  SDT_ILV>;
44def MipsILVR  : SDNode<"MipsISD::ILVR",  SDT_ILV>;
45def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
46def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
47def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
48def MipsFMS   : SDNode<"MipsISD::FMS", SDTFPTernaryOp>;
49
50def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
51def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
52
53def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
54    SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
55def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
56    SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
57
58def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
59def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
60def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
61def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
62
63def timmZExt1Ptr : TImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>;
64def timmZExt2Ptr : TImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>;
65def timmZExt3Ptr : TImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>;
66def timmZExt4Ptr : TImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
67
68// Operands
69
70def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
71
72// Pattern fragments
73def vextract_sext_i8  : PatFrag<(ops node:$vec, node:$idx),
74                                (MipsVExtractSExt node:$vec, node:$idx, i8)>;
75def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
76                                (MipsVExtractSExt node:$vec, node:$idx, i16)>;
77def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
78                                (MipsVExtractSExt node:$vec, node:$idx, i32)>;
79def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
80                                (MipsVExtractSExt node:$vec, node:$idx, i64)>;
81
82def vextract_zext_i8  : PatFrag<(ops node:$vec, node:$idx),
83                                (MipsVExtractZExt node:$vec, node:$idx, i8)>;
84def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
85                                (MipsVExtractZExt node:$vec, node:$idx, i16)>;
86def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
87                                (MipsVExtractZExt node:$vec, node:$idx, i32)>;
88def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
89                                (MipsVExtractZExt node:$vec, node:$idx, i64)>;
90
91def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
92    (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
93def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
94    (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
95def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
96    (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
97def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
98    (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
99
100def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
101    (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
102def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
103    (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
104def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
105    (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
106def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
107    (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
108
109class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
110  PatFrag<(ops node:$lhs, node:$rhs),
111          (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
112
113// ISD::SETFALSE cannot occur
114def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
115def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>;
116def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
117def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>;
118def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
119def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>;
120def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
121def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>;
122def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
123def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
124def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
125def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>;
126def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
127def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
128def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
129def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
130def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
131def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
132def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
133def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
134def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
135def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
136def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
137def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
138def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
139def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
140def vfsetun_v4f32  : vfsetcc_type<v4i32, v4f32, SETUO>;
141def vfsetun_v2f64  : vfsetcc_type<v2i64, v2f64, SETUO>;
142def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
143def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
144def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
145def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
146def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
147def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
148def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
149def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
150def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
152def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
153def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
154// ISD::SETTRUE cannot occur
155// ISD::SETFALSE2 cannot occur
156// ISD::SETTRUE2 cannot occur
157
158class vsetcc_type<ValueType ResTy, CondCode CC> :
159  PatFrag<(ops node:$lhs, node:$rhs),
160          (ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
161
162def vseteq_v16i8  : vsetcc_type<v16i8, SETEQ>;
163def vseteq_v8i16  : vsetcc_type<v8i16, SETEQ>;
164def vseteq_v4i32  : vsetcc_type<v4i32, SETEQ>;
165def vseteq_v2i64  : vsetcc_type<v2i64, SETEQ>;
166def vsetle_v16i8  : vsetcc_type<v16i8, SETLE>;
167def vsetle_v8i16  : vsetcc_type<v8i16, SETLE>;
168def vsetle_v4i32  : vsetcc_type<v4i32, SETLE>;
169def vsetle_v2i64  : vsetcc_type<v2i64, SETLE>;
170def vsetlt_v16i8  : vsetcc_type<v16i8, SETLT>;
171def vsetlt_v8i16  : vsetcc_type<v8i16, SETLT>;
172def vsetlt_v4i32  : vsetcc_type<v4i32, SETLT>;
173def vsetlt_v2i64  : vsetcc_type<v2i64, SETLT>;
174def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
175def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
176def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
177def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
178def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
182
183def vsplati8  : PatFrag<(ops node:$e0),
184                        (v16i8 (build_vector node:$e0, node:$e0,
185                                             node:$e0, node:$e0,
186                                             node:$e0, node:$e0,
187                                             node:$e0, node:$e0,
188                                             node:$e0, node:$e0,
189                                             node:$e0, node:$e0,
190                                             node:$e0, node:$e0,
191                                             node:$e0, node:$e0))>;
192def vsplati16 : PatFrag<(ops node:$e0),
193                        (v8i16 (build_vector node:$e0, node:$e0,
194                                             node:$e0, node:$e0,
195                                             node:$e0, node:$e0,
196                                             node:$e0, node:$e0))>;
197def vsplati32 : PatFrag<(ops node:$e0),
198                        (v4i32 (build_vector node:$e0, node:$e0,
199                                             node:$e0, node:$e0))>;
200
201// Any build_vector that is a constant splat with a value that equals 1
202def vsplat_imm_eq_1 : ComplexPattern<vAny, 0, "selectVSplatImmEq1">;
203
204def vsplati64 : PatFrag<(ops node:$e0),
205                        (v2i64 (build_vector node:$e0, node:$e0))>;
206
207def vsplati64_splat_d : PatFrag<(ops node:$e0),
208                                (v2i64 (bitconvert
209                                         (v4i32 (and
210                                           (v4i32 (build_vector node:$e0,
211                                                                node:$e0,
212                                                                node:$e0,
213                                                                node:$e0)),
214                                           (vsplat_imm_eq_1)))))>;
215
216def vsplatf32 : PatFrag<(ops node:$e0),
217                        (v4f32 (build_vector node:$e0, node:$e0,
218                                             node:$e0, node:$e0))>;
219def vsplatf64 : PatFrag<(ops node:$e0),
220                        (v2f64 (build_vector node:$e0, node:$e0))>;
221
222def vsplati8_elt  : PatFrag<(ops node:$v, node:$i),
223                            (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
224def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
225                            (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
226def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
227                            (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
228def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
229                            (MipsVSHF (vsplati64_splat_d node:$i),
230                                      node:$v, node:$v)>;
231
232class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
233                          list<SDNode> roots = [],
234                          list<SDNodeProperty> props = []> :
235  ComplexPattern<ty, numops, fn, roots, props> {
236  Operand OpClass = opclass;
237}
238
239def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
240                                         "selectVSplatUimm<3>">;
241
242def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
243                                         "selectVSplatUimm<4>">;
244
245def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
246                                         "selectVSplatUimm<5>">;
247
248def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
249                                         "selectVSplatUimm<8>">;
250
251def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
252                                         "selectVSplatSimm<5>">;
253
254def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
255                                          "selectVSplatUimm<3>">;
256
257def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
258                                          "selectVSplatUimm<4>">;
259
260def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
261                                          "selectVSplatUimm<5>">;
262
263def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
264                                          "selectVSplatSimm<5>">;
265
266def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
267                                          "selectVSplatUimm<2>">;
268
269def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
270                                          "selectVSplatUimm<5>">;
271
272def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
273                                          "selectVSplatSimm<5>">;
274
275def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
276                                          "selectVSplatUimm<1>">;
277
278def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
279                                          "selectVSplatUimm<5>">;
280
281def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
282                                          "selectVSplatUimm<6>">;
283
284def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
285                                          "selectVSplatSimm<5>">;
286
287// Any build_vector that is a constant splat with a value that is an exact
288// power of 2
289def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2">;
290
291// Any build_vector that is a constant splat with a value that is the bitwise
292// inverse of an exact power of 2
293def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2">;
294
295// Any build_vector that is a constant splat with only a consecutive sequence
296// of left-most bits set.
297def vsplat_maskl_bits_uimm3
298    : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL">;
299def vsplat_maskl_bits_uimm4
300    : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL">;
301def vsplat_maskl_bits_uimm5
302    : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL">;
303def vsplat_maskl_bits_uimm6
304    : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL">;
305
306// Any build_vector that is a constant splat with only a consecutive sequence
307// of right-most bits set.
308def vsplat_maskr_bits_uimm3
309    : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR">;
310def vsplat_maskr_bits_uimm4
311    : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR">;
312def vsplat_maskr_bits_uimm5
313    : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR">;
314def vsplat_maskr_bits_uimm6
315    : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR">;
316
317
318def vbclr : PatFrag<(ops node:$ws, node:$wt),
319                    (and node:$ws, (vnot (shl (vsplat_imm_eq_1), node:$wt)))>;
320
321def vbneg : PatFrag<(ops node:$ws, node:$wt),
322                    (xor node:$ws, (shl (vsplat_imm_eq_1), node:$wt))>;
323
324def vbset : PatFrag<(ops node:$ws, node:$wt),
325                    (or node:$ws, (shl (vsplat_imm_eq_1), node:$wt))>;
326
327def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
328                     (add node:$wd, (mul node:$ws, node:$wt))>;
329
330def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
331                     (sub node:$wd, (mul node:$ws, node:$wt))>;
332
333def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
334                        (fmul node:$ws, (fexp2 node:$wt))>;
335
336// Instruction encoding.
337class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
338class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
339class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
340class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
341
342class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
343class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
344class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
345class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
346
347class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
348class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
349class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
350class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
351
352class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
353class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
354class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
355class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
356
357class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
358class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
359class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
360class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
361
362class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
363class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
364class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
365class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
366
367class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
368
369class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
370
371class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
372class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
373class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
374class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
375
376class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
377class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
378class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
379class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
380
381class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
382class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
383class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
384class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
385
386class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
387class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
388class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
389class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
390
391class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
392class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
393class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
394class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
395
396class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
397class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
398class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
399class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
400
401class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
402class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
403class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
404class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
405
406class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
407class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
408class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
409class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
410
411class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
412class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
413class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
414class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
415
416class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
417class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
418class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
419class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
420
421class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
422class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
423class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
424class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
425
426class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
427class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
428class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
429class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
430
431class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
432
433class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
434
435class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
436
437class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
438
439class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
440class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
441class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
442class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
443
444class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
445class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
446class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
447class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
448
449class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
450class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
451class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
452class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
453
454class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
455
456class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
457
458class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
459
460class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
461class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
462class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
463class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
464
465class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
466class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
467class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
468class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
469
470class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
471class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
472class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
473class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
474
475class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
476
477class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
478class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
479class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
480class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
481
482class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
483class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
484class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
485class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
486
487class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
488
489class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
490class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
491class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
492class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
493
494class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
495class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
496class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
497class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
498
499class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
500class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
501class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
502class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
503
504class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
505class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
506class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
507class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
508
509class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
510class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
511class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
512class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
513
514class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
515class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
516class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
517class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
518
519class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
520class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
521class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
522class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
523
524class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
525class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
526class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
527class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
528
529class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
530class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
531class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
532class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
533
534class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
535class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
536class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
537
538class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
539
540class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
541class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
542class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
543class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
544
545class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
546class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
547class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
548class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
549
550class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
551class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
552class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
553
554class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
555class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
556class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
557
558class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
559class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
560class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
561
562class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
563class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
564class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
565
566class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
567class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
568class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
569
570class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
571class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
572class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
573
574class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
575class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
576
577class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
578class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
579
580class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
581class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
582
583class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
584class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
585
586class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
587class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
588
589class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
590class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
591
592class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
593class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
594
595class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
596class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
597
598class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
599class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
600
601class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
602class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
603
604class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
605class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
606
607class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
608class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
609
610class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
611class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
612
613class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
614class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
615
616class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
617class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
618
619class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
620class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
621
622class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
623class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
624
625class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
626class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
627
628class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
629class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
630
631class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
632class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
633
634class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
635class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
636
637class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
638class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
639
640class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
641class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
642class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
643class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
644
645class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
646class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
647
648class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
649class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
650
651class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
652class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
653
654class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
655class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
656
657class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
658class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
659
660class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
661class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
662
663class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
664class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
665
666class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
667class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
668
669class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
670class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
671
672class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
673class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
674
675class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
676class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
677
678class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
679class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
680
681class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
682class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
683
684class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
685class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
686
687class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
688class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
689
690class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
691class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
692
693class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
694class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
695
696class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
697class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
698
699class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
700class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
701
702class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
703class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
704
705class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
706class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
707
708class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
709class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
710
711class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
712class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
713
714class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
715class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
716
717class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
718class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
719
720class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
721class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
722
723class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
724class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
725
726class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
727class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
728
729class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
730class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
731
732class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
733class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
734class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
735
736class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
737class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
738class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
739
740class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
741class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
742class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
743
744class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
745class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
746class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
747
748class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
749class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
750class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
751class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
752
753class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
754class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
755class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
756class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
757
758class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
759class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
760class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
761class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
762
763class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
764class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
765class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
766class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
767
768class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
769class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
770class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
771class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
772
773class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
774class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
775class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
776class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
777
778class LD_B_ENC   : MSA_MI10_FMT<0b00, 0b1000>;
779class LD_H_ENC   : MSA_MI10_FMT<0b01, 0b1000>;
780class LD_W_ENC   : MSA_MI10_FMT<0b10, 0b1000>;
781class LD_D_ENC   : MSA_MI10_FMT<0b11, 0b1000>;
782
783class LDI_B_ENC  : MSA_I10_FMT<0b110, 0b00, 0b000111>;
784class LDI_H_ENC  : MSA_I10_FMT<0b110, 0b01, 0b000111>;
785class LDI_W_ENC  : MSA_I10_FMT<0b110, 0b10, 0b000111>;
786class LDI_D_ENC  : MSA_I10_FMT<0b110, 0b11, 0b000111>;
787
788class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
789class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
790
791class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
792class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
793
794class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
795class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
796
797class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
798class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
799class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
800class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
801
802class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
803class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
804class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
805class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
806
807class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
808class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
809class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
810class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
811
812class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
813class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
814class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
815class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
816
817class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
818class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
819class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
820class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
821
822class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
823class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
824class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
825class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
826
827class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
828class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
829class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
830class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
831
832class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
833class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
834class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
835class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
836
837class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
838class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
839class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
840class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
841
842class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
843class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
844class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
845class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
846
847class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
848class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
849class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
850class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
851
852class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
853class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
854class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
855class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
856
857class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
858class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
859class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
860class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
861
862class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
863
864class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
865class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
866
867class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
868class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
869
870class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
871class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
872class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
873class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
874
875class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
876class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
877
878class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
879class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
880
881class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
882class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
883class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
884class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
885
886class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
887class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
888class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
889class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
890
891class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
892class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
893class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
894class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
895
896class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
897
898class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
899
900class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
901
902class ORI_B_ENC  : MSA_I8_FMT<0b01, 0b000000>;
903
904class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
905class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
906class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
907class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
908
909class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
910class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
911class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
912class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
913
914class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
915class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
916class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
917class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
918
919class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
920class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
921class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
922class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
923
924class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
925class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
926class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
927class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
928
929class SHF_B_ENC  : MSA_I8_FMT<0b00, 0b000010>;
930class SHF_H_ENC  : MSA_I8_FMT<0b01, 0b000010>;
931class SHF_W_ENC  : MSA_I8_FMT<0b10, 0b000010>;
932
933class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
934class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
935class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
936class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
937
938class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
939class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
940class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
941class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
942
943class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
944class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
945class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
946class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
947
948class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
949class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
950class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
951class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
952
953class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
954class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
955class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
956class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
957
958class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
959class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
960class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
961class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
962
963class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
964class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
965class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
966class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
967
968class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
969class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
970class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
971class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
972
973class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
974class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
975class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
976class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
977
978class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
979class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
980class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
981class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
982
983class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
984class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
985class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
986class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
987
988class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
989class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
990class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
991class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
992
993class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
994class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
995class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
996class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
997
998class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
999class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
1000class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
1001class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
1002
1003class ST_B_ENC   : MSA_MI10_FMT<0b00, 0b1001>;
1004class ST_H_ENC   : MSA_MI10_FMT<0b01, 0b1001>;
1005class ST_W_ENC   : MSA_MI10_FMT<0b10, 0b1001>;
1006class ST_D_ENC   : MSA_MI10_FMT<0b11, 0b1001>;
1007
1008class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
1009class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
1010class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
1011class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
1012
1013class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
1014class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
1015class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
1016class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
1017
1018class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
1019class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
1020class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
1021class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
1022
1023class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
1024class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
1025class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
1026class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
1027
1028class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
1029class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
1030class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
1031class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
1032
1033class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
1034class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
1035class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
1036class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
1037
1038class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
1039class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
1040class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
1041class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
1042
1043class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
1044
1045class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
1046
1047// Instruction desc.
1048class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1049                          ComplexPattern Imm, RegisterOperand ROWD,
1050                          RegisterOperand ROWS = ROWD,
1051                          InstrItinClass itin = NoItinerary> {
1052  dag OutOperandList = (outs ROWD:$wd);
1053  dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
1054  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1055  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1056  InstrItinClass Itinerary = itin;
1057}
1058
1059class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1060                          ComplexPattern Imm, RegisterOperand ROWD,
1061                          RegisterOperand ROWS = ROWD,
1062                          InstrItinClass itin = NoItinerary> {
1063  dag OutOperandList = (outs ROWD:$wd);
1064  dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
1065  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1066  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1067  InstrItinClass Itinerary = itin;
1068}
1069
1070class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1071                          ComplexPattern Imm, RegisterOperand ROWD,
1072                          RegisterOperand ROWS = ROWD,
1073                          InstrItinClass itin = NoItinerary> {
1074  dag OutOperandList = (outs ROWD:$wd);
1075  dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
1076  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1077  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1078  InstrItinClass Itinerary = itin;
1079}
1080
1081class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1082                          ComplexPattern Imm, RegisterOperand ROWD,
1083                          RegisterOperand ROWS = ROWD,
1084                          InstrItinClass itin = NoItinerary> {
1085  dag OutOperandList = (outs ROWD:$wd);
1086  dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
1087  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1088  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1089  InstrItinClass Itinerary = itin;
1090}
1091
1092class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1093                          Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1094                          RegisterOperand ROWS = ROWD,
1095                          InstrItinClass itin = NoItinerary> {
1096  dag OutOperandList = (outs ROWD:$wd);
1097  dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
1098  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1099  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
1100  InstrItinClass Itinerary = itin;
1101}
1102
1103class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
1104                               SplatComplexPattern Mask, RegisterOperand ROWD,
1105                               RegisterOperand ROWS = ROWD,
1106                               InstrItinClass itin = NoItinerary> {
1107  dag OutOperandList = (outs ROWD:$wd);
1108  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m);
1109  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1110  // Note that binsxi and vselect treat the condition operand the opposite
1111  // way to each other.
1112  //   (vselect cond, if_set, if_clear)
1113  //   (BSEL_V cond, if_clear, if_set)
1114  list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
1115                                               ROWS:$wd_in))];
1116  InstrItinClass Itinerary = itin;
1117  string Constraints = "$wd = $wd_in";
1118}
1119
1120class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
1121                               SplatComplexPattern ImmOp, RegisterOperand ROWD,
1122                               RegisterOperand ROWS = ROWD,
1123                               InstrItinClass itin = NoItinerary> :
1124  MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1125
1126class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
1127                               SplatComplexPattern ImmOp, RegisterOperand ROWD,
1128                               RegisterOperand ROWS = ROWD,
1129                               InstrItinClass itin = NoItinerary> :
1130  MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
1131
1132class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1133                              SplatComplexPattern SplatImm,
1134                              RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1135                              InstrItinClass itin = NoItinerary> {
1136  dag OutOperandList = (outs ROWD:$wd);
1137  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
1138  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
1139  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
1140  InstrItinClass Itinerary = itin;
1141}
1142
1143class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1144                         ValueType VecTy, Operand ImmOp, ImmLeaf Imm,
1145                         RegisterOperand ROD, RegisterOperand ROWS,
1146                         InstrItinClass itin = NoItinerary> {
1147  dag OutOperandList = (outs ROD:$rd);
1148  dag InOperandList = (ins ROWS:$ws, ImmOp:$n);
1149  string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
1150  list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))];
1151  InstrItinClass Itinerary = itin;
1152}
1153
1154class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1155                            RegisterOperand ROWD, RegisterOperand ROWS,
1156                            Operand ImmOp, ImmLeaf Imm,
1157                            InstrItinClass itin = NoItinerary> {
1158  dag OutOperandList = (outs ROWD:$wd);
1159  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
1160  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1161  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1162                                              Imm:$n))];
1163  string Constraints = "$wd = $wd_in";
1164  InstrItinClass Itinerary = itin;
1165}
1166
1167class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
1168                           Operand ImmOp, ImmLeaf Imm, RegisterClass RCD,
1169                           RegisterClass RCWS> :
1170      MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n),
1171                [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> {
1172  bit usesCustomInserter = 1;
1173  bit hasNoSchedulingInfo = 1;
1174}
1175
1176class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1177                       SplatComplexPattern SplatImm, RegisterOperand ROWD,
1178                       RegisterOperand ROWS = ROWD,
1179                       InstrItinClass itin = NoItinerary> {
1180  dag OutOperandList = (outs ROWD:$wd);
1181  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
1182  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
1183  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
1184  InstrItinClass Itinerary = itin;
1185}
1186
1187class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1188                       SplatComplexPattern SplatImm, RegisterOperand ROWD,
1189                       RegisterOperand ROWS = ROWD,
1190                       InstrItinClass itin = NoItinerary> {
1191  dag OutOperandList = (outs ROWD:$wd);
1192  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
1193  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1194  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
1195  InstrItinClass Itinerary = itin;
1196}
1197
1198class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1199                           RegisterOperand ROWS = ROWD,
1200                           InstrItinClass itin = NoItinerary> {
1201  dag OutOperandList = (outs ROWD:$wd);
1202  dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
1203  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
1204  list<dag> Pattern = [(set ROWD:$wd, (MipsSHF timmZExt8:$u8, ROWS:$ws))];
1205  InstrItinClass Itinerary = itin;
1206}
1207
1208class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1209                            InstrItinClass itin = NoItinerary> {
1210  dag OutOperandList = (outs ROWD:$wd);
1211  dag InOperandList = (ins vsplat_simm10:$s10);
1212  string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
1213  // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
1214  list<dag> Pattern = [];
1215  bit hasSideEffects = 0;
1216  bit isReMaterializable = 1;
1217  InstrItinClass Itinerary = itin;
1218}
1219
1220class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1221                       RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1222                       InstrItinClass itin = NoItinerary> {
1223  dag OutOperandList = (outs ROWD:$wd);
1224  dag InOperandList = (ins ROWS:$ws);
1225  string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1226  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1227  InstrItinClass Itinerary = itin;
1228}
1229
1230class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
1231                            SDPatternOperator OpNode, RegisterOperand ROWD,
1232                            RegisterOperand ROS = ROWD,
1233                            InstrItinClass itin = NoItinerary> {
1234  dag OutOperandList = (outs ROWD:$wd);
1235  dag InOperandList = (ins ROS:$rs);
1236  string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
1237  list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1238  InstrItinClass Itinerary = itin;
1239}
1240
1241class MSA_2R_FILL_PSEUDO_BASE<SDPatternOperator OpNode,
1242                              RegisterClass RCWD, RegisterClass RCWS> :
1243      MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
1244                [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1245  let usesCustomInserter = 1;
1246}
1247
1248class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1249                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1250                        InstrItinClass itin = NoItinerary> {
1251  dag OutOperandList = (outs ROWD:$wd);
1252  dag InOperandList = (ins ROWS:$ws);
1253  string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
1254  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1255  InstrItinClass Itinerary = itin;
1256}
1257
1258class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1259                       RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1260                       RegisterOperand ROWT = ROWD,
1261                       InstrItinClass itin = NoItinerary> {
1262  dag OutOperandList = (outs ROWD:$wd);
1263  dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1264  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1265  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1266  InstrItinClass Itinerary = itin;
1267}
1268
1269class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1270                             RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1271                             RegisterOperand ROWT = ROWD,
1272                             InstrItinClass itin = NoItinerary> {
1273  dag OutOperandList = (outs ROWD:$wd);
1274  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1275  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1276  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1277                                              ROWT:$wt))];
1278  string Constraints = "$wd = $wd_in";
1279  InstrItinClass Itinerary = itin;
1280}
1281
1282class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1283                             RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1284                             InstrItinClass itin = NoItinerary> {
1285  dag OutOperandList = (outs ROWD:$wd);
1286  dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
1287  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1288  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
1289  InstrItinClass Itinerary = itin;
1290}
1291
1292class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
1293                            RegisterOperand ROWS = ROWD,
1294                            RegisterOperand ROWT = ROWD,
1295                            InstrItinClass itin = NoItinerary> {
1296  dag OutOperandList = (outs ROWD:$wd);
1297  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1298  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1299  list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
1300                                                ROWT:$wt))];
1301  string Constraints = "$wd = $wd_in";
1302  InstrItinClass Itinerary = itin;
1303}
1304
1305class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1306                           RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1307                           InstrItinClass itin = NoItinerary> {
1308  dag OutOperandList = (outs ROWD:$wd);
1309  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
1310  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
1311  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1312                                              GPR32Opnd:$rt))];
1313  InstrItinClass Itinerary = itin;
1314  string Constraints = "$wd = $wd_in";
1315}
1316
1317class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1318                          RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1319                          RegisterOperand ROWT = ROWD,
1320                          InstrItinClass itin = NoItinerary> {
1321  dag OutOperandList = (outs ROWD:$wd);
1322  dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
1323  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1324  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
1325                                              ROWT:$wt))];
1326  InstrItinClass Itinerary = itin;
1327  string Constraints = "$wd = $wd_in";
1328}
1329
1330class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1331                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1332                        RegisterOperand ROWT = ROWD,
1333                        InstrItinClass itin = NoItinerary> :
1334  MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1335
1336class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1337                            RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1338                            RegisterOperand ROWT = ROWD,
1339                            InstrItinClass itin = NoItinerary> :
1340  MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1341
1342class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
1343  dag OutOperandList = (outs);
1344  dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
1345  string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
1346  list<dag> Pattern = [];
1347  InstrItinClass Itinerary = NoItinerary;
1348  bit isBranch = 1;
1349  bit isTerminator = 1;
1350  bit hasDelaySlot = 1;
1351  list<Register> Defs = [AT];
1352}
1353
1354class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1355                           Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1356                           RegisterOperand ROS,
1357                           InstrItinClass itin = NoItinerary> {
1358  dag OutOperandList = (outs ROWD:$wd);
1359  dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n);
1360  string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
1361  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))];
1362  InstrItinClass Itinerary = itin;
1363  string Constraints = "$wd = $wd_in";
1364}
1365
1366class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1367                             Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1368                             RegisterOperand ROFS> :
1369      MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs),
1370                [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> {
1371  bit usesCustomInserter = 1;
1372  string Constraints = "$wd = $wd_in";
1373}
1374
1375class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
1376                                  RegisterOperand ROWD, RegisterOperand ROFS,
1377                                  RegisterOperand ROIdx> :
1378      MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
1379                [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
1380                                        ROIdx:$n))]> {
1381  bit usesCustomInserter = 1;
1382  bit hasNoSchedulingInfo = 1;
1383  string Constraints = "$wd = $wd_in";
1384}
1385
1386class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1387                          Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
1388                          RegisterOperand ROWS = ROWD,
1389                          InstrItinClass itin = NoItinerary> {
1390  dag OutOperandList = (outs ROWD:$wd);
1391  dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2);
1392  string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
1393  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1394                                              Imm:$n,
1395                                              ROWS:$ws,
1396                                              immz:$n2))];
1397  InstrItinClass Itinerary = itin;
1398  string Constraints = "$wd = $wd_in";
1399}
1400
1401class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
1402                        RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
1403                        RegisterOperand ROWT = ROWD,
1404                        InstrItinClass itin = NoItinerary> {
1405  dag OutOperandList = (outs ROWD:$wd);
1406  dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
1407  string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
1408  list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
1409  InstrItinClass Itinerary = itin;
1410}
1411
1412class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
1413                              RegisterOperand ROWD,
1414                              RegisterOperand ROWS = ROWD,
1415                              InstrItinClass itin = NoItinerary> {
1416  dag OutOperandList = (outs ROWD:$wd);
1417  dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
1418  string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
1419  list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
1420                                                ROWS:$ws))];
1421  InstrItinClass Itinerary = itin;
1422}
1423
1424class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
1425                          RegisterOperand ROWS = ROWD,
1426                          RegisterOperand ROWT = ROWD> :
1427      MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
1428                [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
1429
1430class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1431                     IsCommutable;
1432class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1433                     IsCommutable;
1434class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1435                     IsCommutable;
1436class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
1437                     IsCommutable;
1438
1439class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
1440                                       MSA128BOpnd>, IsCommutable;
1441class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
1442                                       MSA128HOpnd>, IsCommutable;
1443class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
1444                                       MSA128WOpnd>, IsCommutable;
1445class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
1446                                       MSA128DOpnd>, IsCommutable;
1447
1448class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
1449                                       MSA128BOpnd>, IsCommutable;
1450class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
1451                                       MSA128HOpnd>, IsCommutable;
1452class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
1453                                       MSA128WOpnd>, IsCommutable;
1454class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
1455                                       MSA128DOpnd>, IsCommutable;
1456
1457class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
1458                                       MSA128BOpnd>, IsCommutable;
1459class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
1460                                       MSA128HOpnd>, IsCommutable;
1461class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
1462                                       MSA128WOpnd>, IsCommutable;
1463class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
1464                                       MSA128DOpnd>, IsCommutable;
1465
1466class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
1467class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
1468class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
1469class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
1470
1471class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
1472                                      MSA128BOpnd>;
1473class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
1474                                      MSA128HOpnd>;
1475class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
1476                                      MSA128WOpnd>;
1477class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
1478                                      MSA128DOpnd>;
1479
1480class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
1481class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
1482class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
1483class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
1484
1485class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
1486                                     MSA128BOpnd>;
1487
1488class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
1489                                       MSA128BOpnd>;
1490class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
1491                                       MSA128HOpnd>;
1492class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
1493                                       MSA128WOpnd>;
1494class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
1495                                       MSA128DOpnd>;
1496
1497class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
1498                                       MSA128BOpnd>;
1499class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
1500                                       MSA128HOpnd>;
1501class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
1502                                       MSA128WOpnd>;
1503class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
1504                                       MSA128DOpnd>;
1505
1506class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
1507                     IsCommutable;
1508class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
1509                     IsCommutable;
1510class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
1511                     IsCommutable;
1512class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
1513                     IsCommutable;
1514
1515class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
1516                     IsCommutable;
1517class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
1518                     IsCommutable;
1519class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
1520                     IsCommutable;
1521class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
1522                     IsCommutable;
1523
1524class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
1525                                       MSA128BOpnd>, IsCommutable;
1526class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
1527                                       MSA128HOpnd>, IsCommutable;
1528class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
1529                                       MSA128WOpnd>, IsCommutable;
1530class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
1531                                       MSA128DOpnd>, IsCommutable;
1532
1533class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
1534                                       MSA128BOpnd>, IsCommutable;
1535class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
1536                                       MSA128HOpnd>, IsCommutable;
1537class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
1538                                       MSA128WOpnd>, IsCommutable;
1539class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
1540                                       MSA128DOpnd>, IsCommutable;
1541
1542class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr, MSA128BOpnd>;
1543class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr, MSA128HOpnd>;
1544class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr, MSA128WOpnd>;
1545class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr, MSA128DOpnd>;
1546
1547class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
1548                                         MSA128BOpnd>;
1549class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
1550                                         MSA128HOpnd>;
1551class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
1552                                         MSA128WOpnd>;
1553class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
1554                                         MSA128DOpnd>;
1555
1556class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
1557                                            MSA128BOpnd>;
1558class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
1559                                            MSA128HOpnd>;
1560class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
1561                                            MSA128WOpnd>;
1562class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
1563                                            MSA128DOpnd>;
1564
1565class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>;
1566class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>;
1567class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>;
1568class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>;
1569
1570class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
1571                                            MSA128BOpnd>;
1572class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
1573                                            MSA128HOpnd>;
1574class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
1575                                            MSA128WOpnd>;
1576class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
1577                                            MSA128DOpnd>;
1578
1579class BINSRI_B_DESC
1580    : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3,
1581                               MSA128BOpnd>;
1582class BINSRI_H_DESC
1583    : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4,
1584                               MSA128HOpnd>;
1585class BINSRI_W_DESC
1586    : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5,
1587                               MSA128WOpnd>;
1588class BINSRI_D_DESC
1589    : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6,
1590                               MSA128DOpnd>;
1591
1592class BMNZ_V_DESC {
1593  dag OutOperandList = (outs MSA128BOpnd:$wd);
1594  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1595                       MSA128BOpnd:$wt);
1596  string AsmString = "bmnz.v\t$wd, $ws, $wt";
1597  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1598                                                      MSA128BOpnd:$ws,
1599                                                      MSA128BOpnd:$wd_in))];
1600  InstrItinClass Itinerary = NoItinerary;
1601  string Constraints = "$wd = $wd_in";
1602}
1603
1604class BMNZI_B_DESC {
1605  dag OutOperandList = (outs MSA128BOpnd:$wd);
1606  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1607                           vsplat_uimm8:$u8);
1608  string AsmString = "bmnzi.b\t$wd, $ws, $u8";
1609  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1610                                                      MSA128BOpnd:$ws,
1611                                                      MSA128BOpnd:$wd_in))];
1612  InstrItinClass Itinerary = NoItinerary;
1613  string Constraints = "$wd = $wd_in";
1614}
1615
1616class BMZ_V_DESC {
1617  dag OutOperandList = (outs MSA128BOpnd:$wd);
1618  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1619                       MSA128BOpnd:$wt);
1620  string AsmString = "bmz.v\t$wd, $ws, $wt";
1621  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
1622                                                      MSA128BOpnd:$wd_in,
1623                                                      MSA128BOpnd:$ws))];
1624  InstrItinClass Itinerary = NoItinerary;
1625  string Constraints = "$wd = $wd_in";
1626}
1627
1628class BMZI_B_DESC {
1629  dag OutOperandList = (outs MSA128BOpnd:$wd);
1630  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1631                           vsplat_uimm8:$u8);
1632  string AsmString = "bmzi.b\t$wd, $ws, $u8";
1633  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
1634                                                      MSA128BOpnd:$wd_in,
1635                                                      MSA128BOpnd:$ws))];
1636  InstrItinClass Itinerary = NoItinerary;
1637  string Constraints = "$wd = $wd_in";
1638}
1639
1640class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg, MSA128BOpnd>;
1641class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg, MSA128HOpnd>;
1642class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg, MSA128WOpnd>;
1643class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg, MSA128DOpnd>;
1644
1645class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
1646                                         MSA128BOpnd>;
1647class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
1648                                         MSA128HOpnd>;
1649class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
1650                                         MSA128WOpnd>;
1651class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
1652                                         MSA128DOpnd>;
1653
1654class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
1655class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
1656class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
1657class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
1658
1659class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
1660
1661class BSEL_V_DESC {
1662  dag OutOperandList = (outs MSA128BOpnd:$wd);
1663  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1664                       MSA128BOpnd:$wt);
1665  string AsmString = "bsel.v\t$wd, $ws, $wt";
1666  // Note that vselect and BSEL_V treat the condition operand the opposite way
1667  // from each other.
1668  //   (vselect cond, if_set, if_clear)
1669  //   (BSEL_V cond, if_clear, if_set)
1670  list<dag> Pattern = [(set MSA128BOpnd:$wd,
1671                        (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
1672                                                     MSA128BOpnd:$ws))];
1673  InstrItinClass Itinerary = NoItinerary;
1674  string Constraints = "$wd = $wd_in";
1675}
1676
1677class BSELI_B_DESC {
1678  dag OutOperandList = (outs MSA128BOpnd:$wd);
1679  dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
1680                           vsplat_uimm8:$u8);
1681  string AsmString = "bseli.b\t$wd, $ws, $u8";
1682  // Note that vselect and BSEL_V treat the condition operand the opposite way
1683  // from each other.
1684  //   (vselect cond, if_set, if_clear)
1685  //   (BSEL_V cond, if_clear, if_set)
1686  list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
1687                                                      vsplati8_uimm8:$u8,
1688                                                      MSA128BOpnd:$ws))];
1689  InstrItinClass Itinerary = NoItinerary;
1690  string Constraints = "$wd = $wd_in";
1691}
1692
1693class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset, MSA128BOpnd>;
1694class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset, MSA128HOpnd>;
1695class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset, MSA128WOpnd>;
1696class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset, MSA128DOpnd>;
1697
1698class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
1699                                         MSA128BOpnd>;
1700class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
1701                                         MSA128HOpnd>;
1702class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
1703                                         MSA128WOpnd>;
1704class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
1705                                         MSA128DOpnd>;
1706
1707class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
1708class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
1709class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
1710class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
1711
1712class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
1713
1714class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
1715                   IsCommutable;
1716class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
1717                   IsCommutable;
1718class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
1719                   IsCommutable;
1720class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
1721                   IsCommutable;
1722
1723class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
1724                                     MSA128BOpnd>;
1725class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
1726                                     MSA128HOpnd>;
1727class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
1728                                     MSA128WOpnd>;
1729class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
1730                                     MSA128DOpnd>;
1731
1732class CFCMSA_DESC {
1733  dag OutOperandList = (outs GPR32Opnd:$rd);
1734  dag InOperandList = (ins MSA128CROpnd:$cs);
1735  string AsmString = "cfcmsa\t$rd, $cs";
1736  InstrItinClass Itinerary = NoItinerary;
1737  bit hasSideEffects = 1;
1738  bit isMoveReg = 1;
1739}
1740
1741class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
1742class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
1743class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
1744class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
1745
1746class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
1747class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
1748class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
1749class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
1750
1751class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
1752                                       vsplati8_simm5,  MSA128BOpnd>;
1753class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
1754                                       vsplati16_simm5, MSA128HOpnd>;
1755class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
1756                                       vsplati32_simm5, MSA128WOpnd>;
1757class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
1758                                       vsplati64_simm5, MSA128DOpnd>;
1759
1760class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
1761                                       vsplati8_uimm5,  MSA128BOpnd>;
1762class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
1763                                       vsplati16_uimm5, MSA128HOpnd>;
1764class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
1765                                       vsplati32_uimm5, MSA128WOpnd>;
1766class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
1767                                       vsplati64_uimm5, MSA128DOpnd>;
1768
1769class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
1770class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
1771class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
1772class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
1773
1774class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
1775class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
1776class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
1777class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
1778
1779class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
1780                                       vsplati8_simm5, MSA128BOpnd>;
1781class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
1782                                       vsplati16_simm5, MSA128HOpnd>;
1783class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
1784                                       vsplati32_simm5, MSA128WOpnd>;
1785class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
1786                                       vsplati64_simm5, MSA128DOpnd>;
1787
1788class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
1789                                       vsplati8_uimm5, MSA128BOpnd>;
1790class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
1791                                       vsplati16_uimm5, MSA128HOpnd>;
1792class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
1793                                       vsplati32_uimm5, MSA128WOpnd>;
1794class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
1795                                       vsplati64_uimm5, MSA128DOpnd>;
1796
1797class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8,  v16i8,
1798                                         uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1799                                         MSA128BOpnd>;
1800class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
1801                                         uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1802                                         MSA128HOpnd>;
1803class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
1804                                         uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1805                                         MSA128WOpnd>;
1806class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
1807                                         uimm1_ptr, immZExt1Ptr, GPR64Opnd,
1808                                         MSA128DOpnd>;
1809
1810class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8,  v16i8,
1811                                         uimm4_ptr, immZExt4Ptr, GPR32Opnd,
1812                                         MSA128BOpnd>;
1813class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
1814                                         uimm3_ptr, immZExt3Ptr, GPR32Opnd,
1815                                         MSA128HOpnd>;
1816class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
1817                                         uimm2_ptr, immZExt2Ptr, GPR32Opnd,
1818                                         MSA128WOpnd>;
1819
1820class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32,
1821                                                 uimm2_ptr, immZExt2Ptr, FGR32,
1822                                                 MSA128W>;
1823class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64,
1824                                                 uimm1_ptr, immZExt1Ptr, FGR64,
1825                                                 MSA128D>;
1826
1827class CTCMSA_DESC {
1828  dag OutOperandList = (outs);
1829  dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
1830  string AsmString = "ctcmsa\t$cd, $rs";
1831  InstrItinClass Itinerary = NoItinerary;
1832  bit hasSideEffects = 1;
1833  bit isMoveReg = 1;
1834}
1835
1836class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
1837class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
1838class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
1839class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
1840
1841class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
1842class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
1843class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
1844class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
1845
1846class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
1847                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1848                      IsCommutable;
1849class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
1850                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1851                      IsCommutable;
1852class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
1853                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1854                      IsCommutable;
1855
1856class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
1857                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
1858                      IsCommutable;
1859class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
1860                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
1861                      IsCommutable;
1862class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
1863                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
1864                      IsCommutable;
1865
1866class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
1867                                           MSA128HOpnd, MSA128BOpnd,
1868                                           MSA128BOpnd>, IsCommutable;
1869class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
1870                                           MSA128WOpnd, MSA128HOpnd,
1871                                           MSA128HOpnd>, IsCommutable;
1872class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
1873                                           MSA128DOpnd, MSA128WOpnd,
1874                                           MSA128WOpnd>, IsCommutable;
1875
1876class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
1877                                           MSA128HOpnd, MSA128BOpnd,
1878                                           MSA128BOpnd>, IsCommutable;
1879class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
1880                                           MSA128WOpnd, MSA128HOpnd,
1881                                           MSA128HOpnd>, IsCommutable;
1882class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
1883                                           MSA128DOpnd, MSA128WOpnd,
1884                                           MSA128WOpnd>, IsCommutable;
1885
1886class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
1887                                           MSA128HOpnd, MSA128BOpnd,
1888                                           MSA128BOpnd>;
1889class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
1890                                           MSA128WOpnd, MSA128HOpnd,
1891                                           MSA128HOpnd>;
1892class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
1893                                           MSA128DOpnd, MSA128WOpnd,
1894                                           MSA128WOpnd>;
1895
1896class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
1897                                           MSA128HOpnd, MSA128BOpnd,
1898                                           MSA128BOpnd>;
1899class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
1900                                           MSA128WOpnd, MSA128HOpnd,
1901                                           MSA128HOpnd>;
1902class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
1903                                           MSA128DOpnd, MSA128WOpnd,
1904                                           MSA128WOpnd>;
1905
1906class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
1907                    IsCommutable;
1908class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
1909                    IsCommutable;
1910
1911class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
1912                    IsCommutable;
1913class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
1914                    IsCommutable;
1915
1916class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
1917                    IsCommutable;
1918class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
1919                    IsCommutable;
1920
1921class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
1922                                        MSA128WOpnd>;
1923class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
1924                                        MSA128DOpnd>;
1925
1926class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
1927class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
1928
1929class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
1930class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
1931
1932class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
1933                    IsCommutable;
1934class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
1935                    IsCommutable;
1936
1937class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
1938                    IsCommutable;
1939class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
1940                    IsCommutable;
1941
1942class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
1943                     IsCommutable;
1944class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
1945                     IsCommutable;
1946
1947class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
1948                     IsCommutable;
1949class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
1950                     IsCommutable;
1951
1952class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
1953                     IsCommutable;
1954class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
1955                     IsCommutable;
1956
1957class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
1958                    IsCommutable;
1959class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
1960                    IsCommutable;
1961
1962class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
1963                     IsCommutable;
1964class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
1965                     IsCommutable;
1966
1967class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
1968class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
1969
1970class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
1971                                       MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
1972class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
1973                                       MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
1974
1975// The fexp2.df instruction multiplies the first operand by 2 to the power of
1976// the second operand. We therefore need a pseudo-insn in order to invent the
1977// 1.0 when we only need to match ISD::FEXP2.
1978class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
1979class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
1980let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
1981  class FEXP2_W_1_PSEUDO_DESC :
1982      MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
1983                [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
1984  class FEXP2_D_1_PSEUDO_DESC :
1985      MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
1986                [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
1987}
1988
1989class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
1990                                        MSA128WOpnd, MSA128HOpnd>;
1991class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
1992                                        MSA128DOpnd, MSA128WOpnd>;
1993
1994class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
1995                                        MSA128WOpnd, MSA128HOpnd>;
1996class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
1997                                        MSA128DOpnd, MSA128WOpnd>;
1998
1999class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
2000class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
2001
2002class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
2003class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
2004
2005class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
2006                                      MSA128WOpnd, MSA128HOpnd>;
2007class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
2008                                      MSA128DOpnd, MSA128WOpnd>;
2009
2010class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
2011                                      MSA128WOpnd, MSA128HOpnd>;
2012class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
2013                                      MSA128DOpnd, MSA128WOpnd>;
2014
2015class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
2016                                          MSA128BOpnd, GPR32Opnd>;
2017class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
2018                                          MSA128HOpnd, GPR32Opnd>;
2019class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
2020                                          MSA128WOpnd, GPR32Opnd>;
2021class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
2022                                          MSA128DOpnd, GPR64Opnd>;
2023
2024class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf32, MSA128W, FGR32>;
2025class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf64, MSA128D, FGR64>;
2026
2027class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
2028class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
2029
2030class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
2031class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
2032
2033class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
2034class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
2035
2036class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
2037                                        MSA128WOpnd>;
2038class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
2039                                        MSA128DOpnd>;
2040
2041class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
2042class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
2043
2044class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
2045                                        MSA128WOpnd>;
2046class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
2047                                        MSA128DOpnd>;
2048
2049class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>;
2050class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>;
2051
2052class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
2053class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
2054
2055class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
2056class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
2057
2058class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
2059class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
2060
2061class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
2062                                        MSA128WOpnd>;
2063class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
2064                                        MSA128DOpnd>;
2065
2066class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
2067class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
2068
2069class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
2070class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
2071
2072class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
2073class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
2074
2075class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
2076class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
2077
2078class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
2079class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
2080
2081class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
2082class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
2083
2084class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
2085class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
2086
2087class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
2088class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
2089
2090class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
2091                                       MSA128WOpnd>;
2092class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
2093                                       MSA128DOpnd>;
2094
2095class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
2096                                       MSA128WOpnd>;
2097class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
2098                                       MSA128DOpnd>;
2099
2100class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
2101                                       MSA128WOpnd>;
2102class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
2103                                       MSA128DOpnd>;
2104
2105class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
2106                                      MSA128WOpnd>;
2107class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
2108                                      MSA128DOpnd>;
2109
2110class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
2111                                       MSA128WOpnd>;
2112class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
2113                                       MSA128DOpnd>;
2114
2115class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
2116                                         MSA128WOpnd>;
2117class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
2118                                         MSA128DOpnd>;
2119
2120class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
2121                                         MSA128WOpnd>;
2122class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
2123                                         MSA128DOpnd>;
2124
2125class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
2126                                     MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
2127class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
2128                                     MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
2129
2130class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
2131                                          MSA128WOpnd>;
2132class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
2133                                          MSA128DOpnd>;
2134
2135class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
2136                                          MSA128WOpnd>;
2137class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
2138                                          MSA128DOpnd>;
2139
2140class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
2141                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2142class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
2143                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2144class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
2145                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2146
2147class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
2148                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2149class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
2150                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2151class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
2152                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2153
2154class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
2155                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2156class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
2157                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2158class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
2159                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2160
2161class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
2162                                       MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
2163class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
2164                                       MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
2165class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
2166                                       MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
2167
2168class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
2169class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
2170class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
2171class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
2172
2173class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
2174class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
2175class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
2176class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
2177
2178class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
2179class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
2180class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
2181class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
2182
2183class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
2184class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
2185class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
2186class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
2187
2188class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4,
2189                                           immZExt4Ptr, MSA128BOpnd, GPR32Opnd>;
2190class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3,
2191                                           immZExt3Ptr, MSA128HOpnd, GPR32Opnd>;
2192class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2,
2193                                           immZExt2Ptr, MSA128WOpnd, GPR32Opnd>;
2194class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1,
2195                                           immZExt1Ptr, MSA128DOpnd, GPR64Opnd>;
2196
2197class INSERT_B_VIDX_PSEUDO_DESC :
2198    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
2199class INSERT_H_VIDX_PSEUDO_DESC :
2200    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
2201class INSERT_W_VIDX_PSEUDO_DESC :
2202    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
2203class INSERT_D_VIDX_PSEUDO_DESC :
2204    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
2205
2206class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
2207                                                     uimm2, immZExt2Ptr,
2208                                                     MSA128WOpnd, FGR32Opnd>;
2209class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
2210                                                     uimm1, immZExt1Ptr,
2211                                                     MSA128DOpnd, FGR64Opnd>;
2212
2213class INSERT_FW_VIDX_PSEUDO_DESC :
2214    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
2215class INSERT_FD_VIDX_PSEUDO_DESC :
2216    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
2217
2218class INSERT_B_VIDX64_PSEUDO_DESC :
2219    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
2220class INSERT_H_VIDX64_PSEUDO_DESC :
2221    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
2222class INSERT_W_VIDX64_PSEUDO_DESC :
2223    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
2224class INSERT_D_VIDX64_PSEUDO_DESC :
2225    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
2226
2227class INSERT_FW_VIDX64_PSEUDO_DESC :
2228    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
2229class INSERT_FD_VIDX64_PSEUDO_DESC :
2230    MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
2231
2232class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4,
2233                                         MSA128BOpnd>;
2234class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, timmZExt3,
2235                                         MSA128HOpnd>;
2236class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, timmZExt2,
2237                                         MSA128WOpnd>;
2238class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt1,
2239                                         MSA128DOpnd>;
2240
2241class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2242                   ValueType TyNode, RegisterOperand ROWD,
2243                   Operand MemOpnd, ComplexPattern Addr = addrimm10,
2244                   InstrItinClass itin = NoItinerary> {
2245  dag OutOperandList = (outs ROWD:$wd);
2246  dag InOperandList = (ins MemOpnd:$addr);
2247  string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2248  list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
2249  InstrItinClass Itinerary = itin;
2250  string DecoderMethod = "DecodeMSA128Mem";
2251}
2252
2253class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>;
2254class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd,
2255                               mem_simm10_lsl1, addrimm10lsl1>;
2256class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd,
2257                               mem_simm10_lsl2, addrimm10lsl2>;
2258class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd,
2259                               mem_simm10_lsl3, addrimm10lsl3>;
2260
2261class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
2262class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
2263class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
2264class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
2265
2266class MSA_LOAD_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> :
2267  PseudoSE<(outs RO:$dst), (ins PtrRC:$ptr, GPR32:$imm),
2268           [(set RO:$dst, (intrinsic iPTR:$ptr, GPR32:$imm))]> {
2269  let hasNoSchedulingInfo = 1;
2270  let usesCustomInserter = 1;
2271}
2272
2273def LDR_D : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_d, MSA128DOpnd>;
2274def LDR_W : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_w, MSA128WOpnd>;
2275
2276class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
2277                    InstrItinClass itin = NoItinerary> {
2278  dag OutOperandList = (outs RORD:$rd);
2279  dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa);
2280  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
2281  list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt,
2282                                                (shl RORD:$rs,
2283                                                     immZExt2Lsa:$sa)))];
2284  InstrItinClass Itinerary = itin;
2285}
2286
2287class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>;
2288class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>;
2289
2290class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
2291                                            MSA128HOpnd>;
2292class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
2293                                            MSA128WOpnd>;
2294
2295class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
2296                                             MSA128HOpnd>;
2297class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
2298                                             MSA128WOpnd>;
2299
2300class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
2301class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
2302class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
2303class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
2304
2305class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
2306class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
2307class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
2308class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
2309
2310class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>;
2311class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>;
2312class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>;
2313class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>;
2314
2315class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>;
2316class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>;
2317class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>;
2318class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>;
2319
2320class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5,
2321                                       MSA128BOpnd>;
2322class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5,
2323                                       MSA128HOpnd>;
2324class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5,
2325                                       MSA128WOpnd>;
2326class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5,
2327                                       MSA128DOpnd>;
2328
2329class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5,
2330                                       MSA128BOpnd>;
2331class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5,
2332                                       MSA128HOpnd>;
2333class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5,
2334                                       MSA128WOpnd>;
2335class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5,
2336                                       MSA128DOpnd>;
2337
2338class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
2339class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
2340class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
2341class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
2342
2343class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>;
2344class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>;
2345class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>;
2346class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>;
2347
2348class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>;
2349class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>;
2350class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>;
2351class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>;
2352
2353class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5,
2354                                       MSA128BOpnd>;
2355class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5,
2356                                       MSA128HOpnd>;
2357class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5,
2358                                       MSA128WOpnd>;
2359class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5,
2360                                       MSA128DOpnd>;
2361
2362class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5,
2363                                       MSA128BOpnd>;
2364class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5,
2365                                       MSA128HOpnd>;
2366class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5,
2367                                       MSA128WOpnd>;
2368class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5,
2369                                       MSA128DOpnd>;
2370
2371class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
2372class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
2373class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
2374class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
2375
2376class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
2377class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
2378class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
2379class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
2380
2381class MOVE_V_DESC {
2382  dag OutOperandList = (outs MSA128BOpnd:$wd);
2383  dag InOperandList = (ins MSA128BOpnd:$ws);
2384  string AsmString = "move.v\t$wd, $ws";
2385  list<dag> Pattern = [];
2386  InstrItinClass Itinerary = NoItinerary;
2387  bit isMoveReg = 1;
2388}
2389
2390class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
2391                                            MSA128HOpnd>;
2392class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
2393                                            MSA128WOpnd>;
2394
2395class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
2396                                             MSA128HOpnd>;
2397class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
2398                                             MSA128WOpnd>;
2399
2400class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
2401class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
2402class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
2403class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
2404
2405class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
2406                                       MSA128HOpnd>;
2407class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
2408                                       MSA128WOpnd>;
2409
2410class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
2411                                        MSA128HOpnd>;
2412class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
2413                                        MSA128WOpnd>;
2414
2415class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
2416class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
2417class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
2418class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
2419
2420class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
2421class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
2422class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
2423class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
2424
2425class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
2426class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
2427class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
2428class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
2429
2430class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
2431class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
2432class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
2433class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
2434
2435class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
2436                                     MSA128BOpnd>;
2437
2438class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
2439class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
2440class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
2441class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
2442
2443class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
2444
2445class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
2446class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
2447class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
2448class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
2449
2450class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
2451class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
2452class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
2453class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
2454
2455class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
2456class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
2457class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
2458class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
2459
2460class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3,
2461                                         timmZExt3, MSA128BOpnd>;
2462class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4,
2463                                         timmZExt4, MSA128HOpnd>;
2464class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5,
2465                                         timmZExt5, MSA128WOpnd>;
2466class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6,
2467                                         timmZExt6, MSA128DOpnd>;
2468
2469class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3,
2470                                         timmZExt3, MSA128BOpnd>;
2471class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4,
2472                                         timmZExt4, MSA128HOpnd>;
2473class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5,
2474                                         timmZExt5, MSA128WOpnd>;
2475class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6,
2476                                         timmZExt6, MSA128DOpnd>;
2477
2478class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
2479class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
2480class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
2481
2482class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
2483class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
2484class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
2485class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
2486
2487class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
2488                                          MSA128BOpnd, MSA128BOpnd, uimm4,
2489                                          timmZExt4>;
2490class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
2491                                          MSA128HOpnd, MSA128HOpnd, uimm3,
2492                                          timmZExt3>;
2493class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
2494                                          MSA128WOpnd, MSA128WOpnd, uimm2,
2495                                          timmZExt2>;
2496class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
2497                                          MSA128DOpnd, MSA128DOpnd, uimm1,
2498                                          timmZExt1>;
2499
2500class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
2501class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
2502class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
2503class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
2504
2505class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
2506                                            MSA128BOpnd>;
2507class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
2508                                            MSA128HOpnd>;
2509class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
2510                                            MSA128WOpnd>;
2511class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
2512                                            MSA128DOpnd>;
2513
2514class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
2515                                            MSA128BOpnd>;
2516class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
2517                                            MSA128HOpnd>;
2518class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
2519                                            MSA128WOpnd>;
2520class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
2521                                            MSA128DOpnd>;
2522
2523class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
2524                                              MSA128BOpnd>;
2525class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
2526                                              MSA128HOpnd>;
2527class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
2528                                              MSA128WOpnd>;
2529class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
2530                                              MSA128DOpnd>;
2531
2532class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
2533class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
2534class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
2535class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
2536
2537class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
2538                                            MSA128BOpnd>;
2539class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
2540                                            MSA128HOpnd>;
2541class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
2542                                            MSA128WOpnd>;
2543class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
2544                                            MSA128DOpnd>;
2545
2546class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
2547class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
2548class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
2549class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
2550
2551class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3,
2552                                         timmZExt3, MSA128BOpnd>;
2553class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4,
2554                                         timmZExt4, MSA128HOpnd>;
2555class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5,
2556                                         timmZExt5, MSA128WOpnd>;
2557class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6,
2558                                         timmZExt6, MSA128DOpnd>;
2559
2560class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
2561class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
2562class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
2563class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
2564
2565class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
2566                                            MSA128BOpnd>;
2567class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
2568                                            MSA128HOpnd>;
2569class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
2570                                            MSA128WOpnd>;
2571class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
2572                                            MSA128DOpnd>;
2573
2574class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
2575class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
2576class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
2577class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
2578
2579class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3,
2580                                         timmZExt3, MSA128BOpnd>;
2581class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4,
2582                                         timmZExt4, MSA128HOpnd>;
2583class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5,
2584                                         timmZExt5, MSA128WOpnd>;
2585class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6,
2586                                         timmZExt6, MSA128DOpnd>;
2587
2588class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2589                   ValueType TyNode, RegisterOperand ROWD,
2590                   Operand MemOpnd, ComplexPattern Addr = addrimm10,
2591                   InstrItinClass itin = NoItinerary> {
2592  dag OutOperandList = (outs);
2593  dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
2594  string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
2595  list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
2596  InstrItinClass Itinerary = itin;
2597  string DecoderMethod = "DecodeMSA128Mem";
2598}
2599
2600class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>;
2601class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd,
2602                               mem_simm10_lsl1, addrimm10lsl1>;
2603class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd,
2604                               mem_simm10_lsl2, addrimm10lsl2>;
2605class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd,
2606                               mem_simm10_lsl3, addrimm10lsl3>;
2607
2608class MSA_STORE_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> :
2609  PseudoSE<(outs), (ins RO:$dst, PtrRC:$ptr, GPR32:$imm),
2610           [(intrinsic RO:$dst, iPTR:$ptr, GPR32:$imm)]> {
2611  let hasNoSchedulingInfo = 1;
2612  let usesCustomInserter = 1;
2613}
2614
2615def STR_D : MSA_STORE_PSEUDO_BASE<int_mips_str_d, MSA128DOpnd>;
2616def STR_W : MSA_STORE_PSEUDO_BASE<int_mips_str_w, MSA128WOpnd>;
2617
2618class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
2619                                       MSA128BOpnd>;
2620class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
2621                                       MSA128HOpnd>;
2622class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
2623                                       MSA128WOpnd>;
2624class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
2625                                       MSA128DOpnd>;
2626
2627class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
2628                                       MSA128BOpnd>;
2629class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
2630                                       MSA128HOpnd>;
2631class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
2632                                       MSA128WOpnd>;
2633class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
2634                                       MSA128DOpnd>;
2635
2636class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
2637                                         MSA128BOpnd>;
2638class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
2639                                         MSA128HOpnd>;
2640class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
2641                                         MSA128WOpnd>;
2642class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
2643                                         MSA128DOpnd>;
2644
2645class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
2646                                         MSA128BOpnd>;
2647class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
2648                                         MSA128HOpnd>;
2649class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
2650                                         MSA128WOpnd>;
2651class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
2652                                         MSA128DOpnd>;
2653
2654class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
2655class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
2656class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
2657class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
2658
2659class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
2660                                      MSA128BOpnd>;
2661class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
2662                                      MSA128HOpnd>;
2663class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
2664                                      MSA128WOpnd>;
2665class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
2666                                      MSA128DOpnd>;
2667
2668class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
2669class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
2670class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
2671class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
2672
2673class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
2674class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
2675class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
2676class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
2677
2678class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
2679                                     MSA128BOpnd>;
2680
2681// Instruction defs.
2682def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
2683def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
2684def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
2685def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
2686
2687def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
2688def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
2689def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
2690def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
2691
2692def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
2693def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
2694def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
2695def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
2696
2697def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
2698def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
2699def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
2700def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
2701
2702def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
2703def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
2704def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
2705def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
2706
2707def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
2708def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
2709def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
2710def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
2711
2712def AND_V : AND_V_ENC, AND_V_DESC;
2713def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
2714                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2715                                                MSA128BOpnd:$ws,
2716                                                MSA128BOpnd:$wt)>;
2717def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
2718                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2719                                                MSA128BOpnd:$ws,
2720                                                MSA128BOpnd:$wt)>;
2721def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
2722                     PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
2723                                                MSA128BOpnd:$ws,
2724                                                MSA128BOpnd:$wt)>;
2725
2726def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
2727
2728def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
2729def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
2730def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
2731def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
2732
2733def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
2734def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
2735def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
2736def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
2737
2738def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
2739def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
2740def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
2741def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
2742
2743def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
2744def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
2745def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
2746def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
2747
2748def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
2749def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
2750def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
2751def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
2752
2753def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
2754def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
2755def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
2756def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
2757
2758def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
2759def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
2760def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
2761def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
2762
2763def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
2764def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
2765def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
2766def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
2767
2768def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
2769def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
2770def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
2771def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
2772
2773def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
2774def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
2775def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
2776def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
2777
2778def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
2779def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
2780def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
2781def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
2782
2783def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
2784def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
2785def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
2786def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
2787
2788def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
2789
2790def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
2791
2792def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
2793
2794def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
2795
2796def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
2797def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
2798def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
2799def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
2800
2801def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
2802def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
2803def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
2804def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
2805
2806def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
2807def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
2808def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
2809def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
2810
2811def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
2812
2813def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
2814
2815class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
2816  MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
2817            [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
2818  // Note that vselect and BSEL_V treat the condition operand the opposite way
2819  // from each other.
2820  //   (vselect cond, if_set, if_clear)
2821  //   (BSEL_V cond, if_clear, if_set)
2822  PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
2823                              MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
2824  let Constraints = "$wd_in = $wd";
2825}
2826
2827def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
2828def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
2829def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
2830def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
2831def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
2832
2833def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
2834
2835def BSET_B : BSET_B_ENC, BSET_B_DESC;
2836def BSET_H : BSET_H_ENC, BSET_H_DESC;
2837def BSET_W : BSET_W_ENC, BSET_W_DESC;
2838def BSET_D : BSET_D_ENC, BSET_D_DESC;
2839
2840def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
2841def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
2842def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
2843def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
2844
2845def BZ_B : BZ_B_ENC, BZ_B_DESC;
2846def BZ_H : BZ_H_ENC, BZ_H_DESC;
2847def BZ_W : BZ_W_ENC, BZ_W_DESC;
2848def BZ_D : BZ_D_ENC, BZ_D_DESC;
2849
2850def BZ_V : BZ_V_ENC, BZ_V_DESC;
2851
2852def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
2853def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
2854def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
2855def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
2856
2857def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
2858def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
2859def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
2860def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
2861
2862def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
2863
2864def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
2865def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
2866def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
2867def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
2868
2869def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
2870def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
2871def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
2872def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
2873
2874def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
2875def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
2876def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
2877def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
2878
2879def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
2880def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
2881def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
2882def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
2883
2884def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
2885def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
2886def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
2887def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
2888
2889def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
2890def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
2891def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
2892def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
2893
2894def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
2895def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
2896def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
2897def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
2898
2899def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
2900def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
2901def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
2902def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
2903
2904def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
2905def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
2906def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
2907def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64;
2908
2909def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
2910def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
2911def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64;
2912
2913def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
2914def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
2915
2916def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
2917
2918def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
2919def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
2920def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
2921def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
2922
2923def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
2924def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
2925def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
2926def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
2927
2928def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
2929def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
2930def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
2931
2932def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
2933def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
2934def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
2935
2936def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
2937def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
2938def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
2939
2940def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
2941def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
2942def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
2943
2944def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
2945def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
2946def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
2947
2948def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
2949def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
2950def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
2951
2952def FADD_W : FADD_W_ENC, FADD_W_DESC;
2953def FADD_D : FADD_D_ENC, FADD_D_DESC;
2954
2955def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
2956def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
2957
2958def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
2959def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
2960
2961def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
2962def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
2963
2964def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
2965def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
2966
2967def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
2968def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
2969
2970def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
2971def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
2972
2973def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
2974def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
2975
2976def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
2977def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
2978
2979def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
2980def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
2981
2982def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
2983def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
2984
2985def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
2986def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
2987
2988def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
2989def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
2990
2991def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
2992def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
2993
2994def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
2995def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
2996
2997def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
2998def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
2999def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
3000def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
3001
3002def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
3003def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
3004
3005def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
3006def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
3007
3008def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
3009def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
3010
3011def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
3012def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
3013
3014def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
3015def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
3016
3017def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
3018def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
3019
3020def FILL_B : FILL_B_ENC, FILL_B_DESC;
3021def FILL_H : FILL_H_ENC, FILL_H_DESC;
3022def FILL_W : FILL_W_ENC, FILL_W_DESC;
3023def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64;
3024def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
3025def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
3026
3027def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
3028def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
3029
3030def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
3031def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
3032
3033def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
3034def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
3035
3036def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
3037def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
3038
3039def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
3040def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
3041
3042def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
3043def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
3044
3045def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
3046def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
3047
3048def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
3049def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
3050
3051def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
3052def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
3053
3054def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
3055def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
3056
3057def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
3058def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
3059
3060def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
3061def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
3062
3063def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
3064def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
3065
3066def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
3067def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
3068
3069def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
3070def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
3071
3072def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
3073def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
3074
3075def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
3076def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
3077
3078def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
3079def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
3080
3081def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
3082def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
3083
3084def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
3085def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
3086
3087def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
3088def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
3089
3090def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
3091def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
3092
3093def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
3094def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
3095
3096def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
3097def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
3098
3099def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
3100def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
3101
3102def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
3103def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
3104
3105def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
3106def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
3107
3108def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
3109def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
3110
3111def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
3112def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
3113
3114def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
3115              (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
3116              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3117def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
3118              (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
3119              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3120
3121def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)),
3122              (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>,
3123              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3124def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)),
3125              (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>,
3126              ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST;
3127
3128def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
3129def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
3130def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
3131
3132def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
3133def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
3134def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
3135
3136def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
3137def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
3138def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
3139
3140def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
3141def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
3142def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
3143
3144def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
3145def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
3146def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
3147def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
3148
3149def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
3150def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
3151def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
3152def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
3153
3154def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
3155def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
3156def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
3157def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
3158
3159def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
3160def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
3161def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
3162def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
3163
3164def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
3165def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
3166def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
3167def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64;
3168
3169// INSERT_FW_PSEUDO defined after INSVE_W
3170// INSERT_FD_PSEUDO defined after INSVE_D
3171
3172// There is a fourth operand that is not present in the encoding. Use a
3173// custom decoder to get a chance to add it.
3174let DecoderMethod = "DecodeINSVE_DF" in {
3175  def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
3176  def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
3177  def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
3178  def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
3179}
3180
3181def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
3182def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
3183
3184def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
3185def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
3186def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
3187def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
3188def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
3189def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
3190
3191def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC;
3192def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC;
3193def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC;
3194def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC;
3195def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC;
3196def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC;
3197
3198def LD_B: LD_B_ENC, LD_B_DESC;
3199def LD_H: LD_H_ENC, LD_H_DESC;
3200def LD_W: LD_W_ENC, LD_W_DESC;
3201def LD_D: LD_D_ENC, LD_D_DESC;
3202
3203def LDI_B : LDI_B_ENC, LDI_B_DESC;
3204def LDI_H : LDI_H_ENC, LDI_H_DESC;
3205def LDI_W : LDI_W_ENC, LDI_W_DESC;
3206def LDI_D : LDI_D_ENC, LDI_D_DESC;
3207
3208def LSA : LSA_ENC, LSA_DESC;
3209def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64;
3210
3211def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
3212def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
3213
3214def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
3215def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
3216
3217def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
3218def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
3219def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
3220def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
3221
3222def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
3223def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
3224def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
3225def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
3226
3227def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
3228def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
3229def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
3230def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
3231
3232def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
3233def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
3234def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
3235def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
3236
3237def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
3238def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
3239def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
3240def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
3241
3242def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
3243def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
3244def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
3245def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
3246
3247def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
3248def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
3249def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
3250def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
3251
3252def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
3253def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
3254def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
3255def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
3256
3257def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
3258def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
3259def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
3260def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
3261
3262def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
3263def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
3264def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
3265def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
3266
3267def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
3268def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
3269def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
3270def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
3271
3272def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
3273def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
3274def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
3275def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
3276
3277def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
3278def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
3279def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
3280def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
3281
3282def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
3283
3284def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
3285def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
3286
3287def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
3288def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
3289
3290def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
3291def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
3292def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
3293def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
3294
3295def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
3296def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
3297
3298def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
3299def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
3300
3301def MULV_B : MULV_B_ENC, MULV_B_DESC;
3302def MULV_H : MULV_H_ENC, MULV_H_DESC;
3303def MULV_W : MULV_W_ENC, MULV_W_DESC;
3304def MULV_D : MULV_D_ENC, MULV_D_DESC;
3305
3306def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
3307def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
3308def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
3309def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
3310
3311def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
3312def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
3313def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
3314def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
3315
3316def NOR_V : NOR_V_ENC, NOR_V_DESC;
3317def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
3318                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3319                                                MSA128BOpnd:$ws,
3320                                                MSA128BOpnd:$wt)>;
3321def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
3322                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3323                                                MSA128BOpnd:$ws,
3324                                                MSA128BOpnd:$wt)>;
3325def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
3326                     PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
3327                                                MSA128BOpnd:$ws,
3328                                                MSA128BOpnd:$wt)>;
3329
3330def NORI_B : NORI_B_ENC, NORI_B_DESC;
3331
3332def OR_V : OR_V_ENC, OR_V_DESC;
3333def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
3334                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3335                                              MSA128BOpnd:$ws,
3336                                              MSA128BOpnd:$wt)>;
3337def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
3338                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3339                                              MSA128BOpnd:$ws,
3340                                              MSA128BOpnd:$wt)>;
3341def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
3342                    PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
3343                                              MSA128BOpnd:$ws,
3344                                              MSA128BOpnd:$wt)>;
3345
3346def ORI_B : ORI_B_ENC, ORI_B_DESC;
3347
3348def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
3349def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
3350def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
3351def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
3352
3353def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
3354def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
3355def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
3356def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
3357
3358def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
3359def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
3360def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
3361def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
3362
3363def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
3364def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
3365def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
3366def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
3367
3368def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
3369def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
3370def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
3371def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
3372
3373def SHF_B : SHF_B_ENC, SHF_B_DESC;
3374def SHF_H : SHF_H_ENC, SHF_H_DESC;
3375def SHF_W : SHF_W_ENC, SHF_W_DESC;
3376
3377def SLD_B : SLD_B_ENC, SLD_B_DESC;
3378def SLD_H : SLD_H_ENC, SLD_H_DESC;
3379def SLD_W : SLD_W_ENC, SLD_W_DESC;
3380def SLD_D : SLD_D_ENC, SLD_D_DESC;
3381
3382def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
3383def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
3384def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
3385def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
3386
3387def SLL_B : SLL_B_ENC, SLL_B_DESC;
3388def SLL_H : SLL_H_ENC, SLL_H_DESC;
3389def SLL_W : SLL_W_ENC, SLL_W_DESC;
3390def SLL_D : SLL_D_ENC, SLL_D_DESC;
3391
3392def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
3393def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
3394def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
3395def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
3396
3397def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
3398def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
3399def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
3400def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
3401
3402def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
3403def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
3404def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
3405def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
3406
3407def SRA_B : SRA_B_ENC, SRA_B_DESC;
3408def SRA_H : SRA_H_ENC, SRA_H_DESC;
3409def SRA_W : SRA_W_ENC, SRA_W_DESC;
3410def SRA_D : SRA_D_ENC, SRA_D_DESC;
3411
3412def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
3413def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
3414def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
3415def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
3416
3417def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
3418def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
3419def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
3420def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
3421
3422def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
3423def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
3424def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
3425def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
3426
3427def SRL_B : SRL_B_ENC, SRL_B_DESC;
3428def SRL_H : SRL_H_ENC, SRL_H_DESC;
3429def SRL_W : SRL_W_ENC, SRL_W_DESC;
3430def SRL_D : SRL_D_ENC, SRL_D_DESC;
3431
3432def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
3433def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
3434def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
3435def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
3436
3437def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
3438def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
3439def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
3440def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
3441
3442def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
3443def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
3444def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
3445def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
3446
3447def ST_B: ST_B_ENC, ST_B_DESC;
3448def ST_H: ST_H_ENC, ST_H_DESC;
3449def ST_W: ST_W_ENC, ST_W_DESC;
3450def ST_D: ST_D_ENC, ST_D_DESC;
3451
3452def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
3453def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
3454def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
3455def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
3456
3457def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
3458def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
3459def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
3460def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
3461
3462def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
3463def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
3464def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
3465def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
3466
3467def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
3468def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
3469def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
3470def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
3471
3472def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
3473def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
3474def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
3475def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
3476
3477def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
3478def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
3479def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
3480def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
3481
3482def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
3483def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
3484def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
3485def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
3486
3487def XOR_V : XOR_V_ENC, XOR_V_DESC;
3488def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
3489                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3490                                                MSA128BOpnd:$ws,
3491                                                MSA128BOpnd:$wt)>;
3492def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
3493                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3494                                                MSA128BOpnd:$ws,
3495                                                MSA128BOpnd:$wt)>;
3496def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
3497                     PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
3498                                                MSA128BOpnd:$ws,
3499                                                MSA128BOpnd:$wt)>;
3500
3501def XORI_B : XORI_B_ENC, XORI_B_DESC;
3502
3503// Patterns.
3504class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
3505  Pat<pattern, result>, Requires<pred>;
3506
3507def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
3508             (COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
3509
3510def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>;
3511def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>;
3512def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>;
3513
3514def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr),
3515                   (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>;
3516def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr),
3517                   (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>;
3518def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr),
3519                   (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>;
3520
3521class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
3522                                RegisterOperand ROWS = ROWD,
3523                                InstrItinClass itin = NoItinerary> :
3524  MSAPseudo<(outs ROWD:$wd),
3525            (ins ROWS:$ws),
3526            [(set ROWD:$wd, (fabs ROWS:$ws))]> {
3527  InstrItinClass Itinerary = itin;
3528}
3529def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
3530             PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
3531                                           MSA128WOpnd:$ws)>;
3532def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
3533             PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
3534                                           MSA128DOpnd:$ws)>;
3535
3536class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3537                       RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
3538   MSAPat<(DstVT (bitconvert SrcVT:$src)),
3539          (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3540
3541// These are endian-independent because the element size doesnt change
3542def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
3543def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
3544def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
3545def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
3546def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
3547def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
3548
3549// Little endian bitcasts are always no-ops
3550def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
3551def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
3552def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
3553def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
3554def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
3555def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
3556
3557def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
3558def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
3559def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
3560def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
3561def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
3562
3563def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
3564def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
3565def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
3566def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
3567def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
3568
3569def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
3570def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
3571def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
3572def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
3573def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
3574
3575def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
3576def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
3577def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
3578def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
3579def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
3580
3581def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
3582def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
3583def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
3584def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
3585def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
3586
3587// Big endian bitcasts expand to shuffle instructions.
3588// This is because bitcast is defined to be a store/load sequence and the
3589// vector store/load instructions are mixed-endian with respect to the vector
3590// as a whole (little endian with respect to element order, but big endian
3591// elements).
3592
3593class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3594                                      RegisterClass DstRC, MSAInst Insn,
3595                                      RegisterClass ViaRC> :
3596  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3597         (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3598                           DstRC),
3599         [HasMSA, IsBE]>;
3600
3601class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3602                                    RegisterClass DstRC, MSAInst Insn,
3603                                    RegisterClass ViaRC> :
3604  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3605         (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3606                           DstRC),
3607         [HasMSA, IsBE]>;
3608
3609class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3610                                  RegisterClass DstRC> :
3611  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3612
3613class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3614                                  RegisterClass DstRC> :
3615  MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3616
3617class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
3618                                  RegisterClass DstRC> :
3619  MSAPat<(DstVT (bitconvert SrcVT:$src)),
3620         (COPY_TO_REGCLASS
3621           (SHF_W
3622             (COPY_TO_REGCLASS
3623               (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3624               MSA128W), 177),
3625           DstRC),
3626         [HasMSA, IsBE]>;
3627
3628class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
3629                                  RegisterClass DstRC> :
3630  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3631
3632class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
3633                                  RegisterClass DstRC> :
3634  MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
3635
3636class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
3637                                  RegisterClass DstRC> :
3638  MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
3639
3640def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
3641def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
3642def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
3643def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
3644def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
3645def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
3646
3647def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
3648def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
3649def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
3650def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
3651def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
3652
3653def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
3654def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
3655def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
3656def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
3657def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
3658
3659def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
3660def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
3661def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
3662def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
3663def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
3664
3665def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
3666def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
3667def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
3668def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
3669def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
3670
3671def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
3672def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
3673def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
3674def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
3675def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
3676
3677def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
3678def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
3679def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
3680def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
3681def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
3682
3683// Pseudos used to implement BNZ.df, and BZ.df
3684
3685class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
3686                                   RegisterClass RCWS> :
3687  MipsPseudo<(outs GPR32:$dst),
3688             (ins RCWS:$ws),
3689             [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
3690  bit usesCustomInserter = 1;
3691  bit hasNoSchedulingInfo = 1;
3692}
3693
3694def SNZ_B_PSEUDO
3695    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, MSA128B>;
3696def SNZ_H_PSEUDO
3697    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, MSA128H>;
3698def SNZ_W_PSEUDO
3699    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, MSA128W>;
3700def SNZ_D_PSEUDO
3701    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, MSA128D>;
3702def SNZ_V_PSEUDO
3703    : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, MSA128B>;
3704
3705def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, MSA128B>;
3706def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, MSA128H>;
3707def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, MSA128W>;
3708def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, MSA128D>;
3709def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, MSA128B>;
3710
3711// Pseudoes used to implement transparent fp16 support.
3712
3713let ASEPredicate = [HasMSA] in {
3714  let usesCustomInserter = 1 in {
3715    def ST_F16 :
3716        MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr),
3717                   [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]>;
3718    def LD_F16 :
3719        MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr),
3720                   [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]>;
3721  }
3722
3723  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
3724    def MSA_FP_EXTEND_W_PSEUDO :
3725        MipsPseudo<(outs FGR32Opnd:$fd), (ins MSA128F16:$ws),
3726                   [(set FGR32Opnd:$fd, (f32 (fpextend MSA128F16:$ws)))]>;
3727    def MSA_FP_ROUND_W_PSEUDO :
3728        MipsPseudo<(outs MSA128F16:$wd), (ins FGR32Opnd:$fs),
3729                   [(set MSA128F16:$wd, (f16 (fpround FGR32Opnd:$fs)))]>;
3730    def MSA_FP_EXTEND_D_PSEUDO :
3731        MipsPseudo<(outs FGR64Opnd:$fd), (ins MSA128F16:$ws),
3732                   [(set FGR64Opnd:$fd, (f64 (fpextend MSA128F16:$ws)))]>;
3733    def MSA_FP_ROUND_D_PSEUDO :
3734        MipsPseudo<(outs MSA128F16:$wd), (ins FGR64Opnd:$fs),
3735                   [(set MSA128F16:$wd, (f16 (fpround FGR64Opnd:$fs)))]>;
3736  }
3737
3738  def : MipsPat<(MipsTruncIntFP MSA128F16:$ws),
3739                (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>,
3740        ISA_MIPS1, ASE_MSA;
3741
3742  def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond),
3743                (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws),
3744                          (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>,
3745        ISA_MIPS1_NOT_32R6_64R6, ASE_MSA;
3746}
3747
3748def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
3749  APInt Imm;
3750  SDNode *BV = N->getOperand(0).getNode();
3751  EVT EltTy = N->getValueType(0).getVectorElementType();
3752
3753  return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
3754         Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;
3755}]>;
3756
3757def immi32Cst7  : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>;
3758def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>;
3759def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>;
3760
3761def vsplati8imm7 :   PatFrag<(ops node:$wt),
3762                             (and node:$wt, (vsplati8 immi32Cst7))>;
3763def vsplati16imm15 : PatFrag<(ops node:$wt),
3764                             (and node:$wt, (vsplati16 immi32Cst15))>;
3765def vsplati32imm31 : PatFrag<(ops node:$wt),
3766                             (and node:$wt, (vsplati32 immi32Cst31))>;
3767def vsplati64imm63 : PatFrag<(ops node:$wt),
3768                             (and node:$wt, vsplati64_imm_eq_63)>;
3769
3770class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> :
3771  MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))),
3772         (VT (Insn VT:$ws, VT:$wt))>;
3773
3774class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> :
3775  MSAPat<(VT (Node VT:$ws, (shl (vsplat_imm_eq_1), (Frag VT:$wt)))),
3776         (VT (Insn VT:$ws, VT:$wt))>;
3777
3778multiclass MSAShiftPats<SDNode Node, string Insn> {
3779  def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B),
3780                    (vsplati8 immi32Cst7)>;
3781  def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H),
3782                    (vsplati16 immi32Cst15)>;
3783  def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W),
3784                    (vsplati32 immi32Cst31)>;
3785  def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt,
3786                                                   vsplati64_imm_eq_63)))),
3787               (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3788}
3789
3790multiclass MSABitPats<SDNode Node, string Insn> {
3791  def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>;
3792  def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>;
3793  def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>;
3794  def : MSAPat<(Node v2i64:$ws, (shl (vsplat_imm_eq_1),
3795                                     (vsplati64imm63 v2i64:$wt))),
3796               (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>;
3797}
3798
3799defm : MSAShiftPats<shl, "SLL">;
3800defm : MSAShiftPats<srl, "SRL">;
3801defm : MSAShiftPats<sra, "SRA">;
3802defm : MSABitPats<xor, "BNEG">;
3803defm : MSABitPats<or, "BSET">;
3804
3805def : MSAPat<(and v16i8:$ws, (vnot (shl (vsplat_imm_eq_1),
3806                                        (vsplati8imm7 v16i8:$wt)))),
3807             (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>;
3808def : MSAPat<(and v8i16:$ws, (vnot (shl (vsplat_imm_eq_1),
3809                                        (vsplati16imm15 v8i16:$wt)))),
3810             (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>;
3811def : MSAPat<(and v4i32:$ws, (vnot (shl (vsplat_imm_eq_1),
3812                                        (vsplati32imm31 v4i32:$wt)))),
3813             (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>;
3814def : MSAPat<(and v2i64:$ws, (vnot (shl (vsplat_imm_eq_1),
3815                                        (vsplati64imm63 v2i64:$wt)))),
3816             (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>;
3817
3818// Vector extraction with fixed index.
3819//
3820// Extracting 32-bit values on MSA32 should always use COPY_S_W rather than
3821// COPY_U_W, even for the zero-extended case. This is because our forward
3822// compatibility strategy is to consider registers to be infinitely
3823// sign-extended so that a MIPS64 can execute MIPS32 code without getting
3824// different register values.
3825def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx),
3826             (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3827def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx),
3828             (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64;
3829
3830// Extracting 64-bit values on MSA64 should always use COPY_S_D rather than
3831// COPY_U_D, even for the zero-extended case. This is because our forward
3832// compatibility strategy is to consider registers to be infinitely
3833// sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64
3834// code without getting different register values.
3835def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx),
3836             (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3837def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx),
3838             (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64;
3839
3840// Vector extraction with variable index
3841def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
3842             (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3843                                                                  i32:$idx),
3844                                                         sub_lo)),
3845                                    GPR32), (i32 24))>;
3846def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
3847             (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3848                                                                  i32:$idx),
3849                                                         sub_lo)),
3850                                    GPR32), (i32 16))>;
3851def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
3852             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3853                                                             i32:$idx),
3854                                                    sub_lo)),
3855                               GPR32)>;
3856def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
3857             (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3858                                                             i32:$idx),
3859                                                    sub_64)),
3860                               GPR64), [HasMSA, IsGP64bit]>;
3861
3862def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
3863             (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3864                                                                  i32:$idx),
3865                                                         sub_lo)),
3866                                    GPR32), (i32 24))>;
3867def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
3868             (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3869                                                                  i32:$idx),
3870                                                         sub_lo)),
3871                                    GPR32), (i32 16))>;
3872def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
3873             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3874                                                             i32:$idx),
3875                                                    sub_lo)),
3876                               GPR32)>;
3877def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
3878             (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3879                                                             i32:$idx),
3880                                                    sub_64)),
3881                               GPR64), [HasMSA, IsGP64bit]>;
3882
3883def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
3884             (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3885                                           i32:$idx),
3886                                  sub_lo))>;
3887def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
3888             (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
3889                                           i32:$idx),
3890                                  sub_64))>;
3891
3892// Vector extraction with variable index (N64 ABI)
3893def : MSAPat<
3894  (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
3895  (SRA (COPY_TO_REGCLASS
3896         (i32 (EXTRACT_SUBREG
3897                (SPLAT_B v16i8:$ws,
3898                  (COPY_TO_REGCLASS
3899                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3900                sub_lo)),
3901         GPR32),
3902       (i32 24))>;
3903def : MSAPat<
3904  (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)),
3905  (SRA (COPY_TO_REGCLASS
3906         (i32 (EXTRACT_SUBREG
3907                (SPLAT_H v8i16:$ws,
3908                  (COPY_TO_REGCLASS
3909                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3910                sub_lo)),
3911         GPR32),
3912       (i32 16))>;
3913def : MSAPat<
3914  (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)),
3915  (COPY_TO_REGCLASS
3916    (i32 (EXTRACT_SUBREG
3917           (SPLAT_W v4i32:$ws,
3918             (COPY_TO_REGCLASS
3919               (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3920           sub_lo)),
3921    GPR32)>;
3922def : MSAPat<
3923  (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)),
3924  (COPY_TO_REGCLASS
3925    (i64 (EXTRACT_SUBREG
3926           (SPLAT_D v2i64:$ws,
3927             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3928           sub_64)),
3929    GPR64), [HasMSA, IsGP64bit]>;
3930
3931def : MSAPat<
3932  (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
3933  (SRL (COPY_TO_REGCLASS
3934         (i32 (EXTRACT_SUBREG
3935                 (SPLAT_B v16i8:$ws,
3936                   (COPY_TO_REGCLASS
3937                     (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3938                 sub_lo)),
3939         GPR32),
3940       (i32 24))>;
3941def : MSAPat<
3942  (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)),
3943  (SRL (COPY_TO_REGCLASS
3944         (i32 (EXTRACT_SUBREG
3945                (SPLAT_H v8i16:$ws,
3946                  (COPY_TO_REGCLASS
3947                    (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3948                sub_lo)),
3949         GPR32),
3950       (i32 16))>;
3951def : MSAPat<
3952  (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)),
3953  (COPY_TO_REGCLASS
3954    (i32 (EXTRACT_SUBREG
3955           (SPLAT_W v4i32:$ws,
3956             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3957           sub_lo)),
3958    GPR32)>;
3959def : MSAPat<
3960  (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)),
3961  (COPY_TO_REGCLASS
3962    (i64 (EXTRACT_SUBREG
3963           (SPLAT_D v2i64:$ws,
3964             (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3965           sub_64)),
3966    GPR64),
3967  [HasMSA, IsGP64bit]>;
3968
3969def : MSAPat<
3970  (f32 (vector_extract v4f32:$ws, i64:$idx)),
3971  (f32 (EXTRACT_SUBREG
3972         (SPLAT_W v4f32:$ws,
3973           (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3974         sub_lo))>;
3975def : MSAPat<
3976  (f64 (vector_extract v2f64:$ws, i64:$idx)),
3977  (f64 (EXTRACT_SUBREG
3978         (SPLAT_D v2f64:$ws,
3979           (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
3980         sub_64))>;
3981
3982def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
3983             (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
3984def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
3985             (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
3986def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
3987             (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
3988def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
3989             (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
3990def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
3991             (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
3992def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
3993             (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
3994def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
3995             (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
3996def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
3997             (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
3998