1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides Mips specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsMCTargetDesc.h" 14 #include "MipsAsmBackend.h" 15 #include "MipsBaseInfo.h" 16 #include "MipsELFStreamer.h" 17 #include "MipsInstPrinter.h" 18 #include "MipsMCAsmInfo.h" 19 #include "MipsMCNaCl.h" 20 #include "MipsTargetStreamer.h" 21 #include "TargetInfo/MipsTargetInfo.h" 22 #include "llvm/DebugInfo/CodeView/CodeView.h" 23 #include "llvm/MC/MCCodeEmitter.h" 24 #include "llvm/MC/MCELFStreamer.h" 25 #include "llvm/MC/MCInstrAnalysis.h" 26 #include "llvm/MC/MCInstrInfo.h" 27 #include "llvm/MC/MCObjectWriter.h" 28 #include "llvm/MC/MCRegisterInfo.h" 29 #include "llvm/MC/MCSubtargetInfo.h" 30 #include "llvm/MC/MCSymbol.h" 31 #include "llvm/MC/TargetRegistry.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/FormattedStream.h" 34 #include "llvm/TargetParser/Triple.h" 35 36 using namespace llvm; 37 38 #define GET_INSTRINFO_MC_DESC 39 #define ENABLE_INSTR_PREDICATE_VERIFIER 40 #include "MipsGenInstrInfo.inc" 41 42 #define GET_SUBTARGETINFO_MC_DESC 43 #include "MipsGenSubtargetInfo.inc" 44 45 #define GET_REGINFO_MC_DESC 46 #include "MipsGenRegisterInfo.inc" 47 48 void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) { 49 // Mapping from CodeView to MC register id. 50 static const struct { 51 codeview::RegisterId CVReg; 52 MCPhysReg Reg; 53 } RegMap[] = { 54 {codeview::RegisterId::MIPS_ZERO, Mips::ZERO}, 55 {codeview::RegisterId::MIPS_AT, Mips::AT}, 56 {codeview::RegisterId::MIPS_V0, Mips::V0}, 57 {codeview::RegisterId::MIPS_V1, Mips::V1}, 58 {codeview::RegisterId::MIPS_A0, Mips::A0}, 59 {codeview::RegisterId::MIPS_A1, Mips::A1}, 60 {codeview::RegisterId::MIPS_A2, Mips::A2}, 61 {codeview::RegisterId::MIPS_A3, Mips::A3}, 62 {codeview::RegisterId::MIPS_T0, Mips::T0}, 63 {codeview::RegisterId::MIPS_T1, Mips::T1}, 64 {codeview::RegisterId::MIPS_T2, Mips::T2}, 65 {codeview::RegisterId::MIPS_T3, Mips::T3}, 66 {codeview::RegisterId::MIPS_T4, Mips::T4}, 67 {codeview::RegisterId::MIPS_T5, Mips::T5}, 68 {codeview::RegisterId::MIPS_T6, Mips::T6}, 69 {codeview::RegisterId::MIPS_T7, Mips::T7}, 70 {codeview::RegisterId::MIPS_S0, Mips::S0}, 71 {codeview::RegisterId::MIPS_S1, Mips::S1}, 72 {codeview::RegisterId::MIPS_S2, Mips::S2}, 73 {codeview::RegisterId::MIPS_S3, Mips::S3}, 74 {codeview::RegisterId::MIPS_S4, Mips::S4}, 75 {codeview::RegisterId::MIPS_S5, Mips::S5}, 76 {codeview::RegisterId::MIPS_S6, Mips::S6}, 77 {codeview::RegisterId::MIPS_S7, Mips::S7}, 78 {codeview::RegisterId::MIPS_T8, Mips::T8}, 79 {codeview::RegisterId::MIPS_T9, Mips::T9}, 80 {codeview::RegisterId::MIPS_K0, Mips::K0}, 81 {codeview::RegisterId::MIPS_K1, Mips::K1}, 82 {codeview::RegisterId::MIPS_GP, Mips::GP}, 83 {codeview::RegisterId::MIPS_SP, Mips::SP}, 84 {codeview::RegisterId::MIPS_S8, Mips::FP}, 85 {codeview::RegisterId::MIPS_RA, Mips::RA}, 86 {codeview::RegisterId::MIPS_LO, Mips::HI0}, 87 {codeview::RegisterId::MIPS_HI, Mips::LO0}, 88 {codeview::RegisterId::MIPS_Fir, Mips::FCR0}, 89 {codeview::RegisterId::MIPS_Psr, Mips::COP012}, // CP0.Status 90 {codeview::RegisterId::MIPS_F0, Mips::F0}, 91 {codeview::RegisterId::MIPS_F1, Mips::F1}, 92 {codeview::RegisterId::MIPS_F2, Mips::F2}, 93 {codeview::RegisterId::MIPS_F3, Mips::F3}, 94 {codeview::RegisterId::MIPS_F4, Mips::F4}, 95 {codeview::RegisterId::MIPS_F5, Mips::F5}, 96 {codeview::RegisterId::MIPS_F6, Mips::F6}, 97 {codeview::RegisterId::MIPS_F7, Mips::F7}, 98 {codeview::RegisterId::MIPS_F8, Mips::F8}, 99 {codeview::RegisterId::MIPS_F9, Mips::F9}, 100 {codeview::RegisterId::MIPS_F10, Mips::F10}, 101 {codeview::RegisterId::MIPS_F11, Mips::F11}, 102 {codeview::RegisterId::MIPS_F12, Mips::F12}, 103 {codeview::RegisterId::MIPS_F13, Mips::F13}, 104 {codeview::RegisterId::MIPS_F14, Mips::F14}, 105 {codeview::RegisterId::MIPS_F15, Mips::F15}, 106 {codeview::RegisterId::MIPS_F16, Mips::F16}, 107 {codeview::RegisterId::MIPS_F17, Mips::F17}, 108 {codeview::RegisterId::MIPS_F18, Mips::F18}, 109 {codeview::RegisterId::MIPS_F19, Mips::F19}, 110 {codeview::RegisterId::MIPS_F20, Mips::F20}, 111 {codeview::RegisterId::MIPS_F21, Mips::F21}, 112 {codeview::RegisterId::MIPS_F22, Mips::F22}, 113 {codeview::RegisterId::MIPS_F23, Mips::F23}, 114 {codeview::RegisterId::MIPS_F24, Mips::F24}, 115 {codeview::RegisterId::MIPS_F25, Mips::F25}, 116 {codeview::RegisterId::MIPS_F26, Mips::F26}, 117 {codeview::RegisterId::MIPS_F27, Mips::F27}, 118 {codeview::RegisterId::MIPS_F28, Mips::F28}, 119 {codeview::RegisterId::MIPS_F29, Mips::F29}, 120 {codeview::RegisterId::MIPS_F30, Mips::F30}, 121 {codeview::RegisterId::MIPS_F31, Mips::F31}, 122 {codeview::RegisterId::MIPS_Fsr, Mips::FCR31}, 123 }; 124 for (const auto &I : RegMap) 125 MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg)); 126 } 127 128 namespace { 129 class MipsWinCOFFTargetStreamer : public MipsTargetStreamer { 130 public: 131 MipsWinCOFFTargetStreamer(MCStreamer &S) : MipsTargetStreamer(S) {} 132 }; 133 } // end namespace 134 135 /// Select the Mips CPU for the given triple and cpu name. 136 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) { 137 if (CPU.empty() || CPU == "generic") { 138 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) { 139 if (TT.isMIPS32()) 140 CPU = "mips32r6"; 141 else 142 CPU = "mips64r6"; 143 } else { 144 if (TT.isMIPS32()) 145 CPU = "mips32"; 146 else 147 CPU = "mips64"; 148 } 149 } 150 return CPU; 151 } 152 153 static MCInstrInfo *createMipsMCInstrInfo() { 154 MCInstrInfo *X = new MCInstrInfo(); 155 InitMipsMCInstrInfo(X); 156 return X; 157 } 158 159 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) { 160 MCRegisterInfo *X = new MCRegisterInfo(); 161 InitMipsMCRegisterInfo(X, Mips::RA); 162 return X; 163 } 164 165 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT, 166 StringRef CPU, StringRef FS) { 167 CPU = MIPS_MC::selectMipsCPU(TT, CPU); 168 return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 169 } 170 171 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, 172 const Triple &TT, 173 const MCTargetOptions &Options) { 174 MCAsmInfo *MAI; 175 176 if (TT.isOSWindows()) 177 MAI = new MipsCOFFMCAsmInfo(); 178 else 179 MAI = new MipsELFMCAsmInfo(TT, Options); 180 181 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); 182 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP); 183 MAI->addInitialFrameState(Inst); 184 185 return MAI; 186 } 187 188 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T, 189 unsigned SyntaxVariant, 190 const MCAsmInfo &MAI, 191 const MCInstrInfo &MII, 192 const MCRegisterInfo &MRI) { 193 return new MipsInstPrinter(MAI, MII, MRI); 194 } 195 196 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, 197 std::unique_ptr<MCAsmBackend> &&MAB, 198 std::unique_ptr<MCObjectWriter> &&OW, 199 std::unique_ptr<MCCodeEmitter> &&Emitter) { 200 MCStreamer *S; 201 if (!T.isOSNaCl()) 202 S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW), 203 std::move(Emitter)); 204 else 205 S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW), 206 std::move(Emitter)); 207 return S; 208 } 209 210 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S, 211 formatted_raw_ostream &OS, 212 MCInstPrinter *InstPrint) { 213 return new MipsTargetAsmStreamer(S, OS); 214 } 215 216 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) { 217 return new MipsTargetStreamer(S); 218 } 219 220 static MCTargetStreamer * 221 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 222 if (STI.getTargetTriple().isOSBinFormatCOFF()) 223 return new MipsWinCOFFTargetStreamer(S); 224 return new MipsTargetELFStreamer(S, STI); 225 } 226 227 namespace { 228 229 class MipsMCInstrAnalysis : public MCInstrAnalysis { 230 public: 231 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 232 233 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 234 uint64_t &Target) const override { 235 unsigned NumOps = Inst.getNumOperands(); 236 if (NumOps == 0) 237 return false; 238 switch (Info->get(Inst.getOpcode()).operands()[NumOps - 1].OperandType) { 239 case MCOI::OPERAND_UNKNOWN: 240 case MCOI::OPERAND_IMMEDIATE: { 241 // j, jal, jalx, jals 242 // Absolute branch within the current 256 MB-aligned region 243 uint64_t Region = Addr & ~uint64_t(0xfffffff); 244 Target = Region + Inst.getOperand(NumOps - 1).getImm(); 245 return true; 246 } 247 case MCOI::OPERAND_PCREL: 248 // b, beq ... 249 Target = Addr + Inst.getOperand(NumOps - 1).getImm(); 250 return true; 251 default: 252 return false; 253 } 254 } 255 }; 256 } 257 258 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) { 259 return new MipsMCInstrAnalysis(Info); 260 } 261 262 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() { 263 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(), 264 &getTheMips64Target(), &getTheMips64elTarget()}) { 265 // Register the MC asm info. 266 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); 267 268 // Register the MC instruction info. 269 TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo); 270 271 // Register the MC register info. 272 TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo); 273 274 // Register the elf streamer. 275 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer); 276 277 // Register the asm target streamer. 278 TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer); 279 280 TargetRegistry::RegisterNullTargetStreamer(*T, 281 createMipsNullTargetStreamer); 282 283 TargetRegistry::RegisterCOFFStreamer(*T, createMipsWinCOFFStreamer); 284 285 // Register the MC subtarget info. 286 TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo); 287 288 // Register the MC instruction analyzer. 289 TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis); 290 291 // Register the MCInstPrinter. 292 TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter); 293 294 TargetRegistry::RegisterObjectTargetStreamer( 295 *T, createMipsObjectTargetStreamer); 296 297 // Register the asm backend. 298 TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend); 299 } 300 301 // Register the MC Code Emitter 302 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()}) 303 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); 304 305 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) 306 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); 307 } 308