1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Mips implementation of the TargetInstrInfo class. 10 // 11 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in 12 // order for MipsLongBranch pass to work correctly when the code has inline 13 // assembly. The returned value doesn't have to be the asm instruction's exact 14 // size in bytes; MipsLongBranch only expects it to be the correct upper bound. 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 18 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 19 20 #include "MCTargetDesc/MipsMCTargetDesc.h" 21 #include "Mips.h" 22 #include "MipsRegisterInfo.h" 23 #include "llvm/ADT/ArrayRef.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineMemOperand.h" 27 #include "llvm/CodeGen/TargetInstrInfo.h" 28 #include <cstdint> 29 30 #define GET_INSTRINFO_HEADER 31 #include "MipsGenInstrInfo.inc" 32 33 namespace llvm { 34 35 class MachineInstr; 36 class MachineOperand; 37 class MipsSubtarget; 38 class TargetRegisterClass; 39 class TargetRegisterInfo; 40 41 class MipsInstrInfo : public MipsGenInstrInfo { 42 virtual void anchor(); 43 44 protected: 45 const MipsSubtarget &Subtarget; 46 unsigned UncondBrOpc; 47 48 public: 49 enum BranchType { 50 BT_None, // Couldn't analyze branch. 51 BT_NoBranch, // No branches found. 52 BT_Uncond, // One unconditional branch. 53 BT_Cond, // One conditional branch. 54 BT_CondUncond, // A conditional branch followed by an unconditional branch. 55 BT_Indirect // One indirct branch. 56 }; 57 58 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); 59 60 static const MipsInstrInfo *create(MipsSubtarget &STI); 61 62 /// Branch Analysis 63 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 64 MachineBasicBlock *&FBB, 65 SmallVectorImpl<MachineOperand> &Cond, 66 bool AllowModify) const override; 67 68 unsigned removeBranch(MachineBasicBlock &MBB, 69 int *BytesRemoved = nullptr) const override; 70 71 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 73 const DebugLoc &DL, 74 int *BytesAdded = nullptr) const override; 75 76 bool 77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 78 79 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 80 MachineBasicBlock *&FBB, 81 SmallVectorImpl<MachineOperand> &Cond, 82 bool AllowModify, 83 SmallVectorImpl<MachineInstr *> &BranchInstrs) const; 84 85 /// Determine the opcode of a non-delay slot form for a branch if one exists. 86 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const; 87 88 /// Determine if the branch target is in range. 89 bool isBranchOffsetInRange(unsigned BranchOpc, 90 int64_t BrOffset) const override; 91 92 bool SafeAfterMflo(const MachineInstr &MI) const; 93 94 /// Predicate to determine if an instruction can go in a forbidden slot. 95 bool SafeInForbiddenSlot(const MachineInstr &MI) const; 96 97 /// Predicate to determine if an instruction can go in an FPU delay slot. 98 bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, 99 const MachineInstr &FPUMI) const; 100 101 /// Predicate to determine if an instruction can go in a load delay slot. 102 bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, 103 const MachineInstr &LoadMI) const; 104 105 bool IsMfloOrMfhi(const MachineInstr &MI) const; 106 107 /// Predicate to determine if an instruction has a forbidden slot. 108 bool HasForbiddenSlot(const MachineInstr &MI) const; 109 110 /// Predicate to determine if an instruction has an FPU delay slot. 111 bool HasFPUDelaySlot(const MachineInstr &MI) const; 112 113 /// Predicate to determine if an instruction has a load delay slot. 114 bool HasLoadDelaySlot(const MachineInstr &MI) const; 115 116 /// Insert nop instruction when hazard condition is found 117 void insertNoop(MachineBasicBlock &MBB, 118 MachineBasicBlock::iterator MI) const override; 119 120 /// Insert an ISA appropriate `nop`. 121 // FIXME: Add support for MIPS16e. 122 MachineInstrBuilder insertNop(MachineBasicBlock &MBB, 123 MachineBasicBlock::iterator MI, 124 DebugLoc DL) const; 125 126 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 127 /// such, whenever a client has an instance of instruction info, it should 128 /// always be able to get register info as well (through this method). 129 virtual const MipsRegisterInfo &getRegisterInfo() const = 0; 130 131 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; 132 133 virtual bool isBranchWithImm(unsigned Opc) const { 134 return false; 135 } 136 137 /// Return the number of bytes of code the specified instruction may be. 138 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 139 140 void storeRegToStackSlot( 141 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, 142 bool isKill, int FrameIndex, const TargetRegisterClass *RC, 143 const TargetRegisterInfo *TRI, Register VReg, 144 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override { 145 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0, Flags); 146 } 147 148 void loadRegFromStackSlot( 149 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 150 Register DestReg, int FrameIndex, const TargetRegisterClass *RC, 151 const TargetRegisterInfo *TRI, Register VReg, 152 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override { 153 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0, Flags); 154 } 155 156 virtual void 157 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 158 Register SrcReg, bool isKill, int FrameIndex, 159 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 160 int64_t Offset, 161 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0; 162 163 virtual void loadRegFromStack( 164 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, 165 int FrameIndex, const TargetRegisterClass *RC, 166 const TargetRegisterInfo *TRI, int64_t Offset, 167 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0; 168 169 virtual void adjustStackPtr(unsigned SP, int64_t Amount, 170 MachineBasicBlock &MBB, 171 MachineBasicBlock::iterator I) const = 0; 172 173 /// Create an instruction which has the same operands and memory operands 174 /// as MI but has a new opcode. 175 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, 176 MachineBasicBlock::iterator I) const; 177 178 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 179 unsigned &SrcOpIdx2) const override; 180 181 /// Perform target specific instruction verification. 182 bool verifyInstruction(const MachineInstr &MI, 183 StringRef &ErrInfo) const override; 184 185 std::pair<unsigned, unsigned> 186 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 187 188 ArrayRef<std::pair<unsigned, const char *>> 189 getSerializableDirectMachineOperandTargetFlags() const override; 190 191 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 192 Register Reg) const override; 193 194 std::optional<ParamLoadedValue> 195 describeLoadedValue(const MachineInstr &MI, Register Reg) const override; 196 197 protected: 198 bool isZeroImm(const MachineOperand &op) const; 199 200 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, 201 MachineMemOperand::Flags Flags) const; 202 203 private: 204 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; 205 206 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 207 MachineBasicBlock *&BB, 208 SmallVectorImpl<MachineOperand> &Cond) const; 209 210 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 211 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const; 212 }; 213 214 /// Create MipsInstrInfo objects. 215 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); 216 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); 217 218 namespace Mips { 219 // Mask assignments for floating-point. 220 enum FClassMask { 221 FClassMaskSignalingNaN = 1 << 0, 222 FClassMaskQuietNaN = 1 << 1, 223 FClassMaskNegativeInfinity = 1 << 2, 224 FClassMaskNegativeNormal = 1 << 3, 225 FClassMaskNegativeSubnormal = 1 << 4, 226 FClassMaskNegativeZero = 1 << 5, 227 FClassMaskPositiveInfinity = 1 << 6, 228 FClassMaskPositiveNormal = 1 << 7, 229 FClassMaskPositiveSubnormal = 1 << 8, 230 FClassMaskPositiveZero = 1 << 9 231 }; 232 233 } // namespace Mips 234 235 } // end namespace llvm 236 237 #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 238