1//===- LoongArchInstrFormats.td - LoongArch Instr. Formats -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Describe LoongArch instructions format 11// 12// opcode - operation code. 13// rd - destination register operand. 14// r{j/k} - source register operand. 15// immN - immediate data operand. 16// 17//===----------------------------------------------------------------------===// 18 19class LAInst<dag outs, dag ins, string opcstr, string opnstr, 20 list<dag> pattern = []> 21 : Instruction { 22 field bits<32> Inst; 23 // SoftFail is a field the disassembler can use to provide a way for 24 // instructions to not match without killing the whole decode process. It is 25 // mainly used for ARM, but Tablegen expects this field to exist or it fails 26 // to build the decode table. 27 field bits<32> SoftFail = 0; 28 29 let Namespace = "LoongArch"; 30 let Size = 4; 31 let OutOperandList = outs; 32 let InOperandList = ins; 33 let AsmString = opcstr # "\t" # opnstr; 34 let Pattern = pattern; 35 36 // Target-specific instruction info and defaults 37 38 bit IsSubjectToAMORdConstraint = 0; 39 let TSFlags{0} = IsSubjectToAMORdConstraint; 40 41 bit IsAMCAS = 0; 42 let TSFlags{1} = IsAMCAS; 43} 44 45// Pseudo instructions 46class Pseudo<dag outs, dag ins, list<dag> pattern = [], string opcstr = "", 47 string opnstr = ""> 48 : LAInst<outs, ins, opcstr, opnstr, pattern> { 49 let isPseudo = 1; 50 let isCodeGenOnly = 1; 51} 52 53class deriveInsnMnemonic<string name> { 54 string ret = !tolower(!subst("@", "_", !subst("_", ".", !subst("__", "@", name)))); 55} 56 57// 2R-type 58// <opcode | rj | rd> 59class Fmt2R<bits<32> op, dag outs, dag ins, string opnstr, 60 list<dag> pattern = []> 61 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 62 bits<5> rj; 63 bits<5> rd; 64 65 let Inst{31-0} = op; 66 let Inst{9-5} = rj; 67 let Inst{4-0} = rd; 68} 69 70// 3R-type 71// <opcode | rk | rj | rd> 72class Fmt3R<bits<32> op, dag outs, dag ins, string opnstr, 73 list<dag> pattern = []> 74 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 75 bits<5> rk; 76 bits<5> rj; 77 bits<5> rd; 78 79 let Inst{31-0} = op; 80 let Inst{14-10} = rk; 81 let Inst{9-5} = rj; 82 let Inst{4-0} = rd; 83} 84 85// 3RI2-type 86// <opcode | I2 | rk | rj | rd> 87class Fmt3RI2<bits<32> op, dag outs, dag ins, string opnstr, 88 list<dag> pattern = []> 89 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 90 bits<2> imm2; 91 bits<5> rk; 92 bits<5> rj; 93 bits<5> rd; 94 95 let Inst{31-0} = op; 96 let Inst{16-15} = imm2; 97 let Inst{14-10} = rk; 98 let Inst{9-5} = rj; 99 let Inst{4-0} = rd; 100} 101 102// 3RI3-type 103// <opcode | I3 | rk | rj | rd> 104class Fmt3RI3<bits<32> op, dag outs, dag ins, string opnstr, 105 list<dag> pattern = []> 106 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 107 bits<3> imm3; 108 bits<5> rk; 109 bits<5> rj; 110 bits<5> rd; 111 112 let Inst{31-0} = op; 113 let Inst{17-15} = imm3; 114 let Inst{14-10} = rk; 115 let Inst{9-5} = rj; 116 let Inst{4-0} = rd; 117} 118 119// 2RI5-type 120// <opcode | I5 | rj | rd> 121class Fmt2RI5<bits<32> op, dag outs, dag ins, string opnstr, 122 list<dag> pattern = []> 123 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 124 bits<5> imm5; 125 bits<5> rj; 126 bits<5> rd; 127 128 let Inst{31-0} = op; 129 let Inst{14-10} = imm5; 130 let Inst{9-5} = rj; 131 let Inst{4-0} = rd; 132} 133 134// 2RI6-type 135// <opcode | I6 | rj | rd> 136class Fmt2RI6<bits<32> op, dag outs, dag ins, string opnstr, 137 list<dag> pattern = []> 138 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 139 bits<6> imm6; 140 bits<5> rj; 141 bits<5> rd; 142 143 let Inst{31-0} = op; 144 let Inst{15-10} = imm6; 145 let Inst{9-5} = rj; 146 let Inst{4-0} = rd; 147} 148 149// 2RI8-type 150// <opcode | I8 | rj | rd> 151class Fmt2RI8<bits<32> op, dag outs, dag ins, string opnstr, 152 list<dag> pattern = []> 153 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 154 bits<8> imm8; 155 bits<5> rj; 156 bits<5> rd; 157 158 let Inst{31-0} = op; 159 let Inst{17-10} = imm8; 160 let Inst{9-5} = rj; 161 let Inst{4-0} = rd; 162} 163 164// 2RI12-type 165// <opcode | I12 | rj | rd> 166class Fmt2RI12<bits<32> op, dag outs, dag ins, string opnstr, 167 list<dag> pattern = []> 168 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 169 bits<12> imm12; 170 bits<5> rj; 171 bits<5> rd; 172 173 let Inst{31-0} = op; 174 let Inst{21-10} = imm12; 175 let Inst{9-5} = rj; 176 let Inst{4-0} = rd; 177} 178 179// 2RI14-type 180// <opcode | I14 | rj | rd> 181class Fmt2RI14<bits<32> op, dag outs, dag ins, string opnstr, 182 list<dag> pattern = []> 183 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 184 bits<14> imm14; 185 bits<5> rj; 186 bits<5> rd; 187 188 let Inst{31-0} = op; 189 let Inst{23-10} = imm14; 190 let Inst{9-5} = rj; 191 let Inst{4-0} = rd; 192} 193 194// 2RI16-type 195// <opcode | I16 | rj | rd> 196class Fmt2RI16<bits<32> op, dag outs, dag ins, string opnstr, 197 list<dag> pattern = []> 198 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 199 bits<16> imm16; 200 bits<5> rj; 201 bits<5> rd; 202 203 let Inst{31-0} = op; 204 let Inst{25-10} = imm16; 205 let Inst{9-5} = rj; 206 let Inst{4-0} = rd; 207} 208 209// 1RI20-type 210// <opcode | I20 | rd> 211class Fmt1RI20<bits<32> op, dag outs, dag ins, string opnstr, 212 list<dag> pattern = []> 213 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 214 bits<20> imm20; 215 bits<5> rd; 216 217 let Inst{31-0} = op; 218 let Inst{24-5} = imm20; 219 let Inst{4-0} = rd; 220} 221 222// 1RI21-type 223// <opcode | I21[15:0] | rj | I21[20:16]> 224class Fmt1RI21<bits<32> op, dag outs, dag ins, string opnstr, 225 list<dag> pattern = []> 226 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 227 bits<21> imm21; 228 bits<5> rj; 229 230 let Inst{31-0} = op; 231 let Inst{25-10} = imm21{15-0}; 232 let Inst{9-5} = rj; 233 let Inst{4-0} = imm21{20-16}; 234} 235 236// I15-type 237// <opcode | I15> 238class FmtI15<bits<32> op, dag outs, dag ins, string opnstr, 239 list<dag> pattern = []> 240 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 241 bits<15> imm15; 242 243 let Inst{31-0} = op; 244 let Inst{14-0} = imm15; 245} 246 247// I26-type 248// <opcode | I26[15:0] | I26[25:16]> 249class FmtI26<bits<32> op, dag outs, dag ins, string opnstr, 250 list<dag> pattern = []> 251 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 252 bits<26> imm26; 253 254 let Inst{31-0} = op; 255 let Inst{25-10} = imm26{15-0}; 256 let Inst{9-0} = imm26{25-16}; 257} 258 259// FmtBSTR_W 260// <opcode | msbw | lsbw | rj | rd> 261class FmtBSTR_W<bits<32> op, dag outs, dag ins, string opnstr, 262 list<dag> pattern = []> 263 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 264 bits<5> msbw; 265 bits<5> lsbw; 266 bits<5> rj; 267 bits<5> rd; 268 269 let Inst{31-0} = op; 270 let Inst{20-16} = msbw; 271 let Inst{14-10} = lsbw; 272 let Inst{9-5} = rj; 273 let Inst{4-0} = rd; 274} 275 276// FmtBSTR_D 277// <opcode | msbd | lsbd | rj | rd> 278class FmtBSTR_D<bits<32> op, dag outs, dag ins, string opnstr, 279 list<dag> pattern = []> 280 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 281 bits<6> msbd; 282 bits<6> lsbd; 283 bits<5> rj; 284 bits<5> rd; 285 286 let Inst{31-0} = op; 287 let Inst{21-16} = msbd; 288 let Inst{15-10} = lsbd; 289 let Inst{9-5} = rj; 290 let Inst{4-0} = rd; 291} 292 293// FmtASRT 294// <opcode | rk | rj> 295class FmtASRT<bits<32> op, dag outs, dag ins, string opnstr, 296 list<dag> pattern = []> 297 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 298 bits<5> rk; 299 bits<5> rj; 300 301 let Inst{31-0} = op; 302 let Inst{14-10} = rk; 303 let Inst{9-5} = rj; 304} 305 306// FmtPRELD 307// < 0b0010101011 | I12 | rj | I5> 308class FmtPRELD<dag outs, dag ins, string opnstr, list<dag> pattern = []> 309 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 310 bits<12> imm12; 311 bits<5> rj; 312 bits<5> imm5; 313 314 let Inst{31-22} = 0b0010101011; 315 let Inst{21-10} = imm12; 316 let Inst{9-5} = rj; 317 let Inst{4-0} = imm5; 318} 319 320// FmtPRELDX 321// < 0b00111000001011000 | rk | rj | I5> 322class FmtPRELDX<dag outs, dag ins, string opnstr, list<dag> pattern = []> 323 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 324 bits<5> rk; 325 bits<5> rj; 326 bits<5> imm5; 327 328 let Inst{31-15} = 0b00111000001011000; 329 let Inst{14-10} = rk; 330 let Inst{9-5} = rj; 331 let Inst{4-0} = imm5; 332} 333 334// FmtCSR 335// <opcode | csr_num | rd> 336class FmtCSR<bits<32> op, dag outs, dag ins, string opnstr, 337 list<dag> pattern = []> 338 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 339 bits<14> csr_num; 340 bits<5> rd; 341 342 let Inst{31-0} = op; 343 let Inst{23-10} = csr_num; 344 let Inst{4-0} = rd; 345} 346 347// FmtCSRXCHG 348// <opcode | csr_num | rj | rd> 349class FmtCSRXCHG<bits<32> op, dag outs, dag ins, string opnstr, 350 list<dag> pattern = []> 351 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 352 bits<14> csr_num; 353 bits<5> rj; 354 bits<5> rd; 355 356 let Inst{31-0} = op; 357 let Inst{23-10} = csr_num; 358 let Inst{9-5} = rj; 359 let Inst{4-0} = rd; 360} 361 362// FmtCACOP 363// <0b0000011000 | I12 | rj | I5> 364class FmtCACOP<dag outs, dag ins, string opnstr, list<dag> pattern = []> 365 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 366 bits<12> imm12; 367 bits<5> rj; 368 bits<5> op; 369 370 let Inst{31-22} = 0b0000011000; 371 let Inst{21-10} = imm12; 372 let Inst{9-5} = rj; 373 let Inst{4-0} = op; 374} 375 376// FmtIMM32 377// <I32> 378class FmtI32<bits<32> op, list<dag> pattern = []> 379 : LAInst<(outs), (ins), deriveInsnMnemonic<NAME>.ret, "", pattern> { 380 let Inst{31-0} = op; 381} 382 383// FmtINVTLB 384// <0b00000110010010011 | rk | rj | I5> 385class FmtINVTLB<dag outs, dag ins, string opnstr, list<dag> pattern = []> 386 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 387 bits<5> rk; 388 bits<5> rj; 389 bits<5> op; 390 391 let Inst{31-15} = 0b00000110010010011; 392 let Inst{14-10} = rk; 393 let Inst{9-5} = rj; 394 let Inst{4-0} = op; 395} 396 397// FmtLDPTE 398// <0b00000110010001 | seq | rj | 00000> 399class FmtLDPTE<dag outs, dag ins, string opnstr, list<dag> pattern = []> 400 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> { 401 bits<8> seq; 402 bits<5> rj; 403 404 let Inst{31-18} = 0b00000110010001; 405 let Inst{17-10} = seq; 406 let Inst{9-5} = rj; 407 let Inst{4-0} = 0b00000; 408} 409