1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief The AMDGPU TargetMachine interface definition for hw codgen targets. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H 16 #define LLVM_LIB_TARGET_R600_AMDGPUTARGETMACHINE_H 17 18 #include "AMDGPUFrameLowering.h" 19 #include "AMDGPUInstrInfo.h" 20 #include "AMDGPUIntrinsicInfo.h" 21 #include "AMDGPUSubtarget.h" 22 #include "R600ISelLowering.h" 23 #include "llvm/IR/DataLayout.h" 24 25 namespace llvm { 26 27 //===----------------------------------------------------------------------===// 28 // AMDGPU Target Machine (R600+) 29 //===----------------------------------------------------------------------===// 30 31 class AMDGPUTargetMachine : public LLVMTargetMachine { 32 protected: 33 TargetLoweringObjectFile *TLOF; 34 AMDGPUSubtarget Subtarget; 35 AMDGPUIntrinsicInfo IntrinsicInfo; 36 37 public: 38 AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS, 39 StringRef CPU, TargetOptions Options, Reloc::Model RM, 40 CodeModel::Model CM, CodeGenOpt::Level OL); 41 ~AMDGPUTargetMachine(); getSubtargetImpl()42 const AMDGPUSubtarget *getSubtargetImpl() const override { 43 return &Subtarget; 44 } getIntrinsicInfo()45 const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override { 46 return &IntrinsicInfo; 47 } 48 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 49 50 /// \brief Register R600 analysis passes with a pass manager. 51 void addAnalysisPasses(PassManagerBase &PM) override; getObjFileLowering()52 TargetLoweringObjectFile *getObjFileLowering() const override { 53 return TLOF; 54 } 55 }; 56 57 //===----------------------------------------------------------------------===// 58 // GCN Target Machine (SI+) 59 //===----------------------------------------------------------------------===// 60 61 class GCNTargetMachine : public AMDGPUTargetMachine { 62 63 public: 64 GCNTargetMachine(const Target &T, StringRef TT, StringRef FS, 65 StringRef CPU, TargetOptions Options, Reloc::Model RM, 66 CodeModel::Model CM, CodeGenOpt::Level OL); 67 }; 68 69 } // End namespace llvm 70 71 #endif 72