1 //===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file 10 /// The AMDGPU TargetMachine interface definition for hw codegen targets. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 15 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 16 17 #include "GCNSubtarget.h" 18 #include "llvm/CodeGen/CodeGenTargetMachineImpl.h" 19 #include "llvm/CodeGen/TargetPassConfig.h" 20 #include "llvm/MC/MCStreamer.h" 21 #include "llvm/Passes/CodeGenPassBuilder.h" 22 #include <optional> 23 #include <utility> 24 25 namespace llvm { 26 27 //===----------------------------------------------------------------------===// 28 // AMDGPU Target Machine (R600+) 29 //===----------------------------------------------------------------------===// 30 31 class AMDGPUTargetMachine : public CodeGenTargetMachineImpl { 32 protected: 33 std::unique_ptr<TargetLoweringObjectFile> TLOF; 34 35 StringRef getGPUName(const Function &F) const; 36 StringRef getFeatureString(const Function &F) const; 37 38 public: 39 static bool EnableFunctionCalls; 40 static bool EnableLowerModuleLDS; 41 42 AMDGPUTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 43 StringRef FS, const TargetOptions &Options, 44 std::optional<Reloc::Model> RM, 45 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL); 46 ~AMDGPUTargetMachine() override; 47 48 const TargetSubtargetInfo *getSubtargetImpl() const; 49 const TargetSubtargetInfo * 50 getSubtargetImpl(const Function &) const override = 0; 51 52 TargetLoweringObjectFile *getObjFileLowering() const override { 53 return TLOF.get(); 54 } 55 56 void registerPassBuilderCallbacks(PassBuilder &PB) override; 57 void registerDefaultAliasAnalyses(AAManager &) override; 58 59 /// Get the integer value of a null pointer in the given address space. 60 static int64_t getNullPointerValue(unsigned AddrSpace); 61 62 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 63 64 unsigned getAssumedAddrSpace(const Value *V) const override; 65 66 std::pair<const Value *, unsigned> 67 getPredicatedAddrSpace(const Value *V) const override; 68 69 unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override; 70 71 bool splitModule(Module &M, unsigned NumParts, 72 function_ref<void(std::unique_ptr<Module> MPart)> 73 ModuleCallback) override; 74 }; 75 76 //===----------------------------------------------------------------------===// 77 // GCN Target Machine (SI+) 78 //===----------------------------------------------------------------------===// 79 80 class GCNTargetMachine final : public AMDGPUTargetMachine { 81 private: 82 mutable StringMap<std::unique_ptr<GCNSubtarget>> SubtargetMap; 83 84 public: 85 GCNTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 86 StringRef FS, const TargetOptions &Options, 87 std::optional<Reloc::Model> RM, 88 std::optional<CodeModel::Model> CM, CodeGenOptLevel OL, 89 bool JIT); 90 91 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 92 93 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override; 94 95 TargetTransformInfo getTargetTransformInfo(const Function &F) const override; 96 97 bool useIPRA() const override { return true; } 98 99 Error buildCodeGenPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out, 100 raw_pwrite_stream *DwoOut, 101 CodeGenFileType FileType, 102 const CGPassBuilderOption &Opts, 103 PassInstrumentationCallbacks *PIC) override; 104 105 void registerMachineRegisterInfoCallback(MachineFunction &MF) const override; 106 107 MachineFunctionInfo * 108 createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, 109 const TargetSubtargetInfo *STI) const override; 110 111 yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override; 112 yaml::MachineFunctionInfo * 113 convertFuncInfoToYAML(const MachineFunction &MF) const override; 114 bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, 115 PerFunctionMIParsingState &PFS, 116 SMDiagnostic &Error, 117 SMRange &SourceRange) const override; 118 }; 119 120 //===----------------------------------------------------------------------===// 121 // AMDGPU Pass Setup - For Legacy Pass Manager. 122 //===----------------------------------------------------------------------===// 123 124 class AMDGPUPassConfig : public TargetPassConfig { 125 public: 126 AMDGPUPassConfig(TargetMachine &TM, PassManagerBase &PM); 127 128 AMDGPUTargetMachine &getAMDGPUTargetMachine() const { 129 return getTM<AMDGPUTargetMachine>(); 130 } 131 132 ScheduleDAGInstrs * 133 createMachineScheduler(MachineSchedContext *C) const override; 134 135 void addEarlyCSEOrGVNPass(); 136 void addStraightLineScalarOptimizationPasses(); 137 void addIRPasses() override; 138 void addCodeGenPrepare() override; 139 bool addPreISel() override; 140 bool addInstSelector() override; 141 bool addGCPasses() override; 142 143 std::unique_ptr<CSEConfigBase> getCSEConfig() const override; 144 145 /// Check if a pass is enabled given \p Opt option. The option always 146 /// overrides defaults if explicitly used. Otherwise its default will 147 /// be used given that a pass shall work at an optimization \p Level 148 /// minimum. 149 bool isPassEnabled(const cl::opt<bool> &Opt, 150 CodeGenOptLevel Level = CodeGenOptLevel::Default) const { 151 if (Opt.getNumOccurrences()) 152 return Opt; 153 if (TM->getOptLevel() < Level) 154 return false; 155 return Opt; 156 } 157 }; 158 159 //===----------------------------------------------------------------------===// 160 // AMDGPU CodeGen Pass Builder interface. 161 //===----------------------------------------------------------------------===// 162 163 class AMDGPUCodeGenPassBuilder 164 : public CodeGenPassBuilder<AMDGPUCodeGenPassBuilder, GCNTargetMachine> { 165 using Base = CodeGenPassBuilder<AMDGPUCodeGenPassBuilder, GCNTargetMachine>; 166 167 public: 168 AMDGPUCodeGenPassBuilder(GCNTargetMachine &TM, 169 const CGPassBuilderOption &Opts, 170 PassInstrumentationCallbacks *PIC); 171 172 void addIRPasses(AddIRPass &) const; 173 void addCodeGenPrepare(AddIRPass &) const; 174 void addPreISel(AddIRPass &addPass) const; 175 void addILPOpts(AddMachinePass &) const; 176 void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const; 177 Error addInstSelector(AddMachinePass &) const; 178 void addMachineSSAOptimization(AddMachinePass &) const; 179 void addPostRegAlloc(AddMachinePass &) const; 180 181 /// Check if a pass is enabled given \p Opt option. The option always 182 /// overrides defaults if explicitly used. Otherwise its default will be used 183 /// given that a pass shall work at an optimization \p Level minimum. 184 bool isPassEnabled(const cl::opt<bool> &Opt, 185 CodeGenOptLevel Level = CodeGenOptLevel::Default) const; 186 void addEarlyCSEOrGVNPass(AddIRPass &) const; 187 void addStraightLineScalarOptimizationPasses(AddIRPass &) const; 188 }; 189 190 } // end namespace llvm 191 192 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H 193