1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU. 10 /// \todo This should be generated by TableGen. 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H 15 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/CodeGen/MachineBasicBlock.h" 18 #include "llvm/CodeGen/Register.h" 19 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 20 21 #define GET_REGBANK_DECLARATIONS 22 #include "AMDGPUGenRegisterBank.inc" 23 24 namespace llvm { 25 26 class LLT; 27 class GCNSubtarget; 28 class MachineIRBuilder; 29 class SIInstrInfo; 30 class SIRegisterInfo; 31 class TargetRegisterInfo; 32 33 /// This class provides the information for the target register banks. 34 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo { 35 36 protected: 37 38 #define GET_TARGET_REGBANK_CLASS 39 #include "AMDGPUGenRegisterBank.inc" 40 }; 41 42 class AMDGPURegisterBankInfo final : public AMDGPUGenRegisterBankInfo { 43 public: 44 const GCNSubtarget &Subtarget; 45 const SIRegisterInfo *TRI; 46 const SIInstrInfo *TII; 47 48 bool buildVCopy(MachineIRBuilder &B, Register DstReg, Register SrcReg) const; 49 50 bool collectWaterfallOperands( 51 SmallSet<Register, 4> &SGPROperandRegs, 52 MachineInstr &MI, 53 MachineRegisterInfo &MRI, 54 ArrayRef<unsigned> OpIndices) const; 55 56 bool executeInWaterfallLoop( 57 MachineIRBuilder &B, 58 iterator_range<MachineBasicBlock::iterator> Range, 59 SmallSet<Register, 4> &SGPROperandRegs, 60 MachineRegisterInfo &MRI) const; 61 62 bool executeInWaterfallLoop(MachineIRBuilder &B, 63 MachineInstr &MI, 64 MachineRegisterInfo &MRI, 65 ArrayRef<unsigned> OpIndices) const; 66 bool executeInWaterfallLoop(MachineInstr &MI, 67 MachineRegisterInfo &MRI, 68 ArrayRef<unsigned> OpIndices) const; 69 70 void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI, 71 unsigned OpIdx) const; 72 bool applyMappingDynStackAlloc(MachineInstr &MI, 73 const OperandsMapper &OpdMapper, 74 MachineRegisterInfo &MRI) const; 75 bool applyMappingLoad(MachineInstr &MI, 76 const OperandsMapper &OpdMapper, 77 MachineRegisterInfo &MRI) const; 78 bool 79 applyMappingImage(MachineInstr &MI, 80 const OperandsMapper &OpdMapper, 81 MachineRegisterInfo &MRI, int RSrcIdx) const; 82 bool applyMappingSBufferLoad(const OperandsMapper &OpdMapper) const; 83 84 bool applyMappingBFEIntrinsic(const OperandsMapper &OpdMapper, 85 bool Signed) const; 86 87 Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI, 88 Register Reg) const; 89 90 std::pair<Register, unsigned> 91 splitBufferOffsets(MachineIRBuilder &B, Register Offset) const; 92 93 MachineInstr *selectStoreIntrinsic(MachineIRBuilder &B, 94 MachineInstr &MI) const; 95 96 /// See RegisterBankInfo::applyMapping. 97 void applyMappingImpl(const OperandsMapper &OpdMapper) const override; 98 99 const ValueMapping *getValueMappingForPtr(const MachineRegisterInfo &MRI, 100 Register Ptr) const; 101 102 const RegisterBankInfo::InstructionMapping & 103 getInstrMappingForLoad(const MachineInstr &MI) const; 104 105 unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI, 106 unsigned Default = AMDGPU::VGPRRegBankID) const; 107 108 // Return a value mapping for an operand that is required to be an SGPR. 109 const ValueMapping *getSGPROpMapping(Register Reg, 110 const MachineRegisterInfo &MRI, 111 const TargetRegisterInfo &TRI) const; 112 113 // Return a value mapping for an operand that is required to be a VGPR. 114 const ValueMapping *getVGPROpMapping(Register Reg, 115 const MachineRegisterInfo &MRI, 116 const TargetRegisterInfo &TRI) const; 117 118 // Return a value mapping for an operand that is required to be a AGPR. 119 const ValueMapping *getAGPROpMapping(Register Reg, 120 const MachineRegisterInfo &MRI, 121 const TargetRegisterInfo &TRI) const; 122 123 /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p 124 /// Regs. This appropriately sets the regbank of the new registers. 125 void split64BitValueForMapping(MachineIRBuilder &B, 126 SmallVector<Register, 2> &Regs, 127 LLT HalfTy, 128 Register Reg) const; 129 130 template <unsigned NumOps> 131 struct OpRegBankEntry { 132 int8_t RegBanks[NumOps]; 133 int16_t Cost; 134 }; 135 136 template <unsigned NumOps> 137 InstructionMappings 138 addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI, 139 const std::array<unsigned, NumOps> RegSrcOpIdx, 140 ArrayRef<OpRegBankEntry<NumOps>> Table) const; 141 142 RegisterBankInfo::InstructionMappings 143 getInstrAlternativeMappingsIntrinsic( 144 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 145 146 RegisterBankInfo::InstructionMappings 147 getInstrAlternativeMappingsIntrinsicWSideEffects( 148 const MachineInstr &MI, const MachineRegisterInfo &MRI) const; 149 150 unsigned getMappingType(const MachineRegisterInfo &MRI, 151 const MachineInstr &MI) const; 152 153 bool isSALUMapping(const MachineInstr &MI) const; 154 155 const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const; 156 const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const; 157 const InstructionMapping &getDefaultMappingAllVGPR( 158 const MachineInstr &MI) const; 159 160 const InstructionMapping &getImageMapping(const MachineRegisterInfo &MRI, 161 const MachineInstr &MI, 162 int RsrcIdx) const; 163 164 public: 165 AMDGPURegisterBankInfo(const GCNSubtarget &STI); 166 167 unsigned copyCost(const RegisterBank &A, const RegisterBank &B, 168 unsigned Size) const override; 169 170 unsigned getBreakDownCost(const ValueMapping &ValMapping, 171 const RegisterBank *CurBank = nullptr) const override; 172 173 const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC, 174 LLT) const override; 175 176 InstructionMappings 177 getInstrAlternativeMappings(const MachineInstr &MI) const override; 178 179 const InstructionMapping & 180 getInstrMapping(const MachineInstr &MI) const override; 181 182 private: 183 184 bool foldExtractEltToCmpSelect(MachineInstr &MI, 185 MachineRegisterInfo &MRI, 186 const OperandsMapper &OpdMapper) const; 187 bool foldInsertEltToCmpSelect(MachineInstr &MI, 188 MachineRegisterInfo &MRI, 189 const OperandsMapper &OpdMapper) const; 190 }; 191 } // End llvm namespace. 192 #endif 193