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/freebsd-src/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	frontend.json	41 "BriefDescription": "Cycles when a demand ifetch was pending", 71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru… 72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a… 95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano… 101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di… 102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d… 107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on … [all …]
H A D	memory.json	5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 6 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 11 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand … 12 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa… 23 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a… 24 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to … 29 …"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 f… 30 …"PublicDescription": "The processor's data cache was reloaded from a memory location including L4 … [all …]
H A D	cache.json	5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another … 11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch… 17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 35 …"BriefDescription": "The processor's data cache was reloaded from a localtion other than the local… 36 …"PublicDescription": "The processor's data cache was reloaded from a localtion other than the loca… [all …]
H A D	other.json	23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data … 24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum… 29 …"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pum… 30 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was group pu… 36 …data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was ch… 42 … ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chi… 59 …"BriefDescription": "Initial and Final Pump Scope was system pump for all data types (demand load,… 60 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was system p… 65 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope… 66 …e(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump an… [all …]
H A D	marked.json	35 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 47 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi… 59 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 71 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked … 107 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st… 119 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch co… 131 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without disp… 143 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict… 155 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked … [all …]
H A D	translation.json	29 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the lo… 53 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 59 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 65 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data… 71 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch… 77 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 83 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without confl… [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	marked.json	10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 15 …"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at… 20 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam… 35 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with disp… 45 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This i… 50 …A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This i… 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due… 65 …"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) o… 70 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … [all …]
H A D	frontend.json	5 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 15 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 25 …"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in… 40 … (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope… 50 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 55 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict… 70 …"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in th… 85 …"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from… 95 …"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch… 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … [all …]
H A D	translation.json	15 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another cor… 25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 60 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another … 70 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local … 75 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… 80 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 95 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c… 100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same… 115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t… [all …]
H A D	pipeline.json	25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued… 30 …"BriefDescription": "The processor's data cache was reloaded either shared or modified data from a… 35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ… 40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different… 95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe… 115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa… 160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro… 175 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch… [all …]
H A D	cache.json	35 …ause the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this lo… 40 …"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data… 45 …"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its … 50 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the … 55 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot… 70 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… 80 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the … 90 …ription": "Finish stall because the NTF instruction was a load that hit on an older store and it w… 100 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an… 105 … "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
/freebsd-src/contrib/bc/
H A D	NEWS.md	8 This bug was caused by the macOS fix in `7.0.0`. Unfortunately, this means that 23 The second bug is that an array, which should only be a function parameter, was 26 The third bug is that value stack for `dc` was cleared on any error. However, 28 implementations, this behavior was changed. This change is why this version is a 35 The bug was that `bc` attempted to jump out when flushing `stdout` on exit, but 87 The second bug was to remove printing a leading zero in scientific or 90 The change was that the implementation of `irand()` was improved to call the 104 The bug was that multiple read calls could repeat old data. 150 better error checking in tests to help packagers. Unfortunately, I was to [all...]
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_z14/
H A D	extended.json	6 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 12 …een written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data ca… 24 …entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a … 30 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB" 36 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 42 …een written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruc… 54 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 60 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level… 96 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 102 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chi… [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A D	extended.json	6 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 36 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 54 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 96 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 102 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 108 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 114 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 120 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 126 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… 132 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On-… [all …]
/freebsd-src/lib/libsys/
H A D	intro.2	327 chosen from the address family in which the socket was created. 380 An attempt was made to perform an operation limited to processes 385 pathname was an empty string. 414 A request was made to execute a file 419 A file descriptor argument was out of range, referred to no open file, 422 request was made to a file that was only open for writing 427 function was executed by a process that had no existing or unwaited-for 430 An attempt was made to lock a system resource that 433 The new process image required more memory than was allowed by the hardware 439 An attempt was made to access a file in a way forbidden [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/
H A D	other.json	9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol… 12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old… 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… 33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the … 36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o… [all …]
/freebsd-src/share/man/man4/
H A D	hwpmc.4	232 seen by the target process when it was scheduled on the CPU. 265 operation was attempted on a process-private PMC that does not have 431 driver was compiled with 512 The module loading process failed because a version mismatch was detected 519 A negative value was supplied for tunable 522 A negative value was supplied for tunable 525 A negative value was supplied for tunable 664 operation was requested while an existing log was active. 666 A DISABLE operation was requested using the 673 operation was requested on an active system mode PMC. [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a65/
H A D	ifu.json	45 …"PublicDescription": "A 2nd instruction could have been pushed but was not because it was nonseque… 48 …"BriefDescription": "A 2nd instruction could have been pushed but was not because it was nonsequen… 75 …"PublicDescription": "This thread was arbitrated when the other thread was also ready for scheduli… 78 …"BriefDescription": "This thread was arbitrated when the other thread was also ready for schedulin… 81 …"PublicDescription": "This thread was arbitrated when the other thread was also active, but not ne… 84 …"BriefDescription": "This thread was arbitrated when the other thread was also active, but not nec… 87 …"PublicDescription": "This thread was not arbitrated because it was not ready for scheduling. For … 90 …"BriefDescription": "This thread was not arbitrated because it was not ready for scheduling. For e…
/freebsd-src/contrib/llvm-project/clang/include/clang/AST/
H A D	ASTMutationListener.h	52 /// A new TagDecl definition was completed. 58 /// An implicit member was added after the definition was completed. 61 /// A template specialization (or partial one) was added to the in AddedCXXTemplateSpecialization() 66 /// A template specialization (or partial one) was added to the 72 /// A template specialization (or partial one) was added to the in AddedCXXTemplateSpecialization() 92 /// The instantiation of a templated function or variable was 97 /// A templated variable's definition was implicitly instantiated. 100 /// A function template's definition was instantiated. 103 /// A default argument was instantiate in DefaultArgumentInstantiated() [all...]
/freebsd-src/sys/contrib/libsodium/
H A D	ChangeLog	18 - `sodium_stackzero()` was added to wipe content off the stack. 32 - The aes128ctr primitive was removed. It was slow, non-standard, not 36 - The secretstream construction was slightly changed to be consistent 42 major was bumped up. 78 - A new `crypto_secretstream_()` API was added to safely encrypt files 84 - The `crypto_pwhash_str_needs_rehash()` function was added to check if 94 - The public `crypto_pwhash_argon2i_MEMLIMIT_MAX` constant was 99 - armv7s-optimized code was re-added to iOS builds. 100 - An AVX2 optimized implementation of the Argon2 round function was 108 - A `crypto_box_curve25519xchacha20poly1305_seal()` function set was [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A D	extended.json	18 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 24 …e to the Level-1 Instruction cache directory where the returned cache line was sourced from the Le… 30 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from the Le… 42 …A directory write to the Level-1 Data cache where the installed cache line was sourced from memory… 48 …tory write to the Level-1 Instruction cache where the installed cache line was sourced from memory… 54 …"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a … 90 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On … 96 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an Off… 102 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an Off… 108 …ry write to the Level-1 Data cache directory where the returned cache line was sourced from an On … [all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	cache.json	21 …ritebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", 221 …f retired loads that hit in the L3 cache, in which a snoop was required and modified data was forw… 389 …ads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 400 … reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 411 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … 422 …": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop … 433 …: "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy t… 466 …hes that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data wa… 477 …etches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was f… 488 …s that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data … [all …]
/freebsd-src/share/man/man9/
H A D	vfs_getopt.9	175 function returns 0 if the option was found; otherwise, 184 If the option was found, but is not 193 If the option was not found, 201 function returns 1 if the option was found, and 0 if it was not. 205 function returns 0 if the option was not found, or was not 219 functions return 0 if the copy was successful, 221 if the option was found but the lengths did not match, and 223 if the option was not found. 233 function returns 0 if the copy was successful, 235 if the option was found but the string was too long, and [all …]
/freebsd-src/crypto/openssl/test/recipes/15-test_mp_rsa_data/
H A D	plain_text	`1 It was the best of times, it was the worst of times, 2 it was the age of wisdom, it was the age of foolishness, 3 it was the epoch of belief, it was the epoch of incredulity, 4 it was the season of Light, it was the season of Darkness.`
/freebsd-src/contrib/llvm-project/clang/include/clang/Basic/
H A D	DiagnosticSerializationKinds.td	22 "%select{precompiled header\|module file\|AST file}1 '%2' was built" 23 ": %select{size\|mtime\|content}3 changed%select{\| (was %5, now %6)}4">, 33 "PCH file was compiled for the %0 '%1' but the current translation " 36 "%select{AST file was\|current translation unit is}0 compiled with the target " 37 "feature '%1' but the %select{current translation unit is\|AST file was}0 " 39 def err_pch_langopt_mismatch : Error<"%0 was %select{disabled\|enabled}1 in " 43 def err_pch_diagopt_mismatch : Error<"%0 is currently enabled, but was not in " 45 def err_pch_modulecache_mismatch : Error<"PCH was compiled with module cache " 48 "PCH was compiled with different VFS overlay files than are currently in use">, 74 "AST file '%0' was no [all...]

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