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/freebsd-src/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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H A Dmarvell,xenon-sdhci.txt11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
18 - clocks:
23 - clock-names:
28 - reg:
29 * For "marvell,armada-3700-sdhci", two register areas.
[all …]
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
29 - items:
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H A Dsdhci-am654.txt7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
11 - compatible: should be one of:
12 "ti,am654-sdhci-5.1": SDHCI on AM654 device.
13 "ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device.
14 "ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device.
15 - reg: Must be two entries.
16 - The first should be the sdhci register space
17 - The second should the subsystem/phy register space
18 - clocks: Handles to the clock inputs.
[all …]
H A Darasan,sdhci.txt7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
18 - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
[all …]
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dqcom-soc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/qcom-soc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
15 qcom,SoC-IP
18 qcom,sdm845-llcc-bwmon
26 pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
28 - compatible
34 - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10_socdk_sdmmc.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
6 /dts-v1/;
11 cap-sd-highspeed;
12 cap-mmc-highspeed;
13 broken-cd;
14 bus-width = <4>;
15 clk-phase-sd-hs = <0>, <135>;
19 sdmmca-ecc@ff8c2c00 {
20 compatible = "altr,socfpga-sdmmc-ecc";
[all …]
H A Dsocfpga_arria5.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_cyclone5.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
16 clock-frequency = <25000000>;
22 broken-cd;
23 bus-width = <4>;
24 cap-mmc-highspeed;
25 cap-sd-highspeed;
26 clk-phase-sd-hs = <0>, <135>;
30 cpu1-start-addr = <0xffd080c4>;
H A Dsocfpga_cyclone5_mcv.dtsi1 // SPDX-License-Identifier: GPL-2.0+
10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
19 &mmc0 { /* On-SoM eMMC */
20 bus-width = <8>;
21 clk-phase-sd-hs = <0>, <135>;
H A Dsocfpga_arria10_mercury_aa1.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
25 stdout-path = "serial1:115200n8";
30 phy-mode = "rgmii";
31 phy-addr = <0xffffffff>; /* probe for phy addr */
33 max-frame-size = <3800>;
35 phy-handle = <&phy3>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 compatible = "snps,dwmac-mdio";
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/freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6dl-dhcom-picoitx.dts1 // SPDX-License-Identifier: GPL-2.0+
6 * DHCM-iMX6DL-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
7 * DHCOM PCB number: 493-300 or newer
8 * PicoITX PCB number: 487-600 or newer
10 /dts-v1/;
13 #include "imx6qdl-dhcom-som.dtsi"
14 #include "imx6qdl-dhcom-picoitx.dtsi"
18 compatible = "dh,imx6dl-dhcom-picoitx", "dh,imx6dl-dhcom-som",
H A Dimx6q-dhcom-pdk2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2021 DH electronics GmbH
7 * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2
8 * DHCOM PCB number: 493-300 or newer
9 * PDK2 PCB number: 516-400 or newer
11 /dts-v1/;
14 #include "imx6qdl-dhcom-som.dtsi"
15 #include "imx6qdl-dhcom-pdk2.dtsi"
19 compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som",
/freebsd-src/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/freebsd-src/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_n5x_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,n5x-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
29 sdram_edac: memory-controller@f87f8000 {
30 compatible = "snps,ddrc-3.80a";
38 compatible = "intel,easic-n5x-clkmg
[all...]
H A Dsocfpga_agilex_socdk.dts1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
19 stdout-path = "serial0:115200n8";
23 compatible = "gpio-leds";
53 phy-mode = "rgmii";
54 phy-handl
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc7280-idp.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
9 #include <dt-bindings/input/linux-event-code
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA510.td1 //==- AArch64SchedCortexA510.td - ARM Cortex-A510 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
[all...]
/freebsd-src/contrib/wpa/src/ap/
H A Dgas_serv.c3 * Copyright (c) 2011-2014, Qualcomm Atheros, Inc.
67 sta->flags |= WLAN_STA_GAS; in gas_dialog_create()
74 hapd->conf->gas_comeback_delay / 1024 + in gas_dialog_create()
80 if (sta->gas_dialog == NULL) { in gas_dialog_create()
81 sta->gas_dialog = os_calloc(GAS_DIALOG_MAX, in gas_dialog_create()
83 if (sta->gas_dialog == NULL) in gas_dialog_create()
87 for (i = sta->gas_dialog_next, j = 0; j < GAS_DIALOG_MAX; i++, j++) { in gas_dialog_create()
90 if (sta->gas_dialog[i].valid) in gas_dialog_create()
92 dia = &sta->gas_dialo in gas_dialog_create()
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8960.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-binding
[all...]
/freebsd-src/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10_socdk.dts1 // SPDX-License-Identifier: GPL-2.0-only
10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
25 led-hps
[all...]
/freebsd-src/contrib/llvm-project/llvm/lib/ExecutionEngine/Orc/
H A DMachOPlatform.cpp1 //===------ MachOPlatform.cpp - Utilities for executing MachO in Orc ---
1447 __anon2c142cbb1502(SecDesc &SD, jitlink::Section &GraphSec) populateObjCRuntimeObject() argument
1461 auto &SD = DataSections.back(); populateObjCRuntimeObject() local
1576 for (auto &SD : Secs) { populateObjCRuntimeObject() local
1738 for (auto &HS : AdditionalHeaderSymbols) addMachOHeader() local
1761 for (auto &HS : AdditionalHeaderSymbols) createHeaderInterface() local
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/freebsd-src/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhi3670-hikey970.dts1 // SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
14 #include "hikey970-pinctrl.dtsi"
15 #include "hikey970-pmic.dtsi"
19 compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
34 stdout-path = "serial6:115200n8";
43 wlan_en: wlan-en-1-8v {
44 compatible = "regulator-fixed";
45 regulator-name = "wlan-en-regulator";
[all …]

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