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/freebsd-src/sys/contrib/device-tree/Bindings/display/bridge/
H A Dfsl,imx8qxp-pixel-link.yaml4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
14 asynchronous linkage between pixel sources(display controller or
15 camera module) and pixel consumers(imaging or displays).
16 It consists of two distinct functions, a pixel transfer function and a
17 control interface. Multiple pixel channels can exist per one control channel.
18 This binding documentation is only for pixel links whose pixel sources are
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
27 - fsl,imx8qm-dc-pixel-link
[all …]
H A Dfsl,imx8qxp-pixel-combiner.yaml4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml#
7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
15 of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured as
16 either one screen, two screens, or virtual screens. The pixel combiner is
17 also responsible for generating some of the control signals for the pixel link
23 - fsl,imx8qm-pixel-combiner
24 - fsl,imx8qxp-pixel-combiner
47 description: Represents a display stream of pixel combiner.
92 pixel-combiner@56020000 {
[all …]
H A Dfsl,imx8qxp-pxl2dpi.yaml7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
14 interfaces the pixel link 36-bit data output and the DSI controller’s
16 used in LVDS mode, to remap the pixel color codings between those modules.
46 description: The PXL2DPI input port node from pixel link.
H A Dfsl,imx8qxp-ldb.yaml33 A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in
34 the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
52 - description: pixel clock
57 - const: pixel
139 clock-names = "pixel", "bypass";
/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Dgoogle.yaml13 ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
16 Currently upstream this is devices using "gs101" SoC which is found in Pixel
17 6, Pixel 6 Pro and Pixel 6a.
26 - Marketing name ("Pixel 6")
37 - description: Google Pixel 6 / Oriole
/freebsd-src/sys/contrib/device-tree/Bindings/media/
H A Dcdns,csi2rx.yaml14 lanes in input, and 4 different pixel streams in output.
31 - description: pixel Clock for Stream interface 0
32 - description: pixel Clock for Stream interface 1
33 - description: pixel Clock for Stream interface 2
34 - description: pixel Clock for Stream interface 3
49 - description: pixel reset for Stream interface 0
50 - description: pixel reset for Stream interface 1
51 - description: pixel reset for Stream interface 2
52 - description: pixel reset for Stream interface 3
H A Dfsl-pxp.txt1 Freescale Pixel Pipeline
4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
6 pixel conversion via lookup table. Different versions are present on various
H A Dfsl,imx6ull-pxp.yaml8 title: Freescale Pixel Pipeline
15 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
17 pixel conversion via lookup table. Different versions are present on various
/freebsd-src/sys/contrib/device-tree/Bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
29 pixel link MSI bus controller and does not allow SCFW user to control it.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
52 - fsl,imx8qxp-display-pixel-link-msi-bus
53 - fsl,imx8qm-display-pixel-link-msi-bus
94 compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/display/msm/
H A Ddsi-controller-main.yaml68 - pixel:: Display pixel clock.
109 Parents of "byte" and "pixel" for the given platform.
117 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
241 - const: pixel
260 - const: pixel
280 - const: pixel
300 - const: pixel
321 - const: pixel
340 - const: pixel
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/display/
H A Dbrcm,bcm-vc4.txt10 Required properties for Pixel Valve:
31 b) pixel: The pixel clock.
45 b) pixel: The pixel clock that feeds the pixelvalve
72 c) pixel: The DSI pixel clock from CPRMAN
107 clock-names = "pixel", "hdmi";
115 clock-names = "core", "pixel";
137 clock-names = "phy", "escape", "pixel";
H A Dbrcm,bcm2835-dpi.yaml22 - description: The pixel clock that feeds the pixelvalve
27 - const: pixel
52 clock-names = "core", "pixel";
H A Dcirrus,clps711x-fb.txt11 - bits-per-pixel: Bits per pixel.
30 bits-per-pixel = <4>;
H A Dbrcm,bcm2835-dsi0.yaml32 - description: The DSI pixel clock
38 - const: pixel
79 clock-names = "phy", "escape", "pixel";
H A Dbrcm,bcm2835-hdmi.yaml26 - description: The pixel clock
31 - const: pixel
80 clock-names = "pixel", "hdmi";
/freebsd-src/sys/contrib/device-tree/Bindings/display/armada/
H A Dmarvell,dove-lcd.txt13 "axiclk" - axi bus clock for pixel clock
14 "plldivider" - pll divider clock for pixel clock
15 "ext_ref_clk0" - external clock 0 for pixel clock
16 "ext_ref_clk1" - external clock 1 for pixel clock
/freebsd-src/sys/contrib/device-tree/Bindings/media/i2c/
H A Daptina,mt9p031.yaml13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
60 pixel-clock-frequency:
63 description: Target pixel clock frequency
70 - pixel-clock-frequency
103 pixel-clock-frequency = <96000000>;
H A Dmt9p031.txt3 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with
14 - pixel-clock-frequency: Pixel clock frequency.
35 pixel-clock-frequency = <96000000>;
/freebsd-src/stand/efi/include/
H A Defiuga.h34 @param ColorDepth Current video color depth in bits per pixel
59 @param ColorDepth Current video color depth in bits per pixel
85 EFI_UGA_PIXEL Pixel; member
102 <B>EfiUgaVideoFill</B> - Write data from the BltBuffer pixel (SourceX, SourceY)
103 directly to every pixel of the video display rectangle
105 Only one pixel will be used from the BltBuffer. Delta is NOT used.
/freebsd-src/contrib/spleen/
H A DChangeLog100 - Shift vertical line and double vertical line characters one pixel
145 - Remove strain pixel on the '5' digit (5x8 version)
172 - Shift the middle bar of the digit '3' one pixel up, for better
178 - Make the slash inside the digit '0' one pixel thiner (32x64 version)
228 - Remove strain pixel on the '3' and 'k' characters (32x64 version)
237 - Shift the middle bar of the upper case 'G' one pixel down (12x24 version)
266 - Remove extra pixel from the '@' character (12x24 version)
297 percent sign, asterisk, plus, minus, and equal signs one pixel up, for
299 - Shift asterisk character up by one pixel, to align it with minus and plus
/freebsd-src/stand/lua/
H A Dgfx.lua.834 Fill in a rectangle with the pixel
59 and fill with pixel
64 Sets the pixel at
83 and fill with pixel
/freebsd-src/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dpi.yaml15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
47 - description: Pixel Clock
53 - const: pixel
106 clock-names = "pixel", "engine", "pll";
H A Dmediatek,dpi.txt5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
15 - clock-names: must contain "pixel", "engine", and "pll"
32 clock-names = "pixel", "engine", "pll";
/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dfsl,plldig.yaml7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
15 which generate and offers pixel clocks to Display.
49 # Display PIXEL Clock node:
/freebsd-src/sys/contrib/device-tree/Bindings/display/imx/
H A Dfsl,imx-fb.txt14 - bits-per-pixel: Bits per pixel
41 bits-per-pixel = <16>;

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