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/llvm-project/llvm/test/CodeGen/Mips/
H A Dra-allocatable.ll101 %0 = load i32, ptr @a0, align 4
102 %1 = load ptr, ptr @b0, align 4
104 %2 = load i32, ptr @a1, align 4
105 %3 = load ptr, ptr @b1, align 4
107 %4 = load i32, ptr @a2, align 4
108 %5 = load ptr, ptr @b2, align 4
110 %6 = load i32, ptr @a3, align 4
111 %7 = load ptr, ptr @b3, align 4
113 %8 = load i32, ptr @a4, align 4
114 %9 = load pt
[all...]
/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dhrc-stack-coloring.ll66 %v34 = load ptr, ptr %v1, align 4
67 %v37 = load i64, ptr %v34, align 8
69 %v39 = load double, ptr %v32, align 8
72 %v41 = load ptr, ptr %v1, align 4
74 %v44 = load i64, ptr %v42, align 8
76 %v46 = load double, ptr %v32, align 8
79 %v48 = load ptr, ptr %v1, align 4
82 %v51 = load i64, ptr %v50, align 8
84 %v53 = load double, ptr %v32, align 8
87 %v55 = load pt
[all...]
/llvm-project/polly/test/ScopInfo/
H A Dmultiple-types-non-power-of-two.ll74 %load.i1.offset = mul i64 %i.0, 1
75 %load.i1.ptr = getelementptr inbounds i8, ptr %A, i64 %load.i1.offset
76 %load.i1.val = load i1, ptr %load.i1.ptr
77 %load.i1.val.trunc = zext i1 %load.i1.val to i8
79 %load.i16.offset = mul i64 %i.0, 2
80 %load.i16.ptr = getelementptr inbounds i8, ptr %A, i64 %load.i16.offset
81 %load.i16.val = load i16, ptr %load.i16.ptr
82 %load.i16.val.trunc = trunc i16 %load.i16.val to i8
84 %load.i24.offset = mul i64 %i.0, 4
85 %load.i24.ptr = getelementptr inbounds i8, ptr %A, i64 %load.i24.offset
[all …]
/llvm-project/lld/test/wasm/Inputs/
H A Dmany-funcs.ll8 %0 = load i32, ptr @foo, align 4
14 %0 = load i32, ptr @foo, align 4
20 %0 = load i32, ptr @foo, align 4
26 %0 = load i32, ptr @foo, align 4
32 %0 = load i32, ptr @foo, align 4
38 %0 = load i32, ptr @foo, align 4
44 %0 = load i32, ptr @foo, align 4
50 %0 = load i32, ptr @foo, align 4
56 %0 = load i32, ptr @foo, align 4
62 %0 = load i32, ptr @foo, align 4
[all …]
/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
H A Dbuild-vector-float-type.ll13 %v1 = load i32, ptr %a0, align 4
15 %v3 = load float, ptr %v2, align 4
18 %v6 = load i32, ptr %v5, align 4
20 %v8 = load float, ptr %v7, align 4
23 %v11 = load i32, ptr %v10, align 4
25 %v13 = load float, ptr %v12, align 4
28 %v16 = load i32, ptr %v15, align 4
30 %v18 = load float, ptr %v17, align 4
33 %v21 = load i32, ptr %v20, align 4
35 %v23 = load floa
[all...]
/llvm-project/clang/test/CodeGenCXX/
H A Dlvalue-bitcasts.cpp8 // CHECK: load ptr, ptr in reinterpret_cast_test()
9 // CHECK: load i32, ptr in reinterpret_cast_test()
11 // CHECK: load in reinterpret_cast_test()
12 // CHECK: load i32, ptr in reinterpret_cast_test()
14 // CHECK: load ptr in reinterpret_cast_test()
15 // CHECK: load float, ptr in reinterpret_cast_test()
17 // CHECK: load in reinterpret_cast_test()
18 // CHECK: load float, ptr in reinterpret_cast_test()
20 // CHECK: load ptr, ptr in reinterpret_cast_test()
23 // CHECK: load ptr, ptr in reinterpret_cast_test()
[all …]
H A Dvolatile-1.cpp26 // should not load in C++98 in test()
28 // CHECK11-NEXT: load volatile [[INT]], ptr @i in test()
31 // CHECK-NEXT: load volatile [[INT]], ptr @ci in test()
32 // CHECK-NEXT: load volatile [[INT]], ptr getelementptr inbounds nuw ([[CINT]], ptr @ci, i32 0, i32 1) in test()
39 // CHECK11-NEXT: load volatile [[INT]], ptr @ci in test()
40 // CHECK11-NEXT: load volatile [[INT]], ptr getelementptr inbounds nuw ([[CINT]], ptr @ci, i32 0, i32 1) in test()
45 // CHECK-NEXT: [[R:%.*]] = load volatile [[INT]], ptr @ci in test()
46 // CHECK-NEXT: [[I:%.*]] = load volatile [[INT]], ptr getelementptr inbounds nuw ([[CINT]], ptr @ci, i32 0, i32 1) in test()
51 // CHECK-NEXT: [[T:%.*]] = load volatile [[INT]], ptr @j in test()
55 // CHECK-NEXT: [[R1:%.*]] = load volatil in test()
[all...]
/llvm-project/llvm/test/Analysis/CostModel/X86/
H A Dload-broadcast.ll21 ; SSE2-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %load = load <2 x double>, …
22 … estimated cost of 1 for instruction: %bcst = shufflevector <2 x double> %load, <2 x double> poiso…
26 ; SSSE3-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %load = load <2 x double>,…
27 … estimated cost of 0 for instruction: %bcst = shufflevector <2 x double> %load, <2 x double> poiso…
31 ; SSE42-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %load = load <2 x double>,…
32 … estimated cost of 0 for instruction: %bcst = shufflevector <2 x double> %load, <2 x double> poiso…
36 ; AVX-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %load = load <2 x double>, p…
37 … estimated cost of 0 for instruction: %bcst = shufflevector <2 x double> %load, <2 x double> poiso…
40 %load = load <2 x double>, ptr %src
41 %bcst = shufflevector <2 x double> %load, <2 x double> poison, <2 x i32> zeroinitializer
[all …]
/llvm-project/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
H A Dptrmask.ll10 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr [[MASKED]], align 1
11 ; CHECK-NEXT: ret i8 [[LOAD]]
15 %load = load i8, ptr %masked
16 ret i8 %load
23 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr [[MASKED]], align 1
24 ; CHECK-NEXT: ret i8 [[LOAD]]
28 %load = load i8, ptr %masked
29 ret i8 %load
36 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, ptr [[MASKED]], align 1
37 ; CHECK-NEXT: ret i8 [[LOAD]]
[all …]
/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
H A Dmemop-folding-int-arith.ll7 ; cost. In the case that both operands are loaded, one load should get a cost
11 %li32 = load i32, ptr undef
14 %li32_0 = load i32, ptr undef
15 %li32_1 = load i32, ptr undef
18 %li64 = load i64, ptr undef
21 %li64_0 = load i64, ptr undef
22 %li64_1 = load i64, ptr undef
25 ; Truncated load
26 %li64_2 = load i64, ptr undef
31 %li16_0 = load i16, ptr undef
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dload-global-i1.ll13 %load = load i1, ptr addrspace(1) %in
14 store i1 %load, ptr addrspace(1) %out
20 %load = load <2 x i1>, ptr addrspace(1) %in
21 store <2 x i1> %load, ptr addrspace(1) %out
27 %load = load <3 x i1>, ptr addrspace(1) %in
28 store <3 x i1> %load, ptr addrspace(1) %out
34 %load
[all...]
H A Dload-local-i1.ll18 %load = load i1, ptr addrspace(3) %in
19 store i1 %load, ptr addrspace(3) %out
27 %load = load <2 x i1>, ptr addrspace(3) %in
28 store <2 x i1> %load, ptr addrspace(3) %out
36 %load = load <3 x i1>, ptr addrspace(3) %in
37 store <3 x i1> %load, ptr addrspace(3) %out
45 %load
[all...]
H A Dglobal-extload-i16.ll11 %a = load i16, ptr addrspace(1) %in
22 %a = load i16, ptr addrspace(1) %in
32 %load = load <1 x i16>, ptr addrspace(1) %in
33 %ext = zext <1 x i16> %load to <1 x i32>
42 %load = load <1 x i16>, ptr addrspace(1) %in
43 %ext = sext <1 x i16> %load to <1 x i32>
51 %load = load <2 x i16>, ptr addrspace(1) %in
52 %ext = zext <2 x i16> %load to <2 x i32>
60 %load = load <2 x i16>, ptr addrspace(1) %in
61 %ext = sext <2 x i16> %load to <2 x i32>
[all …]
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dframe-19.ll30 %v0 = load volatile <16 x i8>, ptr %ptr
31 %v1 = load volatile <16 x i8>, ptr %ptr
32 %v2 = load volatile <16 x i8>, ptr %ptr
33 %v3 = load volatile <16 x i8>, ptr %ptr
34 %v4 = load volatile <16 x i8>, ptr %ptr
35 %v5 = load volatile <16 x i8>, ptr %ptr
36 %v6 = load volatile <16 x i8>, ptr %ptr
37 %v7 = load volatile <16 x i8>, ptr %ptr
38 %v8 = load volatile <16 x i8>, ptr %ptr
39 %v9 = load volatile <16 x i8>, ptr %ptr
[all …]
H A Dframe-20.ll48 %l0 = load volatile double, ptr %ptr
49 %l1 = load volatile double, ptr %ptr
50 %l2 = load volatile double, ptr %ptr
51 %l3 = load volatile double, ptr %ptr
52 %l4 = load volatile double, ptr %ptr
53 %l5 = load volatile double, ptr %ptr
54 %l6 = load volatile double, ptr %ptr
55 %l7 = load volatile double, ptr %ptr
56 %l8 = load volatile double, ptr %ptr
57 %l9 = load volatile double, ptr %ptr
[all …]
H A Dspill-01.ll47 %val0 = load i32, ptr %ptr0
48 %val1 = load i32, ptr %ptr1
49 %val2 = load i32, ptr %ptr2
50 %val3 = load i32, ptr %ptr3
51 %val4 = load i32, ptr %ptr4
52 %val5 = load i32, ptr %ptr5
53 %val6 = load i32, ptr %ptr6
68 ; Test a case where at least one i32 load and at least one i32 store
85 %val0 = load i32, ptr %ptr0
86 %val1 = load i32, ptr %ptr1
[all …]
/llvm-project/llvm/test/Analysis/CostModel/AArch64/
H A Dsve-ldst.ll8 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.nxv8i8 = load <vscale…
9 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.nxv16i8 = load <vscal…
10 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res.nxv32i8 = load <vscal…
11 ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %res.nxv1i64 = load <vscale x 1 x i64>, pt…
12 ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %res.nxv32i1 = load <vscal…
13 ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %res.nxv16i1 = load <vscal…
14 ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %res.nxv4i1 = load <vscale x 4 x i1>, ptr …
17 %res.nxv8i8 = load <vscale x 8 x i8>, ptr undef
18 %res.nxv16i8 = load <vscale x 16 x i8>, ptr undef
19 %res.nxv32i8 = load <vscale x 32 x i8>, ptr undef
[all …]
/llvm-project/llvm/test/Transforms/GVN/
H A Dequality-assume.ll6 ; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr [[P:%.*]]
7 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[LOAD]], [[V:%.*]]
11 %load = load i32, ptr %p
12 %c = icmp eq i32 %load, %v
14 ret i32 %load
19 ; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr [[P:%.*]]
20 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[LOAD]], [[
[all...]
/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
H A Dload_atomic.ll14 %load = load atomic i8, ptr %ptr unordered, align 1
15 ret i8 %load
25 %load = load atomic i8, ptr %ptr unordered, align 1
26 %sext = sext i8 %load to i32
37 %load = load atomic i8, ptr %ptr unordered, align 1
38 %sext = sext i8 %load to i16
50 %load = load atomic i8, ptr %ptr unordered, align 1
51 %sext = sext i8 %load to i64
61 %load = load atomic i8, ptr %ptr unordered, align 1
62 %zext = zext i8 %load to i32
[all …]
/llvm-project/llvm/test/Transforms/Mem2Reg/
H A Dpreserve-nonnull-load-metadata.ll11 ; CHECK-NEXT: [[ARG_LOAD:%.*]] = load ptr, ptr [[ARG:%.*]], align 8
18 %arg.load = load ptr, ptr %arg, align 8
19 store ptr %arg.load, ptr %buf, align 8
20 %buf.load = load ptr, ptr %buf, !nonnull !0, !noundef !0
21 ret ptr %buf.load
27 ; CHECK-NEXT: [[ARG_LOAD:%.*]] = load ptr, ptr [[ARG:%.*]], align 8
32 %arg.load = load ptr, ptr %arg, align 8
33 store ptr %arg.load, ptr %buf, align 8
34 %buf.load = load ptr, ptr %buf, !nonnull !0
35 ret ptr %buf.load
[all …]
/llvm-project/clang/test/Index/
H A Dload-stmts.cpp120 // RUN: c-index-test -test-load-source all -fno-delayed-template-parsing -frtti %s | FileCheck %s
121 // CHECK: load-stmts.cpp:1:13: TypedefDecl=T:1:13 (Definition) Extent=[1:1 - 1:14]
122 // CHECK: load-stmts.cpp:2:8: StructDecl=X:2:8 (Definition) Extent=[2:1 - 2:23]
123 // CHECK: load-stmts.cpp:2:16: FieldDecl=a:2:16 (Definition) Extent=[2:12 - 2:17]
124 // CHECK: load-stmts.cpp:2:19: FieldDecl=b:2:19 (Definition) Extent=[2:12 - 2:20]
125 // CHECK: load-stmts.cpp:3:6: FunctionDecl=f:3:6 (Definition) Extent=[3:1 - 11:2]
126 // CHECK: load-stmts.cpp:3:12: ParmDecl=x:3:12 (Definition) Extent=[3:8 - 3:13]
127 // CHECK: load-stmts.cpp:4:10: VarDecl=y:4:10 (Definition) Extent=[4:8 - 4:15]
128 // CHECK: load-stmts.cpp:4:8: TypeRef=T:1:13 Extent=[4:8 - 4:9]
129 // CHECK: load-stmts.cpp:4:14: DeclRefExpr=x:3:12 Extent=[4:14 - 4:15]
[all …]
/llvm-project/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/
H A Dvectorize_i8.ll1 ; RUN: opt -mtriple=nvptx64-nvidia-cuda -passes=load-store-vectorizer -S -o - %s | FileCheck %s
10 %l0 = load i8, ptr %ptr0, align 2
11 %l1 = load i8, ptr %ptr1, align 1
12 %l2 = load i8, ptr %ptr2, align 2
21 ; CHECK-DAG: load <2 x i8>
22 ; CHECK-DAG: load i8
32 %l0 = load i8, ptr %ptr0, align 4
33 %l1 = load i8, ptr %ptr1, align 1
34 %l2 = load i8, ptr %ptr2, align 2
43 ; CHECK: load <2 x i8>
[all …]
/llvm-project/llvm/test/Transforms/LoadStoreVectorizer/X86/
H A Dsubchain-interleaved.ll1 ; RUN: opt -mtriple=x86_64-unknown-linux-gnu -passes=load-store-vectorizer -S -o - %s | FileCheck %s
2 ; RUN: opt -mtriple=x86_64-unknown-linux-gnu -aa-pipeline=basic-aa -passes='function(load-store-vec…
6 ; Vectorized subsets of the load/store chains in the presence of
10 ; CHECK: load <2 x i32>
12 ; CHECK: load <2 x i32>
17 %l1 = load i32, ptr %next.gep1, align 4
18 %l2 = load i32, ptr %ptr, align 4
21 %l3 = load i32, ptr %next.gep1, align 4
22 %l4 = load i32, ptr %next.gep2, align 4
28 ; CHECK: load <2 x i32>
[all …]
/llvm-project/llvm/test/Transforms/InstCombine/
H A Dmerge-icmp.ll10 ; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[X:%.*]], align 4
11 ; CHECK-NEXT: [[OR:%.*]] = icmp eq i16 [[LOAD]], 17791
14 %load = load i16, ptr %x, align 4
15 %trunc = trunc i16 %load to i8
17 %and = and i16 %load, -256
25 ; CHECK-NEXT: [[LOAD:%.*]] = load i16, ptr [[X:%.*]], align 4
26 ; CHECK-NEXT: [[OR:%.*]] = icmp eq i16 [[LOAD]], 1779
[all...]
/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
H A Djumbled-load.ll6 define i32 @jumbled-load(ptr noalias nocapture %in, ptr noalias nocapture %inn, ptr noalias nocaptu…
7 ; CHECK-LABEL: @jumbled-load(
8 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[IN:%.*]], align 4
9 ; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[INN:%.*]], align 4
16 %load.1 = load i32, ptr %in, align 4
18 %load.2 = load i32, ptr %gep.1, align 4
20 %load.3 = load i32, ptr %gep.2, align 4
22 %load.4 = load i32, ptr %gep.3, align 4
23 %load.5 = load i32, ptr %inn, align 4
25 %load.6 = load i32, ptr %gep.4, align 4
[all …]

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