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/freebsd-src/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dother.json9 …"PublicDescription": "This event counts every cycle that no operation was committed because the ol…
12 …"BriefDescription": "This event counts every cycle that no operation was committed because the old…
15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
[all …]
H A Dcache.json69 "PublicDescription": "This event counts outstanding L1D cache miss requests per cycle.",
72 "BriefDescription": "This event counts outstanding L1D cache miss requests per cycle."
75 "PublicDescription": "This event counts outstanding L1I cache miss requests per cycle.",
78 "BriefDescription": "This event counts outstanding L1I cache miss requests per cycle."
93 "PublicDescription": "This event counts outstanding L2 cache miss requests per cycle.",
96 "BriefDescription": "This event counts outstanding L2 cache miss requests per cycle."
123 "PublicDescription": "This event counts energy consumption per cycle of L2 cache.",
126 "BriefDescription": "This event counts energy consumption per cycle of L2 cache."
/freebsd-src/contrib/llvm-project/llvm/include/llvm/ADT/
H A DGenericCycleImpl.h30 #define DEBUG_TYPE "generic-cycle-impl"
90 assert(isReducible() && "Cycle Predecessor must be in a reducible cycle!");
122 /// \brief Helper class for computing cycle information.
164 auto Cycle = BlockMapTopLevel.find(Block);
165 if (Cycle != BlockMapTopLevel.end()) in moveTopLevelCycleToNewParent()
166 return Cycle->second; in moveTopLevelCycleToNewParent()
183 "NewParent and Child must be both top level cycle!\n"); in moveTopLevelCycleToNewParent()
203 void GenericCycleInfo<ContextT>::addBlockToCycle(BlockT *Block, CycleT *Cycle) { in addBlockToCycle()
204 // FixMe: Appending NewBlock is fine as a set of blocks in a cycle in addBlockToCycle()
188 addBlockToCycle(BlockT * Block,CycleT * Cycle) addBlockToCycle() argument
389 CycleT *Cycle = getSmallestCommonCycle(getCycle(Pred), getCycle(Succ)); splitCriticalEdge() local
442 CycleT *Cycle = getCycle(Block); getCycleDepth() local
471 for (const CycleT *Cycle : depth_first(TLC)) { validateTree() local
504 for (const CycleT *Cycle = Entry.second; Cycle; validateTree() local
520 for (const CycleT *Cycle : depth_first(TLC)) { print() local
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H A DGenericUniformityImpl.h64 /// 1. The successors of pre-entry nodes (predecessors of an cycle
65 /// entry that are outside the cycle) are replaced by the
67 /// 2. Successors of the cycle header are replaced by the exit blocks
68 /// of the cycle.
73 /// 1. Nodes after a cycle are numbered earlier than the cycle header.
74 /// 2. The header is numbered earlier than the nodes in the cycle.
75 /// 3. The numbering of the nodes within the cycle forms an interval
79 /// cycle as a DAG with the header as the sole leaf, and successors of
84 /// predecessor is the cycle heade
707 for (const auto *Cycle = CI.getCycle(&DivTermBlock); Cycle; computeJoinPoints() local
944 getExtDivCycle(const CycleT * Cycle,const BlockT * DivTermBlock,const BlockT * JoinBlock) getExtDivCycle() argument
982 getIntDivCycle(const CycleT * Cycle,const BlockT * DivTermBlock,const BlockT * JoinBlock,const DominatorTreeT & DT,ContextT & Context) getIntDivCycle() argument
1020 getOutermostDivergentCycle(const CycleT * Cycle,const BlockT * DivTermBlock,const BlockT * JoinBlock,const DominatorTreeT & DT,ContextT & Context) getOutermostDivergentCycle() argument
1042 for (const CycleT *Cycle = CI.getCycle(DefBlock); isTemporalDivergent() local
1069 const auto *Cycle = CI.getCycle(JoinBlock); analyzeControlDivergence() local
1175 for (const CycleT *cycle : AssumedDivergent) { print() local
1182 for (const CycleT *cycle : DivergentExitCycles) { print() local
1258 computeStackPO(SmallVectorImpl<const BlockT * > & Stack,const CycleInfoT & CI,const CycleT * Cycle,SmallPtrSetImpl<const BlockT * > & Finalized) computeStackPO() argument
1326 computeCyclePO(const CycleInfoT & CI,const CycleT * Cycle,SmallPtrSetImpl<const BlockT * > & Finalized) computeCyclePO() argument
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H A DGenericCycleInfo.h15 /// - A cycle is a generalization of a loop which can represent
22 /// unique cycle C which is a superset of L.
52 /// The parent cycle. Is null for the root "cycle". Top-level cycles point
56 /// The entry block(s) of the cycle. The header is the only entry if
57 /// this is a loop. Is empty for the root "cycle", to avoid
64 /// Basic blocks that are contained in the cycle, including entry blocks,
65 /// and including blocks that are part of a child cycle.
70 /// Depth of the cycle in the tree. The root "cycle" i
281 print(const CycleT * Cycle) print() argument
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/freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json9 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt…
12 … operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empt…
15 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt…
18 …No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empt…
21 …tion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empt…
24 …tion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empt…
27 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal…
30 …"No operation issued due to the backend interlock.This event counts every cycle that issue is stal…
33 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal…
36 …eration issued due to the backend, interlock, AGU.This event counts every cycle that issue is stal…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A Dpipeline.json21 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc…
24 …operation issued due to the frontend, cache miss. This event counts every cycle that the Data Proc…
27 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr…
30 …o operation issued due to the frontend, TLB miss. This event counts every cycle that the DPU instr…
39 …No operation issued due to the backend interlock. This event counts every cycle where the issue of…
42 …No operation issued due to the backend interlock. This event counts every cycle where the issue of…
45 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of…
48 …ion issued due to the backend, address interlock. This event counts every cycle where the issue of…
51 …, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a s…
54 …, interlock, or the Vector Processing Unit (VPU). This event counts every cycle where there is a s…
[all …]
/freebsd-src/contrib/bmake/unit-tests/
H A Ddotwait.mk5 TESTS= simple recursive shared cycle
56 # cycle: the cyclic dependency must not cause infinite recursion
58 cycle: cycle.1.99 .WAIT cycle.2.99
59 cycle.2.99: cycle.2.98 _ECHOUSE
60 cycle.2.98: cycle.2.97 _ECHOUSE
61 cycle.2.97: cycle.2.99 _ECHOUSE
H A Ddotwait.exp25 cycle.1.99
26 cycle.1.99
27 make: Graph cycles through `cycle.2.99'
28 make: Graph cycles through `cycle.2.98'
29 make: Graph cycles through `cycle.2.97'
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A Dfloating-point.json6 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
13 …X, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. Th…
20 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
27 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
34 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
40 …ent. The number of retired SSE/AVX FLOPS. The number of events logged per cycle can vary from 0 to…
46 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov…
52 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov…
58 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov…
64 …cycle can vary from 0 to 64. This event requires the use of the MergeEvent since it can count abov…
/freebsd-src/share/doc/psd/18.gprof/
H A Dpostp.me100 (a trivial cycle in the call graph)
109 Time is not propagated from one member of a cycle to another,
112 In addition, children of one member of a cycle
113 must be considered children of all members of the cycle.
114 Similarly, parents of one member of the cycle must inherit
115 all members of the cycle as descendants.
117 Our solution collects all members of a cycle together,
119 All calls into the cycle are made to share the total
120 time of the cycle, and all descendants of the cycle
121 propagate time into the cycle as a whole.
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/freebsd-src/usr.bin/gprof/
H A Dgprof.callg31 its membership in a cycle, if any.
58 parent's membership in a cycle, if any.
84 membership in a cycle, if any.
92 children) in the same cycle as the function. If
93 the function (or child) is a member of a cycle,
96 cycle as a whole.
103 cycle listings:
104 the cycle as a whole is listed with the same
106 the members of the cycle, and their contributions
107 to the time and call counts of the cycle.
H A Darcs.c155 * link together nodes on the same cycle in doarcs()
168 printf("[doarcs] pass %ld, cycle(s) %d\n" , pass , ncycle ); in doarcs()
175 "to reduce the maximum cycle size to", cyclethreshold ); in doarcs()
230 * and cycle headers. in doarcs()
326 * add this share to the parent's cycle header, if any. in timepropagate()
352 int cycle; in cyclelink() local
357 * Count the number of cycles, and initialize the cycle lists in cyclelink()
369 * cyclenl is indexed by cycle number: in cyclelink()
374 errx( 1 , "no room for %zu bytes of cycle headers" , in cyclelink()
378 * number them, accumulate the data for the cycle in cyclelink()
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json6 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
13 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
20 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
27 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
34 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
41 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
48 …X, and SSE instructions, including moves. Each increment represents a one-cycle dispatch event. Th…
55 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
62 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
69 …, and SSE instructions, including moves. Each increment represents a one- cycle dispatch event. Th…
[all …]
/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCycleAnalysis.cpp30 "Machine Cycle Info Analysis", true, true)
32 "Machine Cycle Info Analysis", true, true)
77 "Print Machine Cycle Info Analysis", true, true)
80 "Print Machine Cycle Info Analysis", true, true) in INITIALIZE_PASS_DEPENDENCY()
94 bool llvm::isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I) { in isCycleInvariant() argument
101 // The instruction is cycle invariant if all of its operands are. in isCycleInvariant()
128 } else if (any_of(Cycle->getEntries(), in isCycleInvariant()
132 // If the reg is live into any header of the cycle we can't hoist an in isCycleInvariant()
143 // If the cycle contains the definition of an operand, then the instruction in isCycleInvariant()
144 // isn't cycle invariant. in isCycleInvariant()
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H A DScoreboardHazardRecognizer.cpp36 // the scoreboard. We always make the scoreboard at least 1 cycle deep to in ScoreboardHazardRecognizer()
117 int cycle = Stalls; in getHazardType() local
130 // We must find one of the stage's units free for every cycle the in getHazardType()
134 int StageCycle = cycle + (int)i; in getHazardType()
158 LLVM_DEBUG(dbgs() << "*** Hazard in cycle +" << StageCycle << ", "); in getHazardType()
164 // Advance the cycle to the next stage. in getHazardType()
165 cycle += IS->getNextCycles(); in getHazardType()
184 unsigned cycle = 0; in EmitInstruction() local
189 // We must reserve one of the stage's units for every cycle the in EmitInstruction()
193 assert(((cycle + i) < RequiredScoreboard.getDepth()) && in EmitInstruction()
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/freebsd-src/sys/contrib/device-tree/Bindings/regulator/
H A Dpwm-regulator.txt7 predefined voltage <=> duty-cycle values must be
10 Intermediary duty-cycle values which would normally
19 appropriate duty-cycle values. This allows for a much
22 assumption that a %50 duty-cycle value will cause the
33 - voltage-table: Voltage and Duty-Cycle table consisting of 2 cells
35 Second cell is duty-cycle in percent (%)
38 - pwm-dutycycle-unit: Integer value encoding the duty cycle unit. If not
46 Duty cycle values are expressed in pwm-dutycycle-unit.
71 * Inverted PWM logic, and the duty cycle range is limited
85 /* Voltage Duty-Cycle */
H A Dpwm-regulator.yaml19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
29 appropriate duty-cycle values. This allows for a much more fine grained
31 make an assumption that a %50 duty-cycle value will cause the regulator
49 description: Voltage and Duty-Cycle table.
54 - description: duty-cycle in percent (%)
63 Integer value encoding the duty cycle unit. If not
75 Duty cycle values are expressed in pwm-dutycycle-unit.
104 * Inverted PWM logic, and the duty cycle range is limited
119 /* Voltage Duty-Cycle */
/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DModuloSchedule.h18 // A schedule is, for every instruction in a block, a Cycle and a Stage. Note
22 // The Cycle of an instruction defines a partial order of the instructions in
23 // the remapped loop. Instructions within a cycle must not consume the output
24 // of any instruction in the same cycle. Cycle information is assumed to have
79 /// maintain a Cycle and Stage.
85 /// The instructions to be generated, in total order. Cycle provides a partial
90 /// The cycle for each instruction.
91 DenseMap<MachineInstr *, int> Cycle; variable
103 /// \arg Cycle Cycl
109 ModuloSchedule(MachineFunction & MF,MachineLoop * Loop,std::vector<MachineInstr * > ScheduledInstrs,DenseMap<MachineInstr *,int> Cycle,DenseMap<MachineInstr *,int> Stage) ModuloSchedule() argument
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td33 // Two cycle ALU vector operation that uses an entire superslice.
205 // Three cycle ALU vector operation that uses an entire superslice.
290 // 7 cycle DP vector operation that uses an entire superslice.
401 // 5 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
409 // 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
452 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
461 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
468 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
488 // 7 cycle DP operation. One DP unit, one EXEC pipeline and 1 dispatch units.
524 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
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/freebsd-src/sys/contrib/device-tree/Bindings/input/
H A Dpwm-vibrator.yaml14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
39 direction-duty-cycle-ns:
41 Duty cycle of the direction PWM channel in nanoseconds,
58 direction-duty-cycle-ns = <1000000000>;
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_z10/
H A Dbasic.json6 "PublicDescription": "Cycle Count"
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
42 "PublicDescription": "Problem-State Cycle Count"
60 "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
72 "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A Dbasic.json6 "PublicDescription": "Cycle Count"
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
42 "PublicDescription": "Problem-State Cycle Count"
60 "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
72 "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_z196/
H A Dbasic.json6 "PublicDescription": "Cycle Count"
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
42 "PublicDescription": "Problem-State Cycle Count"
60 "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
72 "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
/freebsd-src/lib/libpmc/pmu-events/arch/s390/cf_z13/
H A Dbasic.json6 "PublicDescription": "Cycle Count"
24 "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
36 "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
42 "PublicDescription": "Problem-State Cycle Count"
60 "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
72 "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"

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