Home
last modified time | relevance | path

Searched full:cores (Results 1 – 25 of 511) sorted by relevance

12345678910>>...21

/freebsd-src/sys/arm64/arm64/
H A Dmp_machdep.c723 /* Introduce rest of cores to the world */ in cpu_mp_announce()
733 u_int *cores = arg; in cpu_count_acpi_handler()
737 (*cores)++; in cpu_count_acpi_handler()
749 u_int cores; in cpu_count_acpi()
761 cores = 0; in cpu_count_acpi()
763 cpu_count_acpi_handler, &cores); in cpu_count_acpi()
767 return (cores);
774 int cores; in cpu_mp_setmaxid()
782 cores = cpu_count_acpi(); in cpu_mp_setmaxid()
783 if (cores > in cpu_mp_setmaxid()
729 u_int *cores = arg; cpu_count_acpi_handler() local
745 u_int cores; cpu_count_acpi() local
770 int cores; cpu_mp_setmaxid() local
[all...]
/freebsd-src/sys/dev/bwn/
H A Dif_bwn_pcivar.h56 * WLAN cores.
58 * However, not all cards with two WLAN cores are fully populated;
65 * Some early devices shipped with unconnected ethernet cores; set
66 * this quirk to treat these cores as unpopulated.
72 * host controller cores; set this quirk to treat these cores as
79 * floating analog softmodem codec cores; set this quirk to treat these
80 * cores as unpopulated.
/freebsd-src/lib/libpmc/pmu-events/arch/x86/ivybridge/
H A Duncore-other.json22 …ntroller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic…
26 …ntroller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic…
31 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
37 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
42 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
48 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
53 …: "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic…
58 …: "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic…
/freebsd-src/lib/libpmc/pmu-events/arch/x86/sandybridge/
H A Duncore-other.json22 …ntroller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic…
26 …ntroller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic…
31 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
37 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
42 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
48 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
53 …: "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic…
58 …: "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic…
H A Dcache.json457 …clusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket…
468 …clusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket…
731 …efetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M…
743 …t needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
755 … & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean respo…
791 …efetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M…
803 …emand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S …
815 …t needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
827 … & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean respo…
851 …efetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M…
[all …]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-other.json358 …oop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop fil…
369 …noop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop fil…
380 … snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop fil…
385 "BriefDescription": "TOR Inserts : All requests from iA Cores",
391 …"PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries succ…
397 "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores",
403 …"PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries su…
409 "BriefDescription": "TOR Inserts : CRDs issued by iA Cores",
415 …"PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries success…
421 "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores",
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dvideo.txt1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
/freebsd-src/sys/contrib/device-tree/Bindings/arm/
H A Darm,vexpress-juno.yaml45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
51 - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
77 cores in a test chip on the core tile. See ARM DDI 0498D.
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
85 cores in a big.LITTLE configuration. It also features the MALI T624
/freebsd-src/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15-tc1.dts199 regulator-cores {
203 regulator-name = "Cores";
207 label = "Cores";
210 amp-cores {
211 /* Total current for the two cores */
214 label = "Cores";
224 power-cores {
228 label = "Cores";
235 label = "Cores";
/freebsd-src/lib/libpmc/pmu-events/arch/x86/broadwellde/
H A Duncore-power.json10 …cy event that tracks the number of cores that are in C0. It can be used by itself to get the aver…
21 …cy event that tracks the number of cores that are in C3. It can be used by itself to get the aver…
32 …cy event that tracks the number of cores that are in C6. It can be used by itself to get the aver…
/freebsd-src/lib/libpmc/pmu-events/arch/x86/broadwellx/
H A Duncore-power.json10 …cy event that tracks the number of cores that are in C0. It can be used by itself to get the aver…
21 …cy event that tracks the number of cores that are in C3. It can be used by itself to get the aver…
32 …cy event that tracks the number of cores that are in C6. It can be used by itself to get the aver…
/freebsd-src/lib/libpmc/pmu-events/arch/x86/haswellx/
H A Duncore-power.json10 …cy event that tracks the number of cores that are in C0. It can be used by itself to get the aver…
21 …cy event that tracks the number of cores that are in C3. It can be used by itself to get the aver…
32 …cy event that tracks the number of cores that are in C6. It can be used by itself to get the aver…
H A Dcache.json829 … all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S …
837 … all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S …
842 …d & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M…
850 …d & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M…
855 … all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S …
863 … all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S …
868 …ads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M…
876 …ads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M…
881 …ode/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S …
889 …ode/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S …
[all …]
/freebsd-src/sys/riscv/riscv/
H A Dmp_machdep.c447 /* Introduce rest of cores to the world */
465 int cores; in cpu_mp_setmaxid() local
468 cores = ofw_cpu_early_foreach(cpu_check_mmu, true); in cpu_mp_setmaxid()
469 if (cores > 0) { in cpu_mp_setmaxid()
470 cores = MIN(cores, MAXCPU); in cpu_mp_setmaxid()
472 printf("Found %d CPUs in the device tree\n", cores); in cpu_mp_setmaxid()
473 mp_ncpus = cores; in cpu_mp_setmaxid()
474 mp_maxid = cores - 1; in cpu_mp_setmaxid()
485 if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) { in cpu_mp_setmaxid()
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/timer/
H A Dsnps,arc-timer.txt4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
12 (16 for ARCHS cores, 3 for ARC700 cores)
/freebsd-src/lib/libpmc/pmu-events/arch/x86/icelakex/
H A Duncore-other.json151 "BriefDescription": "TOR Inserts : All requests from iA Cores",
162 "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC",
173 "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
184 "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
195 "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
206 "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
217 "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
228 "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
239 "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
250 "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
[all …]
/freebsd-src/sys/dev/bhnd/
H A Dbhnd_erom.h151 * Parse all cores descriptors in @p erom, returning the array in @p cores and
158 * @param[out] cores The table of parsed core descriptors.
159 * @param[out] num_cores The number of core records in @p cores.
166 bhnd_erom_get_core_table(bhnd_erom_t *erom, struct bhnd_core_info **cores, in bhnd_erom_get_core_table() argument
169 return (BHND_EROM_GET_CORE_TABLE(erom, cores, num_cores)); in bhnd_erom_get_core_table()
176 * @param cores A core table allocated by @p erom.
179 bhnd_erom_free_core_table(bhnd_erom_t *erom, struct bhnd_core_info *cores) in bhnd_erom_free_core_table() argument
181 return (BHND_EROM_FREE_CORE_TABLE(erom, cores)); in bhnd_erom_free_core_table()
H A Dbhnd_erom_if.m114 * Parse all cores descriptors, returning the array in @p cores and the count
121 * @param[out] cores The table of parsed core descriptors.
122 * @param[out] num_cores The number of core records in @p cores.
130 struct bhnd_core_info **cores;
138 * @param cores A core table allocated by @p erom.
142 struct bhnd_core_info *cores;
/freebsd-src/lib/libpmc/pmu-events/arch/x86/sapphirerapids/
H A Duncore-other.json579 …"BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC…
590 …"BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC…
601 …"BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the L…
611 …"BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the L…
4033 "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC",
4044 "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC",
4055 "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores",
4255 …"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC -…
4266 …"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC -…
4277 …"BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC -…
[all …]
/freebsd-src/sys/modules/bhnd/
H A DMakefile2 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/chipc
3 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/chipc/pwrctl
4 .PATH: ${SRCTOP}/sys/dev/bhnd/cores/pmu
68 cores \
/freebsd-src/sys/dev/bhnd/bhndb/
H A Dbhndb_pci.c67 #include <dev/bhnd/cores/pci/bhnd_pcireg.h>
112 struct bhnd_core_info **cores, u_int *ncores);
114 struct bhnd_core_info *cores);
154 * Provides early bus access to the bridged device's cores and core enumeration
169 struct bhnd_core_info *cores; /**< erom-owned core table */ member
170 u_int ncores; /**< number of cores */
296 /* Identify the chip and enumerate the bridged cores */ in bhndb_pci_probe()
357 struct bhnd_core_info *cores, hostb_core; in bhndb_pci_attach() local
374 cores = NULL; in bhndb_pci_attach()
383 /* Identify the chip and enumerate the bridged cores */ in bhndb_pci_attach()
1429 bhndb_pci_probe_copy_core_table(struct bhndb_pci_probe * probe,struct bhnd_core_info ** cores,u_int * ncores) bhndb_pci_probe_copy_core_table() argument
1447 bhndb_pci_probe_free_core_table(struct bhnd_core_info * cores) bhndb_pci_probe_free_core_table() argument
[all...]
/freebsd-src/lib/libpmc/pmu-events/arch/x86/haswell/
H A Dcache.json793 … all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S …
801 … all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S …
806 …d & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M…
814 …d & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M…
819 … all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S …
827 … all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S …
832 …"BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M st…
840 …"PublicDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M s…
845 …"BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the…
853 …"PublicDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and th…
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/bus/
H A Dbrcm,bus-axi.txt9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
/freebsd-src/sys/contrib/device-tree/Bindings/remoteproc/
H A Dti,pru-consumer.yaml37 firmwares for the PRU cores, the default firmware for the core from
39 correspond to the PRU cores listed in the 'ti,prus' property
50 should correspond to the PRU cores listed in the 'ti,prus' property. The
52 and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the
/freebsd-src/share/man/man4/
H A Dsiba.455 These functional blocks, known as cores, use the Open Core Protocol
62 Not all cores contain both an initiator and a target agent.
63 Initiator agents are present in cores that contain
65 or DMA processors associated with communications cores.

12345678910>>...21