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/freebsd-src/sys/contrib/device-tree/Bindings/sound/
H A Dfsl,rpmsg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...]
H A Dzte,zx-i2s.txt4 - compatible : Must be one of:
5 "zte,zx296718-i2s", "zte,zx296702-i2s"
6 "zte,zx296702-i2s"
7 - reg : Must contain I2S core's registers location and length
8 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - clock-names: "wclk" for the wclk, "pclk" for the pclk to the I2S interface.
10 - dmas: Pairs of phandle and specifier for the DMA channel that is used by
11 the core. The core expects two dma channels for transmit.
12 - dma-names : Must be "tx" and "rx"
14 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
[all …]
H A Dstarfive,jh7110-pwmdac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/starfive,jh7110-pwmdac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PWM-DAC Controller
10 The PWM-DAC Controller uses PWM square wave generators plus RC filters to
11 form a DAC for audio play in StarFive JH7110 SoC. This audio play controller
12 supports 16 bit audio format, up to 48K sampling frequency, up to left and
16 - Hal Feng <hal.feng@starfivetech.com>
19 - $ref: dai-common.yaml#
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H A Dxlnx,audio-formatter.txt1 Device-Tree bindings for Xilinx PL audio formatter
3 The IP core supports DMA, data formatting(AES<->PCM conversion)
4 of audio samples.
7 - compatible: "xlnx,audio-formatter-1.0"
8 - interrupt-names: Names specified to list of interrupts in same
13 - interrupts-parent: Phandle for interrupt controller.
14 - interrupts: List of Interrupt numbers.
15 - reg: Base address and size of the IP core instance.
16 - clock-names: List of input clocks.
18 - clocks: Input clock specifier. Refer to common clock bindings.
[all …]
H A Dqcom,lpass-cpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/qcom,lpass-cpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Rohit kumar <quic_rohkumar@quicinc.com>
14 Qualcomm Technologies Inc. SOC Low-Power Audio SubSystem (LPASS) that consist
15 of MI2S interface for audio data transfer on external codecs. LPASS cpu driver
16 is a module to configure Low-Power Audio Interface(LPAIF) core registers
22 - qcom,lpass-cpu
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H A Dpcm186x.txt1 Texas Instruments PCM186x Universal Audio ADC
8 - compatible : "ti,pcm1862",
13 - reg : The I2C address of the device for I2C, the chip select
16 - avdd-supply: Analog core power supply (3.3v)
17 - dvdd-supply: Digital core power supply
18 - iovdd-supply: Digital IO power supply
31 The pins can be used in referring sound node's audio-routing property.
35 pcm186x: audio-codec@4a {
39 avdd-supply = <&reg_3v3_analog>;
40 dvdd-supply = <&reg_3v3>;
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H A Dti,tlv320aic32x4.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320AIC32x4 Stereo Audio codec
11 - Alexander Stein <alexander.stein@ew.tq-group.com>
14 The TLV320AIC32x4 audio codec can be accessed using I2C or SPI
19 - ti,tas2505
20 - ti,tlv320aic32x4
21 - ti,tlv320aic32x6
28 - description: Master clock
[all …]
H A Dti,tlv320aic3x.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 TLV320AIC3x are a series of low-power stereo audio codecs with stereo
13 single-ended or fully differential configurations.
15 The serial control bus supports SPI or I2C protocols, while the serial audio
16 data bus is programmable for I2S, left/right-justified, DSP, or TDM modes.
18 The following pins can be referred in the sound node's audio routing property:
44 - Jai Luthra <j-luthra@ti.com>
49 - ti,tlv320aic3x
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/freebsd-src/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,audiocc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPASS Audio Clock Controller on SM8250 SoCs
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
15 See include/dt-bindings/clock/qcom,sm8250-lpass-audiocc.h for the full list
16 of Audio Clock controller clock IDs.
20 const: qcom,sm8250-lpass-audiocc
25 '#clock-cells':
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H A Dqcom,aoncc-sm8250.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
15 See include/dt-bindings/clock/qcom,sm8250-lpass-aoncc.h for the full list
16 of Audio Clock controller clock IDs.
20 const: qcom,sm8250-lpass-aoncc
25 '#clock-cells':
30 - description: LPASS Core voting clock
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H A Dmvebu-gated-clock.txt12 -----------------------------------
13 0 Audio AC97 Cntrl
29 -----------------------------------
35 8 audio Audio Cntrl
38 15 sata0_core SATA 0 Core
44 21 sata1_core SATA 1 Core
50 29 crypto0_core Cryptographic Unit Port 0 Core
52 31 crypto1_core Cryptographic Unit Port 1 Core
56 -----------------------------------
57 0 audio Audio
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/freebsd-src/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,apr-services.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,apr-services.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
22 3 = DSP Core Service
23 4 = Audio Front End Service.
26 7 = Audio Stream Manager Service.
27 8 = Audio Device Manager Service.
29 10 = Core voice stream.
[all …]
H A Dqcom,apr.txt5 used for audio/voice services on the QDSP.
7 - compatible:
10 Definition: must be "qcom,apr-v<VERSION-NUMBER>", example "qcom,apr-v2"
12 - qcom,apr-domain
17 1 - APR simulator
18 2 - PC
19 3 - MODEM
20 4 - ADSP
21 5 - APPS
22 6 - MODEM2
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/freebsd-src/sys/contrib/device-tree/Bindings/dsp/
H A Dmediatek,mt8195-dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek mt8195 DSP core
10 - YC Hung <yc.hung@mediatek.com>
13 Some boards from mt8195 contain a DSP core used for
14 advanced pre- and post- audio processing.
18 const: mediatek,mt8195-dsp
22 - description: Address and size of the DSP Cfg registers
[all …]
H A Dmediatek,mt8186-dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek mt8186 DSP core
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 MediaTek mt8186 SoC contains a DSP core used for
14 advanced pre- and post- audio processing.
19 - mediatek,mt8186-dsp
20 - mediatek,mt8188-dsp
[all …]
/freebsd-src/sys/contrib/device-tree/Bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pm
[all...]
/freebsd-src/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
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/freebsd-src/sys/contrib/device-tree/Bindings/display/bridge/
H A Dsil,sii9022.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Boris Brezillon <bbrezillon@kernel.org>
15 - items:
16 - enum:
17 - sil,sii9022-cpi # CEC Programming Interface
18 - sil,sii9022-tpi # Transmitter Programming Interface
19 - const: sil,sii9022
20 - const: sil,sii9022
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/freebsd-src/sys/contrib/device-tree/Bindings/pinctrl/
H A Dqcom,sm8350-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
19 const: qcom,sm8350-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers
[all …]
H A Dqcom,sm8550-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
20 - const: qcom,sm8550-lpass-lpi-pinctrl
21 - items:
22 - const: qcom,x1e80100-lpass-lpi-pinctrl
[all …]
H A Dqcom,sm8250-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
18 const: qcom,sm8250-lpass-lpi-pinctrl
25 - description: LPASS Core voting clock
26 - description: LPASS Audio voting clock
28 clock-names:
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H A Dqcom,sm8650-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
14 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
19 const: qcom,sm8650-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
27 - description: LPASS Core voting clock
[all …]
H A Dqcom,sc8280xp-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
18 const: qcom,sc8280xp-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
27 - description: LPASS Core voting clock
[all …]
H A Dqcom,lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
19 const: qcom,sm8250-lpass-lpi-pinctrl
27 - description: LPASS Core voting clock
28 - description: LPASS Audio voting clock
30 clock-names:
[all …]
H A Dqcom,sm8450-lpass-lpi-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
27 - description: LPASS Core voting clock
[all …]

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