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/llvm-project/llvm/test/CodeGen/MSP430/
H A DBranchSelector.ll5 @reg = common global i16 0, align 2
12 store volatile i16 11, ptr @reg, align 2
13 store volatile i16 13, ptr @reg, align 2
14 store volatile i16 17, ptr @reg, align 2
15 store volatile i16 11, ptr @reg, align 2
16 store volatile i16 13, ptr @reg, align 2
17 store volatile i16 17, ptr @reg, align 2
18 store volatile i16 11, ptr @reg, align 2
19 store volatile i16 13, ptr @reg, align 2
20 store volatile i16 17, ptr @reg, align
[all...]
H A Dmult-alt-generic-msp430.ll6 @mout0 = common global i16 0, align 2
7 @min1 = common global i16 0, align 2
8 @marray = common global [2 x i16] zeroinitializer, align 2
18 %out0 = alloca i16, align 2
19 %index = alloca i16, align 2
20 store i16 0, ptr %out0, align 2
21 store i16 1, ptr %index, align 2
32 %out0 = alloca i16, align 2
33 %in1 = alloca i16, align 2
34 store i16 0, ptr %out0, align
[all...]
/llvm-project/llvm/test/CodeGen/Mips/
H A Dra-allocatable.ll101 %0 = load i32, ptr @a0, align 4
102 %1 = load ptr, ptr @b0, align 4
103 store i32 %0, ptr %1, align 4
104 %2 = load i32, ptr @a1, align 4
105 %3 = load ptr, ptr @b1, align 4
106 store i32 %2, ptr %3, align 4
107 %4 = load i32, ptr @a2, align 4
108 %5 = load ptr, ptr @b2, align 4
109 store i32 %4, ptr %5, align 4
110 %6 = load i32, ptr @a3, align
[all...]
H A Ddagcombine-store-gep-chain-slow.ll11 %e4.addr = alloca i32, align 4
12 %old_val = alloca i8, align 1
13 %new_val = alloca i8, align 1
14 %simd = alloca i8, align 1
15 %code = alloca [269 x i8], align 1
16 store i32 %e4, ptr %e4.addr, align 4
18 store i8 %call, ptr %simd, align 1
20 store i8 32, ptr %code, align 1
22 %a2 = load i8, ptr %old_val, align 1
23 store i8 %a2, ptr %arrayinit.element, align
[all...]
/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dhrc-stack-coloring.ll28 %v0 = alloca ptr, align 4
29 %v1 = alloca ptr, align 4
30 %v2 = alloca ptr, align 4
31 %v3 = alloca float, align 4
32 %v4 = alloca float, align 4
33 %v5 = alloca float, align 4
34 %v6 = alloca float, align 4
35 %v7 = alloca float, align 4
36 %v8 = alloca float, align 4
37 %v9 = alloca float, align
[all...]
/llvm-project/llvm/test/Analysis/CostModel/X86/
H A Dload_store.ll13 …NEXT: Cost Model: Found an estimated cost of 1 for instruction: store i8 undef, ptr undef, align 4
14 …EXT: Cost Model: Found an estimated cost of 1 for instruction: store i16 undef, ptr undef, align 4
15 …EXT: Cost Model: Found an estimated cost of 1 for instruction: store i32 undef, ptr undef, align 4
16 …EXT: Cost Model: Found an estimated cost of 1 for instruction: store i64 undef, ptr undef, align 4
17 …XT: Cost Model: Found an estimated cost of 2 for instruction: store i128 undef, ptr undef, align 4
18 …XT: Cost Model: Found an estimated cost of 4 for instruction: store i256 undef, ptr undef, align 4
19 …XT: Cost Model: Found an estimated cost of 8 for instruction: store i512 undef, ptr undef, align 4
20 …T: Cost Model: Found an estimated cost of 1 for instruction: store float undef, ptr undef, align 4
21 …: Cost Model: Found an estimated cost of 1 for instruction: store double undef, ptr undef, align 4
22 …EXT: Cost Model: Found an estimated cost of 1 for instruction: store ptr undef, ptr undef, align 4
[all …]
/llvm-project/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/
H A Dvectorize_i8.ll5 define void @int8x3a2(ptr nocapture align 2 %ptr) {
10 %l0 = load i8, ptr %ptr0, align 2
11 %l1 = load i8, ptr %ptr1, align 1
12 %l2 = load i8, ptr %ptr2, align 2
14 store i8 %l2, ptr %ptr0, align 2
15 store i8 %l1, ptr %ptr1, align 1
16 store i8 %l0, ptr %ptr2, align 2
27 define void @int8x3a4(ptr nocapture align 4 %ptr) {
32 %l0 = load i8, ptr %ptr0, align 4
33 %l1 = load i8, ptr %ptr1, align 1
[all …]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dupdate-lds-alignment.ll22 …m.amdgcn.kernel.k0.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k0.lds.t poison, align 16
23 …m.amdgcn.kernel.k1.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k1.lds.t poison, align 16
24 …m.amdgcn.kernel.k2.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k2.lds.t poison, align 16
25 …vm.amdgcn.kernel.k3.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k3.lds.t poison, align 8
26 …m.amdgcn.kernel.k4.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k4.lds.t poison, align 16
27 …m.amdgcn.kernel.k5.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k5.lds.t poison, align 16
31 ; CHECK-NOT: @k0.lds.size.1.align.1
32 ; CHECK-NOT: @k0.lds.size.2.align.2
33 ; CHECK-NOT: @k0.lds.size.4.align.4
34 ; CHECK-NOT: @k0.lds.size.8.align.8
[all …]
H A Dlds-alignment.ll3 @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
4 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
6 @lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8
7 @lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32
9 @lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef
10 @lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] undef
19 …call void @llvm.memcpy.p3.p1.i32(ptr addrspace(3) align 4 @lds.align16.0, ptr addrspace(1) align 4…
20 …call void @llvm.memcpy.p1.p3.i32(ptr addrspace(1) align 4 %out, ptr addrspace(3) align 4 @lds.alig…
36 …call void @llvm.memcpy.p3.p1.i32(ptr addrspace(3) align 4 @lds.align16.0, ptr addrspace(1) align 4…
37 …call void @llvm.memcpy.p1.p3.i32(ptr addrspace(1) align 4 %out, ptr addrspace(3) align 4 @lds.alig…
[all …]
/llvm-project/llvm/test/CodeGen/PowerPC/
H A Dmult-alt-generic-powerpc64.ll6 @mout0 = common global i32 0, align 4
7 @min1 = common global i32 0, align 4
8 @marray = common global [2 x i32] zeroinitializer, align 4
18 %out0 = alloca i32, align 4
19 %index = alloca i32, align 4
20 store i32 0, ptr %out0, align 4
21 store i32 1, ptr %index, align 4
32 %out0 = alloca i32, align 4
33 %in1 = alloca i32, align 4
34 store i32 0, ptr %out0, align 4
[all …]
H A Dmult-alt-generic-powerpc.ll6 @mout0 = common global i32 0, align 4
7 @min1 = common global i32 0, align 4
8 @marray = common global [2 x i32] zeroinitializer, align 4
18 %out0 = alloca i32, align 4
19 %index = alloca i32, align 4
20 store i32 0, ptr %out0, align 4
21 store i32 1, ptr %index, align 4
32 %out0 = alloca i32, align 4
33 %in1 = alloca i32, align 4
34 store i32 0, ptr %out0, align 4
[all …]
H A DfloatPSA.ll12 %a.addr = alloca float, align 4
13 %b.addr = alloca float, align 4
14 %c.addr = alloca float, align 4
15 %d.addr = alloca float, align 4
16 %e.addr = alloca float, align 4
17 %f.addr = alloca float, align 4
18 %g.addr = alloca float, align 4
19 %h.addr = alloca float, align 4
20 %i.addr = alloca float, align 4
21 %j.addr = alloca float, align 4
[all …]
H A DAtomics-64.ll18 @sl = common global i64 0, align 8
19 @ul = common global i64 0, align 8
20 @sll = common global i64 0, align 8
21 @ull = common global i64 0, align 8
82 store i8 %0, ptr @sc, align 1
84 store i8 %1, ptr @uc, align 1
86 store i16 %2, ptr @ss, align 2
88 store i16 %3, ptr @us, align 2
90 store i32 %4, ptr @si, align 4
92 store i32 %5, ptr @ui, align 4
[all …]
/llvm-project/llvm/test/CodeGen/ARM/
H A Dmult-alt-generic-arm.ll6 @mout0 = common global i32 0, align 4
7 @min1 = common global i32 0, align 4
8 @marray = common global [2 x i32] zeroinitializer, align 4
18 %out0 = alloca i32, align 4
19 %index = alloca i32, align 4
20 store i32 0, ptr %out0, align 4
21 store i32 1, ptr %index, align 4
32 %out0 = alloca i32, align 4
33 %in1 = alloca i32, align 4
34 store i32 0, ptr %out0, align 4
[all …]
/llvm-project/llvm/test/CodeGen/SPARC/
H A Dmult-alt-generic-sparc.ll6 @mout0 = common global i32 0, align 4
7 @min1 = common global i32 0, align 4
8 @marray = common global [2 x i32] zeroinitializer, align 4
18 %out0 = alloca i32, align 4
19 %index = alloca i32, align 4
20 store i32 0, ptr %out0, align 4
21 store i32 1, ptr %index, align 4
32 %out0 = alloca i32, align 4
33 %in1 = alloca i32, align 4
34 store i32 0, ptr %out0, align
[all...]
/llvm-project/llvm/test/Analysis/IRSimilarityIdentifier/
H A Dbasic.ll9 ; CHECK-NEXT: Start Instruction: store i32 1, ptr %1, align 4
10 ; CHECK-NEXT: End Instruction: store i32 6, ptr %6, align 4
12 ; CHECK-NEXT: Start Instruction: store i32 6, ptr %0, align 4
13 ; CHECK-NEXT: End Instruction: store i32 5, ptr %5, align 4
15 ; CHECK-NEXT: Start Instruction: store i32 6, ptr %0, align 4
16 ; CHECK-NEXT: End Instruction: store i32 5, ptr %5, align 4
18 ; CHECK-NEXT: Start Instruction: store i32 6, ptr %0, align 4
19 ; CHECK-NEXT: End Instruction: store i32 5, ptr %5, align 4
22 ; CHECK-NEXT: Start Instruction: store i32 2, ptr %2, align 4
23 ; CHECK-NEXT: End Instruction: store i32 6, ptr %6, align 4
[all …]
/llvm-project/llvm/test/Instrumentation/HWAddressSanitizer/
H A Dglobals-tag.ll262 @g_0 = dso_local global i32 0, align 4
263 @g_1 = dso_local global i32 0, align 4
264 @g_2 = dso_local global i32 0, align 4
265 @g_3 = dso_local global i32 0, align 4
266 @g_4 = dso_local global i32 0, align 4
267 @g_5 = dso_local global i32 0, align 4
268 @g_6 = dso_local global i32 0, align 4
269 @g_7 = dso_local global i32 0, align 4
270 @g_8 = dso_local global i32 0, align 4
271 @g_9 = dso_local global i32 0, align 4
[all …]
/llvm-project/llvm/test/Transforms/InstCombine/
H A Delement-atomic-memintrins.ll11 call void @llvm.memset.element.unordered.atomic.p0.i32(ptr align 1 %dest, i8 1, i32 0, i32 1)
17 ; CHECK-NEXT: store atomic i8 1, ptr [[DEST:%.*]] unordered, align 1
18 ; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0.i32(ptr nonnull align 1 [[DEST]…
19 ; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0.i32(ptr nonnull align 1 [[DEST]…
20 ; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0.i32(ptr nonnull align 1 [[DEST]…
21 ; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0.i32(ptr nonnull align 1 [[DEST]…
24 call void @llvm.memset.element.unordered.atomic.p0.i32(ptr align 1 %dest, i8 1, i32 1, i32 1)
25 call void @llvm.memset.element.unordered.atomic.p0.i32(ptr align 1 %dest, i8 1, i32 2, i32 1)
26 call void @llvm.memset.element.unordered.atomic.p0.i32(ptr align 1 %dest, i8 1, i32 4, i32 1)
27 call void @llvm.memset.element.unordered.atomic.p0.i32(ptr align 1 %dest, i8 1, i32 8, i32 1)
[all …]
/llvm-project/llvm/test/Transforms/LoopVectorize/ARM/
H A Dmve-interleaved-cost.ll18 ; VF_2: Found an estimated cost of 12 for VF 2 For instruction: %tmp2 = load i8, ptr %tmp0, align 1
19 ; VF_2-NEXT: Found an estimated cost of 12 for VF 2 For instruction: %tmp3 = load i8, ptr %tmp1, align 1
20 ; VF_2-NEXT: Found an estimated cost of 4 for VF 2 For instruction: store i8 %tmp2, ptr %tmp0, align 1
21 ; VF_2-NEXT: Found an estimated cost of 4 for VF 2 For instruction: store i8 %tmp3, ptr %tmp1, align 1
23 ; VF_4: Found an estimated cost of 4 for VF 4 For instruction: %tmp2 = load i8, ptr %tmp0, align 1
24 ; VF_4-NEXT: Found an estimated cost of 0 for VF 4 For instruction: %tmp3 = load i8, ptr %tmp1, align 1
25 ; VF_4-NEXT: Found an estimated cost of 0 for VF 4 For instruction: store i8 %tmp2, ptr %tmp0, align 1
26 ; VF_4-NEXT: Found an estimated cost of 4 for VF 4 For instruction: store i8 %tmp3, ptr %tmp1, align 1
28 ; VF_8: Found an estimated cost of 4 for VF 8 For instruction: %tmp2 = load i8, ptr %tmp0, align 1
29 ; VF_8-NEXT: Found an estimated cost of 0 for VF 8 For instruction: %tmp3 = load i8, ptr %tmp1, align
[all...]
/llvm-project/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-xl-xst.c12 // CHECK-NEXT: [[__VEC_ADDR_I:%.*]] = alloca <8 x i16>, align 16
13 // CHECK-NEXT: [[__OFFSET_ADDR_I1:%.*]] = alloca i64, align 8
14 // CHECK-NEXT: [[__PTR_ADDR_I2:%.*]] = alloca ptr, align 8
15 // CHECK-NEXT: [[__ADDR_I3:%.*]] = alloca ptr, align 8
16 // CHECK-NEXT: [[__OFFSET_ADDR_I:%.*]] = alloca i64, align 8
17 // CHECK-NEXT: [[__PTR_ADDR_I:%.*]] = alloca ptr, align 8
18 // CHECK-NEXT: [[__ADDR_I:%.*]] = alloca ptr, align 8
19 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
20 // CHECK-NEXT: [[ST_ADDR:%.*]] = alloca ptr, align 8
21 // CHECK-NEXT: [[LD_ADDR:%.*]] = alloca ptr, align 8
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Darm64-vext.ll6 %xS8x8 = alloca <8 x i8>, align 8
7 %__a = alloca <8 x i8>, align 8
8 %__b = alloca <8 x i8>, align 8
9 %tmp = load <8 x i8>, ptr %xS8x8, align 8
10 store <8 x i8> %tmp, ptr %__a, align 8
11 %tmp1 = load <8 x i8>, ptr %xS8x8, align 8
12 store <8 x i8> %tmp1, ptr %__b, align 8
13 %tmp2 = load <8 x i8>, ptr %__a, align 8
14 %tmp3 = load <8 x i8>, ptr %__b, align 8
16 store <8 x i8> %vext, ptr %xS8x8, align 8
[all …]
/llvm-project/llvm/test/CodeGen/X86/
H A Dmult-alt-generic-i686.ll6 @mout0 = common global i32 0, align 4
7 @min1 = common global i32 0, align 4
8 @marray = common global [2 x i32] zeroinitializer, align 4
18 %out0 = alloca i32, align 4
19 %index = alloca i32, align 4
20 store i32 0, ptr %out0, align 4
21 store i32 1, ptr %index, align 4
32 %out0 = alloca i32, align 4
33 %in1 = alloca i32, align 4
34 store i32 0, ptr %out0, align 4
[all …]
H A Dmult-alt-generic-x86_64.ll6 @mout0 = common global i32 0, align 4
7 @min1 = common global i32 0, align 4
8 @marray = common global [2 x i32] zeroinitializer, align 4
18 %out0 = alloca i32, align 4
19 %index = alloca i32, align 4
20 store i32 0, ptr %out0, align 4
21 store i32 1, ptr %index, align 4
32 %out0 = alloca i32, align 4
33 %in1 = alloca i32, align 4
34 store i32 0, ptr %out0, align 4
[all …]
/llvm-project/llvm/test/Transforms/MemCpyOpt/
H A Dmemcpy.ll25 ; CHECK-NEXT: [[TMP2:%.*]] = alloca [[TMP0:%.*]], align 16
26 ; CHECK-NEXT: [[MEMTMP:%.*]] = alloca [[TMP0]], align 16
29 ; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 16 [[AGG_RESULT:%.*]], ptr align 16 [[TMP2]], i32 32, i1 false)
34 %memtmp = alloca %0, align 16
37 call void @llvm.memcpy.p0.p0.i32(ptr align 16 %tmp2, ptr align 16 %memtmp, i32 32, i1 false)
38 call void @llvm.memcpy.p0.p0.i32(ptr align 16 %agg.result, ptr align 16 %tmp2, i32 32, i1 false)
49 ; CHECK-NEXT: call void @llvm.memmove.p0.p0.i32(ptr align 1
[all...]
/llvm-project/lld/test/wasm/Inputs/
H A Dmany-funcs.ll3 @g0 = global i32 1, align 4
4 @foo = global i32 1, align 4
8 %0 = load i32, ptr @foo, align 4
14 %0 = load i32, ptr @foo, align 4
20 %0 = load i32, ptr @foo, align 4
26 %0 = load i32, ptr @foo, align 4
32 %0 = load i32, ptr @foo, align 4
38 %0 = load i32, ptr @foo, align 4
44 %0 = load i32, ptr @foo, align 4
50 %0 = load i32, ptr @foo, align 4
[all …]

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