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/llvm-project/llvm/test/ObjectYAML/MachO/
H A Drelocations_ppc_big_endian.yaml6 # OBJDUMP-VERIFY-NEXT: 00000030 False long n/a 11 True 0x00000144
7 # OBJDUMP-VERIFY-NEXT: 00000000 False long n/a 1 True 0x00000018
8 # OBJDUMP-VERIFY-NEXT: 0000002c False long n/a 12 True 0x00000144
9 # OBJDUMP-VERIFY-NEXT: 0000012c False long n/a 1 True 0x00000018
10 # OBJDUMP-VERIFY-NEXT: 00000028 False long n/a 11 True 0x000000d4
11 # OBJDUMP-VERIFY-NEXT: 00000000 False long n/a 1 True 0x00000018
12 # OBJDUMP-VERIFY-NEXT: 00000024 False long n/a 12 True 0x000000d4
13 # OBJDUMP-VERIFY-NEXT: 000000bc False long n/a 1 True 0x00000018
17 # OBJDUMP-VERIFY-NEXT: 00000034 False long n/a 11 True 0x00000144
18 # OBJDUMP-VERIFY-NEXT: 00000000 False long n/a 1 True 0x00000068
[all …]
/llvm-project/lldb/test/Shell/ScriptInterpreter/Python/Crashlog/Inputs/interactive_crashlog/
H A Dmultithread-test.yaml3 magic: 0xFEEDFACF
4 cputype: 0x100000C
5 cpusubtype: 0x0
6 filetype: 0x2
9 flags: 0x218085
10 reserved: 0x0
15 vmaddr: 0
17 fileoff: 0
18 filesize: 0
19 maxprot: 0
[all …]
/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 ((Imm % 4 == 0) &&
40 Imm < 28 && Imm > 0);}]>;
208 let hasDelaySlot = 0;
223 bit mayStore = 0;
233 bit mayLoad = 0;
305 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
407 let hasSideEffects = 0;
612 ARITH_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
614 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
[all …]
/llvm-project/lldb/test/API/lang/rust/enum-structs/
H A Dmain.yaml12 AddressAlign: 0x4
16 AddressAlign: 0x10
21 AddressAlign: 0x10
26 AddressAlign: 0x10
31 AddressAlign: 0x10
36 AddressAlign: 0x10
41 AddressAlign: 0x4
46 AddressAlign: 0x10
51 AddressAlign: 0x10
56 AddressAlign: 0x10
[all …]