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/llvm-project/llvm/test/Analysis/CostModel/X86/
H A Dmul-latency.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=latency -matt
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H A Dmul.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -mattr=+sse2 | FileCheck %s --chec
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H A Dmul-sizelatency.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=size-latenc
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H A Dmul-codesize.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-siz
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H A Drem-latency.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=latency -matt
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H A Drem-sizelatency.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=size-latenc
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H A Drem-codesize.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-siz
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H A Ddiv-latency.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=latency -matt
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H A Ddiv-sizelatency.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=size-latenc
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H A Ddiv-codesize.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -cost-kind=code-siz
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H A Ddiv.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -mattr=+sse2 | FileCheck %s --chec
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H A Drem.ll2 ; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -passes="print<cost-model>" 2>&1 -disable-output -mattr=+sse2 | FileCheck %s --chec
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/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
H A Dmul.ll2 ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=ALL,SLOW16 %s
3 ; RUN: opt -passe
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H A Ddiv.ll2 ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixe
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H A Drem.ll2 ; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixe
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/llvm-project/mlir/test/Integration/GPU/CUDA/TensorCore/
H A Dwmma-matmul-f32.mlir1 // RUN: mlir-opt %s \
2 // RUN: | mlir-opt -gpu-lower-to-nvvm-pipeline="cubin-chip=sm_70 cubin-format=%gpu_compilation_format" \
3 // RUN: | mlir-runne
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/llvm-project/llvm/test/Analysis/CostModel/AArch64/
H A Ddiv.ll2 ; RUN: opt < %s -mtriple=aarch64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output | FileCheck %s
4 target datalayout = "e-m:e-i
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H A Drem.ll2 ; RUN: opt < %s -mtriple=aarch64-unknown-linux-gnu -passes="print<cost-model>" 2>&1 -disable-output | FileCheck %s
4 target datalayout = "e-m:e-i
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/llvm-project/llvm/test/MC/AArch64/
H A Dneon-tbl.s1 // RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s
5 //------------------------------------------------------------------------------
7 //------------------------------------------------------------------------------
9 tbl v0.8b, { v1.16b }, v2.8b
10 tbl v0.8b, { v1.16b, v2.16b }, v2.8b
11 tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
12 tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
13 tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
15 // CHECK: tbl v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x00,0x02,0x0e]
16 // CHECK: tbl v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x20,0x02,0x0e]
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/llvm-project/llvm/test/CodeGen/AArch64/
H A Dmisched-fusion-aes.ll1 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto | FileCheck %s
2 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s
3 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s
4 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s
5 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a65 | FileCheck %s
6 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s
7 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s
8 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a76 | FileCheck %s
9 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a77 | FileCheck %s
10 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a78 | FileCheck %s
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/llvm-project/llvm/test/CodeGen/X86/
H A Davx512-vpternlog-commute.ll2 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s
6 declare <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i32)
8 define <16 x i32> @vpternlog_v16i32_012(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2) {
9 ; CHECK-LABEL: vpternlog_v16i32_012:
11 ; CHECK-NEXT: vpternlogd $114, %zmm2, %zmm1, %zmm0
12 ; CHECK-NEXT: retq
13 …%1 = call <16 x i32> @llvm.x86.avx512.pternlog.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x…
14 ret <16 x i32> %1
17 define <16 x i32> @vpternlog_v16i32_102(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2) {
18 ; CHECK-LABEL: vpternlog_v16i32_102:
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/llvm-project/llvm/test/CodeGen/ARM/
H A Dmisched-fusion-aes.ll1 ; RUN: llc %s -o - -mtriple=armv8 -mattr=+crypto,+fuse-aes -enable-misched -disable-post-ra | FileC…
3 declare <16 x i8> @llvm.arm.neon.aese(<16 x i8> %d, <16 x i8> %k)
4 declare <16 x i8> @llvm.arm.neon.aesmc(<16 x i8> %d)
5 declare <16 x i8> @llvm.arm.neon.aesd(<16 x i8> %d, <16 x i8> %k)
6 declare <16 x i8> @llvm.arm.neon.aesimc(<16 x i8> %d)
8 define void @aesea(ptr %a0, ptr %b0, ptr %c0, <16 x i8> %d, <16 x i8> %e) {
9 %d0 = load <16 x i8>, ptr %a0
10 %a1 = getelementptr inbounds <16 x i8>, ptr %a0, i64 1
11 %d1 = load <16 x i8>, ptr %a1
12 %a2 = getelementptr inbounds <16 x i8>, ptr %a0, i64 2
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/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dvec-cmp-01.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
6 define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
7 ; CHECK-LABEL: f1:
9 ; CHECK-NEXT: br %r14
10 %cmp = icmp eq <16 x i8> %val1, %val2
11 %ret = sext <16 x i1> %cmp to <16 x i8>
12 ret <16 x i8> %ret
16 define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
17 ; CHECK-LABEL: f2:
18 ; CHECK: vceqb [[REG:%v[0-9]+]], %v26, %v28
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/llvm-project/llvm/test/CodeGen/Hexagon/
H A Dintrinsics-v60-alu.ll1 ; RUN: llc -mtriple=hexagon < %s | FileCheck %s
3 ; CHECK-LABEL: test1:
4 ; CHECK: v{{[0-9]+}} = vand(v{{[0-9]+}},v{{[0-9]+}})
5 define <16 x i32> @test1(<16 x i32> %a, <16 x i32> %b) #0 {
7 %0 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16
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/llvm-project/mlir/test/Dialect/Vector/
H A Dvector-mem-transforms.mlir1 // RUN: mlir-opt %s -test-vector-to-vector-lowering | FileCheck %s
3 // CHECK-LABEL: func @maskedload0(
4 // CHECK-SAME: %[[A0:.*]]: memref<?xf32>,
5 // CHECK-SAME: %[[A1:.*]]: vector<16xf32>) -> vector<16xf32> {
6 // CHECK-DAG: %[[C:.*]] = arith.constant 0 : index
7 // CHECK-NEXT: %[[T:.*]] = vector.load %[[A0]][%[[C]]] : memref<?xf32>, vector<16xf32>
8 // CHECK-NEXT: return %[[T]] : vector<16xf32>
9 func.func @maskedload0(%base: memref<?xf32>, %pass_thru: vector<16xf32>) -> vector<16xf32> {
11 %mask = vector.constant_mask [16] : vector<16xi1>
13 : memref<?xf32>, vector<16xi1>, vector<16xf32> into vector<16xf32>
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