1 /* $NetBSD: dmub_cmd.h,v 1.2 2021/12/18 23:45:06 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef _DMUB_CMD_H_ 29 #define _DMUB_CMD_H_ 30 31 #include "dmub_types.h" 32 #include "dmub_cmd_dal.h" 33 #include "dmub_cmd_vbios.h" 34 #include "atomfirmware.h" 35 36 #define DMUB_RB_CMD_SIZE 64 37 #define DMUB_RB_MAX_ENTRY 128 38 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 39 #define REG_SET_MASK 0xFFFF 40 41 42 /* 43 * Command IDs should be treated as stable ABI. 44 * Do not reuse or modify IDs. 45 */ 46 47 enum dmub_cmd_type { 48 DMUB_CMD__NULL = 0, 49 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 50 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 51 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 52 DMUB_CMD__REG_REG_WAIT = 4, 53 DMUB_CMD__PLAT_54186_WA = 5, 54 DMUB_CMD__PSR = 64, 55 DMUB_CMD__VBIOS = 128, 56 }; 57 58 #pragma pack(push, 1) 59 60 struct dmub_cmd_header { 61 unsigned int type : 8; 62 unsigned int sub_type : 8; 63 unsigned int reserved0 : 8; 64 unsigned int payload_bytes : 6; /* up to 60 bytes */ 65 unsigned int reserved1 : 2; 66 }; 67 68 /* 69 * Read modify write 70 * 71 * 60 payload bytes can hold up to 5 sets of read modify writes, 72 * each take 3 dwords. 73 * 74 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 75 * 76 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 77 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 78 */ 79 struct dmub_cmd_read_modify_write_sequence { 80 uint32_t addr; 81 uint32_t modify_mask; 82 uint32_t modify_value; 83 }; 84 85 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 86 struct dmub_rb_cmd_read_modify_write { 87 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE 88 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 89 }; 90 91 /* 92 * Update a register with specified masks and values sequeunce 93 * 94 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 95 * 96 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 97 * 98 * 99 * USE CASE: 100 * 1. auto-increment register where additional read would update pointer and produce wrong result 101 * 2. toggle a bit without read in the middle 102 */ 103 104 struct dmub_cmd_reg_field_update_sequence { 105 uint32_t modify_mask; // 0xffff'ffff to skip initial read 106 uint32_t modify_value; 107 }; 108 109 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 110 111 struct dmub_rb_cmd_reg_field_update_sequence { 112 struct dmub_cmd_header header; 113 uint32_t addr; 114 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 115 }; 116 117 118 /* 119 * Burst write 120 * 121 * support use case such as writing out LUTs. 122 * 123 * 60 payload bytes can hold up to 14 values to write to given address 124 * 125 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 126 */ 127 #define DMUB_BURST_WRITE_VALUES__MAX 14 128 struct dmub_rb_cmd_burst_write { 129 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE 130 uint32_t addr; 131 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 132 }; 133 134 135 struct dmub_rb_cmd_common { 136 struct dmub_cmd_header header; 137 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 138 }; 139 140 struct dmub_cmd_reg_wait_data { 141 uint32_t addr; 142 uint32_t mask; 143 uint32_t condition_field_value; 144 uint32_t time_out_us; 145 }; 146 147 struct dmub_rb_cmd_reg_wait { 148 struct dmub_cmd_header header; 149 struct dmub_cmd_reg_wait_data reg_wait; 150 }; 151 152 #ifndef PHYSICAL_ADDRESS_LOC 153 #define PHYSICAL_ADDRESS_LOC union large_integer 154 #endif 155 156 struct dmub_cmd_PLAT_54186_wa { 157 uint32_t DCSURF_SURFACE_CONTROL; 158 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; 159 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; 160 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; 161 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; 162 struct { 163 uint8_t hubp_inst : 4; 164 uint8_t tmz_surface : 1; 165 uint8_t immediate :1; 166 uint8_t vmid : 4; 167 uint8_t grph_stereo : 1; 168 uint32_t reserved : 21; 169 } flip_params; 170 uint32_t reserved[9]; 171 }; 172 173 struct dmub_rb_cmd_PLAT_54186_wa { 174 struct dmub_cmd_header header; 175 struct dmub_cmd_PLAT_54186_wa flip; 176 }; 177 178 struct dmub_cmd_digx_encoder_control_data { 179 union dig_encoder_control_parameters_v1_5 dig; 180 }; 181 182 struct dmub_rb_cmd_digx_encoder_control { 183 struct dmub_cmd_header header; 184 struct dmub_cmd_digx_encoder_control_data encoder_control; 185 }; 186 187 struct dmub_cmd_set_pixel_clock_data { 188 struct set_pixel_clock_parameter_v1_7 clk; 189 }; 190 191 struct dmub_rb_cmd_set_pixel_clock { 192 struct dmub_cmd_header header; 193 struct dmub_cmd_set_pixel_clock_data pixel_clock; 194 }; 195 196 struct dmub_cmd_enable_disp_power_gating_data { 197 struct enable_disp_power_gating_parameters_v2_1 pwr; 198 }; 199 200 struct dmub_rb_cmd_enable_disp_power_gating { 201 struct dmub_cmd_header header; 202 struct dmub_cmd_enable_disp_power_gating_data power_gating; 203 }; 204 205 struct dmub_cmd_dig1_transmitter_control_data { 206 struct dig_transmitter_control_parameters_v1_6 dig; 207 }; 208 209 struct dmub_rb_cmd_dig1_transmitter_control { 210 struct dmub_cmd_header header; 211 struct dmub_cmd_dig1_transmitter_control_data transmitter_control; 212 }; 213 214 struct dmub_rb_cmd_dpphy_init { 215 struct dmub_cmd_header header; 216 uint8_t reserved[60]; 217 }; 218 219 struct dmub_cmd_psr_copy_settings_data { 220 uint16_t psr_level; 221 uint8_t hubp_inst; 222 uint8_t dpp_inst; 223 uint8_t mpcc_inst; 224 uint8_t opp_inst; 225 uint8_t otg_inst; 226 uint8_t digfe_inst; 227 uint8_t digbe_inst; 228 uint8_t dpphy_inst; 229 uint8_t aux_inst; 230 uint8_t hyst_frames; 231 uint8_t hyst_lines; 232 uint8_t phy_num; 233 uint8_t phy_type; 234 uint8_t aux_repeat; 235 uint8_t smu_optimizations_en; 236 uint8_t skip_wait_for_pll_lock; 237 uint8_t frame_delay; 238 uint8_t smu_phy_id; 239 uint8_t num_of_controllers; 240 uint8_t link_rate; 241 uint8_t frame_cap_ind; 242 }; 243 244 struct dmub_rb_cmd_psr_copy_settings { 245 struct dmub_cmd_header header; 246 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 247 }; 248 249 struct dmub_cmd_psr_set_level_data { 250 uint16_t psr_level; 251 }; 252 253 struct dmub_rb_cmd_psr_set_level { 254 struct dmub_cmd_header header; 255 struct dmub_cmd_psr_set_level_data psr_set_level_data; 256 }; 257 258 struct dmub_rb_cmd_psr_enable { 259 struct dmub_cmd_header header; 260 }; 261 262 struct dmub_cmd_psr_setup_data { 263 enum psr_version version; // PSR version 1 or 2 264 }; 265 266 struct dmub_rb_cmd_psr_setup { 267 struct dmub_cmd_header header; 268 struct dmub_cmd_psr_setup_data psr_setup_data; 269 }; 270 271 union dmub_rb_cmd { 272 struct dmub_rb_cmd_read_modify_write read_modify_write; 273 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 274 struct dmub_rb_cmd_burst_write burst_write; 275 struct dmub_rb_cmd_reg_wait reg_wait; 276 struct dmub_rb_cmd_common cmd_common; 277 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 278 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 279 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 280 struct dmub_rb_cmd_dpphy_init dpphy_init; 281 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 282 struct dmub_rb_cmd_psr_enable psr_enable; 283 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 284 struct dmub_rb_cmd_psr_set_level psr_set_level; 285 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 286 struct dmub_rb_cmd_psr_setup psr_setup; 287 }; 288 289 #pragma pack(pop) 290 291 #endif /* _DMUB_CMD_H_ */ 292