1 /* $NetBSD: amdgpu_dmub_dcn20.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */
2
3 /*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dmub_dcn20.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $");
30
31 #include "../inc/dmub_srv.h"
32 #include "dmub_reg.h"
33 #include "dmub_dcn20.h"
34
35 #include "dcn/dcn_2_0_0_offset.h"
36 #include "dcn/dcn_2_0_0_sh_mask.h"
37 #include "soc15_hw_ip.h"
38 #include "vega10_ip_offset.h"
39
40 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
41 #define CTX dmub
42 #define REGS dmub->regs
43
44 /* Registers. */
45
46 const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
47 #define DMUB_SR(reg) REG_OFFSET(reg),
48 { DMUB_COMMON_REGS() },
49 #undef DMUB_SR
50
51 #define DMUB_SF(reg, field) FD_MASK(reg, field),
52 { DMUB_COMMON_FIELDS() },
53 #undef DMUB_SF
54
55 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
56 { DMUB_COMMON_FIELDS() },
57 #undef DMUB_SF
58 };
59
60 /* Shared functions. */
61
dmub_dcn20_get_fb_base_offset(struct dmub_srv * dmub,uint64_t * fb_base,uint64_t * fb_offset)62 static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
63 uint64_t *fb_base,
64 uint64_t *fb_offset)
65 {
66 uint32_t tmp;
67
68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
69 *fb_base = (uint64_t)tmp << 24;
70
71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
72 *fb_offset = (uint64_t)tmp << 24;
73 }
74
dmub_dcn20_translate_addr(const union dmub_addr * addr_in,uint64_t fb_base,uint64_t fb_offset,union dmub_addr * addr_out)75 static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
76 uint64_t fb_base,
77 uint64_t fb_offset,
78 union dmub_addr *addr_out)
79 {
80 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
81 }
82
dmub_dcn20_reset(struct dmub_srv * dmub)83 void dmub_dcn20_reset(struct dmub_srv *dmub)
84 {
85 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 1);
86 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
87 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
88 REG_WRITE(DMCUB_INBOX1_RPTR, 0);
89 REG_WRITE(DMCUB_INBOX1_WPTR, 0);
90 }
91
dmub_dcn20_reset_release(struct dmub_srv * dmub)92 void dmub_dcn20_reset_release(struct dmub_srv *dmub)
93 {
94 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
95 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
96 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
97 REG_UPDATE(DMCUB_CNTL, DMCUB_SOFT_RESET, 0);
98 }
99
dmub_dcn20_backdoor_load(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)100 void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
101 const struct dmub_window *cw0,
102 const struct dmub_window *cw1)
103 {
104 union dmub_addr offset;
105 uint64_t fb_base, fb_offset;
106
107 dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
108
109 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
110 REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
111 DMCUB_MEM_WRITE_SPACE, 0x3);
112
113 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
114
115 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
116 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
117 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
118 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
119 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
120 DMCUB_REGION3_CW0_ENABLE, 1);
121
122 dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
123
124 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
125 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
126 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
127 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
128 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
129 DMCUB_REGION3_CW1_ENABLE, 1);
130
131 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
132 0x20);
133 }
134
dmub_dcn20_setup_windows(struct dmub_srv * dmub,const struct dmub_window * cw2,const struct dmub_window * cw3,const struct dmub_window * cw4,const struct dmub_window * cw5,const struct dmub_window * cw6)135 void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
136 const struct dmub_window *cw2,
137 const struct dmub_window *cw3,
138 const struct dmub_window *cw4,
139 const struct dmub_window *cw5,
140 const struct dmub_window *cw6)
141 {
142 union dmub_addr offset;
143 uint64_t fb_base, fb_offset;
144
145 dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
146
147 dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
148
149 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part);
150 REG_WRITE(DMCUB_REGION3_CW2_OFFSET_HIGH, offset.u.high_part);
151 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base);
152 REG_SET_2(DMCUB_REGION3_CW2_TOP_ADDRESS, 0,
153 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top,
154 DMCUB_REGION3_CW2_ENABLE, 1);
155
156 dmub_dcn20_translate_addr(&cw3->offset, fb_base, fb_offset, &offset);
157
158 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
159 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
160 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
161 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
162 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
163 DMCUB_REGION3_CW3_ENABLE, 1);
164
165 /* TODO: Move this to CW4. */
166 dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset);
167
168 REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part);
169 REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part);
170 REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS,
171 cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE,
172 1);
173
174 dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset);
175
176 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
177 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
178 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
179 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
180 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
181 DMCUB_REGION3_CW5_ENABLE, 1);
182
183 dmub_dcn20_translate_addr(&cw6->offset, fb_base, fb_offset, &offset);
184
185 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
186 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
187 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
188 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
189 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
190 DMCUB_REGION3_CW6_ENABLE, 1);
191 }
192
dmub_dcn20_setup_mailbox(struct dmub_srv * dmub,const struct dmub_region * inbox1)193 void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,
194 const struct dmub_region *inbox1)
195 {
196 /* TODO: Use CW4 instead of region 4. */
197
198 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000);
199 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
200 }
201
dmub_dcn20_get_inbox1_rptr(struct dmub_srv * dmub)202 uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)
203 {
204 return REG_READ(DMCUB_INBOX1_RPTR);
205 }
206
dmub_dcn20_set_inbox1_wptr(struct dmub_srv * dmub,uint32_t wptr_offset)207 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
208 {
209 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
210 }
211
dmub_dcn20_is_hw_init(struct dmub_srv * dmub)212 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
213 {
214 return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0;
215 }
216
dmub_dcn20_is_supported(struct dmub_srv * dmub)217 bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
218 {
219 uint32_t supported = 0;
220
221 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
222
223 return supported;
224 }
225