1 /* $NetBSD: if_vr.c,v 1.138 2024/06/29 12:11:12 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Copyright (c) 1997, 1998
35 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 * 3. All advertising materials mentioning features or use of this software
46 * must display the following acknowledgement:
47 * This product includes software developed by Bill Paul.
48 * 4. Neither the name of the author nor the names of any co-contributors
49 * may be used to endorse or promote products derived from this software
50 * without specific prior written permission.
51 *
52 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
55 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
62 * THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 * $FreeBSD: if_vr.c,v 1.7 1999/01/10 18:51:49 wpaul Exp $
65 */
66
67 /*
68 * VIA Rhine fast ethernet PCI NIC driver
69 *
70 * Supports various network adapters based on the VIA Rhine
71 * and Rhine II PCI controllers, including the D-Link DFE530TX.
72 * Datasheets are available at http://www.via.com.tw.
73 *
74 * Written by Bill Paul <wpaul@ctr.columbia.edu>
75 * Electrical Engineering Department
76 * Columbia University, New York City
77 */
78
79 /*
80 * The VIA Rhine controllers are similar in some respects to the
81 * the DEC tulip chips, except less complicated. The controller
82 * uses an MII bus and an external physical layer interface. The
83 * receiver has a one entry perfect filter and a 64-bit hash table
84 * multicast filter. Transmit and receive descriptors are similar
85 * to the tulip.
86 *
87 * The Rhine has a serious flaw in its transmit DMA mechanism:
88 * transmit buffers must be longword aligned. Unfortunately,
89 * the kernel doesn't guarantee that mbufs will be filled in starting
90 * at longword boundaries, so we have to do a buffer copy before
91 * transmission.
92 *
93 * Apparently, the receive DMA mechanism also has the same flaw. This
94 * means that on systems with struct alignment requirements, incoming
95 * frames must be copied to a new buffer which shifts the data forward
96 * 2 bytes so that the payload is aligned on a 4-byte boundary.
97 */
98
99 #include <sys/cdefs.h>
100 __KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.138 2024/06/29 12:11:12 riastradh Exp $");
101
102
103
104 #include <sys/param.h>
105 #include <sys/systm.h>
106 #include <sys/callout.h>
107 #include <sys/sockio.h>
108 #include <sys/mbuf.h>
109 #include <sys/kernel.h>
110 #include <sys/socket.h>
111 #include <sys/device.h>
112
113 #include <sys/rndsource.h>
114
115 #include <net/if.h>
116 #include <net/if_arp.h>
117 #include <net/if_dl.h>
118 #include <net/if_media.h>
119 #include <net/if_ether.h>
120
121 #include <net/bpf.h>
122
123 #include <sys/bus.h>
124 #include <sys/intr.h>
125 #include <machine/endian.h>
126
127 #include <dev/mii/mii.h>
128 #include <dev/mii/miivar.h>
129 #include <dev/mii/mii_bitbang.h>
130
131 #include <dev/pci/pcireg.h>
132 #include <dev/pci/pcivar.h>
133 #include <dev/pci/pcidevs.h>
134
135 #include <dev/pci/if_vrreg.h>
136
137 #define VR_USEIOSPACE
138
139 /*
140 * Various supported device vendors/types and their names.
141 */
142 static const struct device_compatible_entry compat_data[] = {
143 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH,
144 PCI_PRODUCT_VIATECH_VT3043) },
145
146 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH,
147 PCI_PRODUCT_VIATECH_VT6102) },
148
149 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH,
150 PCI_PRODUCT_VIATECH_VT6105) },
151
152 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH,
153 PCI_PRODUCT_VIATECH_VT6105M) },
154
155 { .id = PCI_ID_CODE(PCI_VENDOR_VIATECH,
156 PCI_PRODUCT_VIATECH_VT86C100A) },
157
158 PCI_COMPAT_EOL
159 };
160
161 /*
162 * Transmit descriptor list size.
163 */
164 #define VR_NTXDESC 64
165 #define VR_NTXDESC_MASK (VR_NTXDESC - 1)
166 #define VR_NEXTTX(x) (((x) + 1) & VR_NTXDESC_MASK)
167
168 /*
169 * Receive descriptor list size.
170 */
171 #define VR_NRXDESC 64
172 #define VR_NRXDESC_MASK (VR_NRXDESC - 1)
173 #define VR_NEXTRX(x) (((x) + 1) & VR_NRXDESC_MASK)
174
175 /*
176 * Control data structures that are DMA'd to the Rhine chip. We allocate
177 * them in a single clump that maps to a single DMA segment to make several
178 * things easier.
179 *
180 * Note that since we always copy outgoing packets to aligned transmit
181 * buffers, we can reduce the transmit descriptors to one per packet.
182 */
183 struct vr_control_data {
184 struct vr_desc vr_txdescs[VR_NTXDESC];
185 struct vr_desc vr_rxdescs[VR_NRXDESC];
186 };
187
188 #define VR_CDOFF(x) offsetof(struct vr_control_data, x)
189 #define VR_CDTXOFF(x) VR_CDOFF(vr_txdescs[(x)])
190 #define VR_CDRXOFF(x) VR_CDOFF(vr_rxdescs[(x)])
191
192 /*
193 * Software state of transmit and receive descriptors.
194 */
195 struct vr_descsoft {
196 struct mbuf *ds_mbuf; /* head of mbuf chain */
197 bus_dmamap_t ds_dmamap; /* our DMA map */
198 };
199
200 struct vr_softc {
201 device_t vr_dev;
202 void *vr_ih; /* interrupt cookie */
203 bus_space_tag_t vr_bst; /* bus space tag */
204 bus_space_handle_t vr_bsh; /* bus space handle */
205 bus_dma_tag_t vr_dmat; /* bus DMA tag */
206 pci_chipset_tag_t vr_pc; /* PCI chipset info */
207 pcitag_t vr_tag; /* PCI tag */
208 struct ethercom vr_ec; /* Ethernet common info */
209 uint8_t vr_enaddr[ETHER_ADDR_LEN];
210 struct mii_data vr_mii; /* MII/media info */
211
212 pcireg_t vr_id; /* vendor/product ID */
213 uint8_t vr_revid; /* Rhine chip revision */
214
215 callout_t vr_tick_ch; /* tick callout */
216
217 bus_dmamap_t vr_cddmamap; /* control data DMA map */
218 #define vr_cddma vr_cddmamap->dm_segs[0].ds_addr
219
220 /*
221 * Software state for transmit and receive descriptors.
222 */
223 struct vr_descsoft vr_txsoft[VR_NTXDESC];
224 struct vr_descsoft vr_rxsoft[VR_NRXDESC];
225
226 /*
227 * Control data structures.
228 */
229 struct vr_control_data *vr_control_data;
230
231 int vr_txpending; /* number of TX requests pending */
232 int vr_txdirty; /* first dirty TX descriptor */
233 int vr_txlast; /* last used TX descriptor */
234
235 int vr_rxptr; /* next ready RX descriptor */
236
237 uint32_t vr_save_iobase;
238 uint32_t vr_save_membase;
239 uint32_t vr_save_irq;
240
241 bool vr_link;
242 int vr_flags;
243 #define VR_F_RESTART 0x1 /* restart on next tick */
244 u_short vr_if_flags;
245
246 krndsource_t rnd_source; /* random source */
247 };
248
249 #define VR_CDTXADDR(sc, x) ((sc)->vr_cddma + VR_CDTXOFF((x)))
250 #define VR_CDRXADDR(sc, x) ((sc)->vr_cddma + VR_CDRXOFF((x)))
251
252 #define VR_CDTX(sc, x) (&(sc)->vr_control_data->vr_txdescs[(x)])
253 #define VR_CDRX(sc, x) (&(sc)->vr_control_data->vr_rxdescs[(x)])
254
255 #define VR_DSTX(sc, x) (&(sc)->vr_txsoft[(x)])
256 #define VR_DSRX(sc, x) (&(sc)->vr_rxsoft[(x)])
257
258 #define VR_CDTXSYNC(sc, x, ops) \
259 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \
260 VR_CDTXOFF((x)), sizeof(struct vr_desc), (ops))
261
262 #define VR_CDRXSYNC(sc, x, ops) \
263 bus_dmamap_sync((sc)->vr_dmat, (sc)->vr_cddmamap, \
264 VR_CDRXOFF((x)), sizeof(struct vr_desc), (ops))
265
266 /*
267 * Note we rely on MCLBYTES being a power of two below.
268 */
269 #define VR_INIT_RXDESC(sc, i) \
270 do { \
271 struct vr_desc *__d = VR_CDRX((sc), (i)); \
272 struct vr_descsoft *__ds = VR_DSRX((sc), (i)); \
273 \
274 __d->vr_next = htole32(VR_CDRXADDR((sc), VR_NEXTRX((i)))); \
275 __d->vr_data = htole32(__ds->ds_dmamap->dm_segs[0].ds_addr); \
276 __d->vr_ctl = htole32(VR_RXCTL_CHAIN | VR_RXCTL_RX_INTR | \
277 ((MCLBYTES - 1) & VR_RXCTL_BUFLEN)); \
278 __d->vr_status = htole32(VR_RXSTAT_FIRSTFRAG | \
279 VR_RXSTAT_LASTFRAG | VR_RXSTAT_OWN); \
280 VR_CDRXSYNC((sc), (i), BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); \
281 } while (/* CONSTCOND */ 0)
282
283 /*
284 * register space access macros
285 */
286 #define CSR_WRITE_4(sc, reg, val) \
287 bus_space_write_4(sc->vr_bst, sc->vr_bsh, reg, val)
288 #define CSR_WRITE_2(sc, reg, val) \
289 bus_space_write_2(sc->vr_bst, sc->vr_bsh, reg, val)
290 #define CSR_WRITE_1(sc, reg, val) \
291 bus_space_write_1(sc->vr_bst, sc->vr_bsh, reg, val)
292
293 #define CSR_READ_4(sc, reg) \
294 bus_space_read_4(sc->vr_bst, sc->vr_bsh, reg)
295 #define CSR_READ_2(sc, reg) \
296 bus_space_read_2(sc->vr_bst, sc->vr_bsh, reg)
297 #define CSR_READ_1(sc, reg) \
298 bus_space_read_1(sc->vr_bst, sc->vr_bsh, reg)
299
300 #define VR_TIMEOUT 1000
301
302 static int vr_add_rxbuf(struct vr_softc *, int);
303
304 static void vr_rxeof(struct vr_softc *);
305 static void vr_rxeoc(struct vr_softc *);
306 static void vr_txeof(struct vr_softc *);
307 static int vr_intr(void *);
308 static void vr_start(struct ifnet *);
309 static int vr_ioctl(struct ifnet *, u_long, void *);
310 static int vr_init(struct ifnet *);
311 static void vr_stop(struct ifnet *, int);
312 static void vr_rxdrain(struct vr_softc *);
313 static void vr_watchdog(struct ifnet *);
314 static void vr_tick(void *);
315
316 static int vr_mii_readreg(device_t, int, int, uint16_t *);
317 static int vr_mii_writereg(device_t, int, int, uint16_t);
318 static void vr_mii_statchg(struct ifnet *);
319
320 static void vr_setmulti(struct vr_softc *);
321 static void vr_reset(struct vr_softc *);
322 static int vr_restore_state(pci_chipset_tag_t, pcitag_t, device_t,
323 pcireg_t);
324 static bool vr_resume(device_t, const pmf_qual_t *);
325
326 int vr_copy_small = 0;
327
328 #define VR_SETBIT(sc, reg, x) \
329 CSR_WRITE_1(sc, reg, \
330 CSR_READ_1(sc, reg) | (x))
331
332 #define VR_CLRBIT(sc, reg, x) \
333 CSR_WRITE_1(sc, reg, \
334 CSR_READ_1(sc, reg) & ~(x))
335
336 #define VR_SETBIT16(sc, reg, x) \
337 CSR_WRITE_2(sc, reg, \
338 CSR_READ_2(sc, reg) | (x))
339
340 #define VR_CLRBIT16(sc, reg, x) \
341 CSR_WRITE_2(sc, reg, \
342 CSR_READ_2(sc, reg) & ~(x))
343
344 #define VR_SETBIT32(sc, reg, x) \
345 CSR_WRITE_4(sc, reg, \
346 CSR_READ_4(sc, reg) | (x))
347
348 #define VR_CLRBIT32(sc, reg, x) \
349 CSR_WRITE_4(sc, reg, \
350 CSR_READ_4(sc, reg) & ~(x))
351
352 /*
353 * MII bit-bang glue.
354 */
355 static uint32_t vr_mii_bitbang_read(device_t);
356 static void vr_mii_bitbang_write(device_t, uint32_t);
357
358 static const struct mii_bitbang_ops vr_mii_bitbang_ops = {
359 vr_mii_bitbang_read,
360 vr_mii_bitbang_write,
361 {
362 VR_MIICMD_DATAOUT, /* MII_BIT_MDO */
363 VR_MIICMD_DATAIN, /* MII_BIT_MDI */
364 VR_MIICMD_CLK, /* MII_BIT_MDC */
365 VR_MIICMD_DIR, /* MII_BIT_DIR_HOST_PHY */
366 0, /* MII_BIT_DIR_PHY_HOST */
367 }
368 };
369
370 static uint32_t
vr_mii_bitbang_read(device_t self)371 vr_mii_bitbang_read(device_t self)
372 {
373 struct vr_softc *sc = device_private(self);
374
375 return (CSR_READ_1(sc, VR_MIICMD));
376 }
377
378 static void
vr_mii_bitbang_write(device_t self,uint32_t val)379 vr_mii_bitbang_write(device_t self, uint32_t val)
380 {
381 struct vr_softc *sc = device_private(self);
382
383 CSR_WRITE_1(sc, VR_MIICMD, (val & 0xff) | VR_MIICMD_DIRECTPGM);
384 }
385
386 /*
387 * Read an PHY register through the MII.
388 */
389 static int
vr_mii_readreg(device_t self,int phy,int reg,uint16_t * val)390 vr_mii_readreg(device_t self, int phy, int reg, uint16_t *val)
391 {
392 struct vr_softc *sc = device_private(self);
393
394 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
395 return (mii_bitbang_readreg(self, &vr_mii_bitbang_ops, phy, reg, val));
396 }
397
398 /*
399 * Write to a PHY register through the MII.
400 */
401 static int
vr_mii_writereg(device_t self,int phy,int reg,uint16_t val)402 vr_mii_writereg(device_t self, int phy, int reg, uint16_t val)
403 {
404 struct vr_softc *sc = device_private(self);
405
406 CSR_WRITE_1(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
407 return mii_bitbang_writereg(self, &vr_mii_bitbang_ops, phy, reg, val);
408 }
409
410 static void
vr_mii_statchg(struct ifnet * ifp)411 vr_mii_statchg(struct ifnet *ifp)
412 {
413 struct vr_softc *sc = ifp->if_softc;
414 int i;
415
416 /*
417 * In order to fiddle with the 'full-duplex' bit in the netconfig
418 * register, we first have to put the transmit and/or receive logic
419 * in the idle state.
420 */
421 if ((sc->vr_mii.mii_media_status & IFM_ACTIVE) &&
422 IFM_SUBTYPE(sc->vr_mii.mii_media_active) != IFM_NONE) {
423 sc->vr_link = true;
424
425 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON | VR_CMD_RX_ON))
426 VR_CLRBIT16(sc, VR_COMMAND,
427 (VR_CMD_TX_ON | VR_CMD_RX_ON));
428
429 if (sc->vr_mii.mii_media_active & IFM_FDX)
430 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
431 else
432 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
433
434 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON | VR_CMD_RX_ON);
435 } else {
436 sc->vr_link = false;
437 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON | VR_CMD_RX_ON);
438 for (i = VR_TIMEOUT; i > 0; i--) {
439 delay(10);
440 if (!(CSR_READ_2(sc, VR_COMMAND) &
441 (VR_CMD_TX_ON | VR_CMD_RX_ON)))
442 break;
443 }
444 if (i == 0) {
445 #ifdef VR_DEBUG
446 aprint_error_dev(sc->vr_dev, "rx shutdown error!\n");
447 #endif
448 sc->vr_flags |= VR_F_RESTART;
449 }
450 }
451 }
452
453 #define vr_calchash(addr) \
454 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
455
456 /*
457 * Program the 64-bit multicast hash filter.
458 */
459 static void
vr_setmulti(struct vr_softc * sc)460 vr_setmulti(struct vr_softc *sc)
461 {
462 struct ethercom *ec = &sc->vr_ec;
463 struct ifnet *ifp = &ec->ec_if;
464 int h = 0;
465 uint32_t hashes[2] = { 0, 0 };
466 struct ether_multistep step;
467 struct ether_multi *enm;
468 int mcnt = 0;
469 uint8_t rxfilt;
470
471 rxfilt = CSR_READ_1(sc, VR_RXCFG);
472
473 if (ifp->if_flags & IFF_PROMISC) {
474 allmulti:
475 ifp->if_flags |= IFF_ALLMULTI;
476 rxfilt |= VR_RXCFG_RX_MULTI;
477 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
478 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
479 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
480 return;
481 }
482
483 /* first, zot all the existing hash bits */
484 CSR_WRITE_4(sc, VR_MAR0, 0);
485 CSR_WRITE_4(sc, VR_MAR1, 0);
486
487 /* now program new ones */
488 ETHER_LOCK(ec);
489 ETHER_FIRST_MULTI(step, ec, enm);
490 while (enm != NULL) {
491 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
492 ETHER_ADDR_LEN) != 0) {
493 ETHER_UNLOCK(ec);
494 goto allmulti;
495 }
496
497 h = vr_calchash(enm->enm_addrlo);
498
499 if (h < 32)
500 hashes[0] |= (1 << h);
501 else
502 hashes[1] |= (1 << (h - 32));
503 ETHER_NEXT_MULTI(step, enm);
504 mcnt++;
505 }
506 ETHER_UNLOCK(ec);
507
508 ifp->if_flags &= ~IFF_ALLMULTI;
509
510 if (mcnt)
511 rxfilt |= VR_RXCFG_RX_MULTI;
512 else
513 rxfilt &= ~VR_RXCFG_RX_MULTI;
514
515 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
516 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
517 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
518 }
519
520 static void
vr_reset(struct vr_softc * sc)521 vr_reset(struct vr_softc *sc)
522 {
523 int i;
524
525 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
526
527 for (i = 0; i < VR_TIMEOUT; i++) {
528 DELAY(10);
529 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
530 break;
531 }
532 if (i == VR_TIMEOUT) {
533 if (sc->vr_revid < REV_ID_VT3065_A) {
534 aprint_error_dev(sc->vr_dev,
535 "reset never completed!\n");
536 } else {
537 /* Use newer force reset command */
538 aprint_normal_dev(sc->vr_dev,
539 "using force reset command.\n");
540 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
541 }
542 }
543
544 /* Wait a little while for the chip to get its brains in order. */
545 DELAY(1000);
546 }
547
548 /*
549 * Initialize an RX descriptor and attach an MBUF cluster.
550 * Note: the length fields are only 11 bits wide, which means the
551 * largest size we can specify is 2047. This is important because
552 * MCLBYTES is 2048, so we have to subtract one otherwise we'll
553 * overflow the field and make a mess.
554 */
555 static int
vr_add_rxbuf(struct vr_softc * sc,int i)556 vr_add_rxbuf(struct vr_softc *sc, int i)
557 {
558 struct vr_descsoft *ds = VR_DSRX(sc, i);
559 struct mbuf *m_new;
560 int error;
561
562 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
563 if (m_new == NULL)
564 return (ENOBUFS);
565
566 MCLGET(m_new, M_DONTWAIT);
567 if ((m_new->m_flags & M_EXT) == 0) {
568 m_freem(m_new);
569 return (ENOBUFS);
570 }
571
572 if (ds->ds_mbuf != NULL)
573 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap);
574
575 ds->ds_mbuf = m_new;
576
577 error = bus_dmamap_load(sc->vr_dmat, ds->ds_dmamap,
578 m_new->m_ext.ext_buf, m_new->m_ext.ext_size, NULL,
579 BUS_DMA_READ | BUS_DMA_NOWAIT);
580 if (error) {
581 aprint_error_dev(sc->vr_dev,
582 "unable to load rx DMA map %d, error = %d\n", i, error);
583 panic("vr_add_rxbuf"); /* XXX */
584 }
585
586 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
587 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
588
589 VR_INIT_RXDESC(sc, i);
590
591 return (0);
592 }
593
594 /*
595 * A frame has been uploaded: pass the resulting mbuf chain up to
596 * the higher level protocols.
597 */
598 static void
vr_rxeof(struct vr_softc * sc)599 vr_rxeof(struct vr_softc *sc)
600 {
601 struct mbuf *m;
602 struct ifnet *ifp;
603 struct vr_desc *d;
604 struct vr_descsoft *ds;
605 int i, total_len;
606 uint32_t rxstat;
607
608 ifp = &sc->vr_ec.ec_if;
609
610 for (i = sc->vr_rxptr;; i = VR_NEXTRX(i)) {
611 d = VR_CDRX(sc, i);
612 ds = VR_DSRX(sc, i);
613
614 VR_CDRXSYNC(sc, i,
615 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
616
617 rxstat = le32toh(d->vr_status);
618
619 if (rxstat & VR_RXSTAT_OWN) {
620 /*
621 * We have processed all of the receive buffers.
622 */
623 break;
624 }
625
626 /*
627 * If an error occurs, update stats, clear the
628 * status word and leave the mbuf cluster in place:
629 * it should simply get re-used next time this descriptor
630 * comes up in the ring.
631 */
632 if (rxstat & VR_RXSTAT_RXERR) {
633 const char *errstr;
634
635 if_statinc(ifp, if_ierrors);
636 switch (rxstat & 0x000000FF) {
637 case VR_RXSTAT_CRCERR:
638 errstr = "crc error";
639 break;
640 case VR_RXSTAT_FRAMEALIGNERR:
641 errstr = "frame alignment error";
642 break;
643 case VR_RXSTAT_FIFOOFLOW:
644 errstr = "FIFO overflow";
645 break;
646 case VR_RXSTAT_GIANT:
647 errstr = "received giant packet";
648 break;
649 case VR_RXSTAT_RUNT:
650 errstr = "received runt packet";
651 break;
652 case VR_RXSTAT_BUSERR:
653 errstr = "system bus error";
654 break;
655 case VR_RXSTAT_BUFFERR:
656 errstr = "rx buffer error";
657 break;
658 default:
659 errstr = "unknown rx error";
660 break;
661 }
662 aprint_error_dev(sc->vr_dev, "receive error: %s\n",
663 errstr);
664
665 VR_INIT_RXDESC(sc, i);
666
667 continue;
668 } else if (!(rxstat & VR_RXSTAT_FIRSTFRAG) ||
669 !(rxstat & VR_RXSTAT_LASTFRAG)) {
670 /*
671 * This driver expects to receive whole packets every
672 * time. In case we receive a fragment that is not
673 * a complete packet, we discard it.
674 */
675 if_statinc(ifp, if_ierrors);
676
677 aprint_error_dev(sc->vr_dev,
678 "receive error: incomplete frame; "
679 "size = %d, status = 0x%x\n",
680 VR_RXBYTES(le32toh(d->vr_status)), rxstat);
681
682 VR_INIT_RXDESC(sc, i);
683
684 continue;
685 }
686
687 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
688 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
689
690 /* No errors; receive the packet. */
691 total_len = VR_RXBYTES(le32toh(d->vr_status));
692 #ifdef DIAGNOSTIC
693 if (total_len == 0) {
694 /*
695 * If we receive a zero-length packet, we probably
696 * missed to handle an error condition above.
697 * Discard it to avoid a later crash.
698 */
699 if_statinc(ifp, if_ierrors);
700
701 aprint_error_dev(sc->vr_dev,
702 "receive error: zero-length packet; "
703 "status = 0x%x\n", rxstat);
704
705 VR_INIT_RXDESC(sc, i);
706
707 continue;
708 }
709 #endif
710
711 /*
712 * The Rhine chip includes the CRC with every packet.
713 * Trim it off here.
714 */
715 total_len -= ETHER_CRC_LEN;
716
717 #ifdef __NO_STRICT_ALIGNMENT
718 /*
719 * If the packet is small enough to fit in a
720 * single header mbuf, allocate one and copy
721 * the data into it. This greatly reduces
722 * memory consumption when we receive lots
723 * of small packets.
724 *
725 * Otherwise, we add a new buffer to the receive
726 * chain. If this fails, we drop the packet and
727 * recycle the old buffer.
728 */
729 if (vr_copy_small != 0 && total_len <= MHLEN) {
730 MGETHDR(m, M_DONTWAIT, MT_DATA);
731 if (m == NULL)
732 goto dropit;
733 memcpy(mtod(m, void *),
734 mtod(ds->ds_mbuf, void *), total_len);
735 VR_INIT_RXDESC(sc, i);
736 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
737 ds->ds_dmamap->dm_mapsize,
738 BUS_DMASYNC_PREREAD);
739 } else {
740 m = ds->ds_mbuf;
741 if (vr_add_rxbuf(sc, i) == ENOBUFS) {
742 dropit:
743 if_statinc(ifp, if_ierrors);
744 VR_INIT_RXDESC(sc, i);
745 bus_dmamap_sync(sc->vr_dmat,
746 ds->ds_dmamap, 0,
747 ds->ds_dmamap->dm_mapsize,
748 BUS_DMASYNC_PREREAD);
749 continue;
750 }
751 }
752 #else
753 /*
754 * The Rhine's packet buffers must be 4-byte aligned.
755 * But this means that the data after the Ethernet header
756 * is misaligned. We must allocate a new buffer and
757 * copy the data, shifted forward 2 bytes.
758 */
759 MGETHDR(m, M_DONTWAIT, MT_DATA);
760 if (m == NULL) {
761 dropit:
762 if_statinc(ifp, if_ierrors);
763 VR_INIT_RXDESC(sc, i);
764 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
765 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
766 continue;
767 }
768 if (total_len > (MHLEN - 2)) {
769 MCLGET(m, M_DONTWAIT);
770 if ((m->m_flags & M_EXT) == 0) {
771 m_freem(m);
772 goto dropit;
773 }
774 }
775 m->m_data += 2;
776
777 /*
778 * Note that we use clusters for incoming frames, so the
779 * buffer is virtually contiguous.
780 */
781 memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *),
782 total_len);
783
784 /* Allow the receive descriptor to continue using its mbuf. */
785 VR_INIT_RXDESC(sc, i);
786 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
787 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
788 #endif /* __NO_STRICT_ALIGNMENT */
789
790 m_set_rcvif(m, ifp);
791 m->m_pkthdr.len = m->m_len = total_len;
792 /* Pass it on. */
793 if_percpuq_enqueue(ifp->if_percpuq, m);
794 }
795
796 /* Update the receive pointer. */
797 sc->vr_rxptr = i;
798 }
799
800 void
vr_rxeoc(struct vr_softc * sc)801 vr_rxeoc(struct vr_softc *sc)
802 {
803 struct ifnet *ifp;
804 int i;
805
806 ifp = &sc->vr_ec.ec_if;
807
808 if_statinc(ifp, if_ierrors);
809
810 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
811 for (i = 0; i < VR_TIMEOUT; i++) {
812 DELAY(10);
813 if ((CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON) == 0)
814 break;
815 }
816 if (i == VR_TIMEOUT) {
817 /* XXX need reset? */
818 aprint_error_dev(sc->vr_dev, "RX shutdown never completed\n");
819 }
820
821 vr_rxeof(sc);
822
823 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr));
824 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
825 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
826 }
827
828 /*
829 * A frame was downloaded to the chip. It's safe for us to clean up
830 * the list buffers.
831 */
832 static void
vr_txeof(struct vr_softc * sc)833 vr_txeof(struct vr_softc *sc)
834 {
835 struct ifnet *ifp = &sc->vr_ec.ec_if;
836 struct vr_desc *d;
837 struct vr_descsoft *ds;
838 uint32_t txstat;
839 int i, j;
840
841 /*
842 * Go through our tx list and free mbufs for those
843 * frames that have been transmitted.
844 */
845 for (i = sc->vr_txdirty; sc->vr_txpending != 0;
846 i = VR_NEXTTX(i), sc->vr_txpending--) {
847 d = VR_CDTX(sc, i);
848 ds = VR_DSTX(sc, i);
849
850 VR_CDTXSYNC(sc, i,
851 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
852
853 txstat = le32toh(d->vr_status);
854
855 if (txstat & (VR_TXSTAT_ABRT | VR_TXSTAT_UDF)) {
856 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
857 for (j = 0; j < VR_TIMEOUT; j++) {
858 DELAY(10);
859 if ((CSR_READ_2(sc, VR_COMMAND) &
860 VR_CMD_TX_ON) == 0)
861 break;
862 }
863 if (j == VR_TIMEOUT) {
864 /* XXX need reset? */
865 aprint_error_dev(sc->vr_dev,
866 "TX shutdown never completed\n");
867 }
868 d->vr_status = htole32(VR_TXSTAT_OWN);
869 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, i));
870 break;
871 }
872
873 if (txstat & VR_TXSTAT_OWN)
874 break;
875
876 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap,
877 0, ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
878 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap);
879 m_freem(ds->ds_mbuf);
880 ds->ds_mbuf = NULL;
881
882 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
883 if (txstat & VR_TXSTAT_ERRSUM) {
884 if_statinc_ref(ifp, nsr, if_oerrors);
885 if (txstat & VR_TXSTAT_DEFER)
886 if_statinc_ref(ifp, nsr, if_collisions);
887 if (txstat & VR_TXSTAT_LATECOLL)
888 if_statinc_ref(ifp, nsr, if_collisions);
889 }
890
891 if_statadd_ref(ifp, nsr, if_collisions,
892 (txstat & VR_TXSTAT_COLLCNT) >> 3);
893 if_statinc_ref(ifp, nsr, if_opackets);
894 IF_STAT_PUTREF(ifp);
895 }
896
897 /* Update the dirty transmit buffer pointer. */
898 sc->vr_txdirty = i;
899
900 /*
901 * Cancel the watchdog timer if there are no pending
902 * transmissions.
903 */
904 if (sc->vr_txpending == 0)
905 ifp->if_timer = 0;
906 }
907
908 static int
vr_intr(void * arg)909 vr_intr(void *arg)
910 {
911 struct vr_softc *sc;
912 struct ifnet *ifp;
913 uint16_t status;
914 int handled = 0, dotx = 0;
915
916 sc = arg;
917 ifp = &sc->vr_ec.ec_if;
918
919 /* Suppress unwanted interrupts. */
920 if ((ifp->if_flags & IFF_UP) == 0) {
921 vr_stop(ifp, 1);
922 return (0);
923 }
924
925 /* Disable interrupts. */
926 CSR_WRITE_2(sc, VR_IMR, 0x0000);
927
928 for (;;) {
929 status = CSR_READ_2(sc, VR_ISR);
930 if (status)
931 CSR_WRITE_2(sc, VR_ISR, status);
932
933 if ((status & VR_INTRS) == 0)
934 break;
935
936 handled = 1;
937
938 rnd_add_uint32(&sc->rnd_source, status);
939
940 if (status & VR_ISR_RX_OK)
941 vr_rxeof(sc);
942
943 if (status & VR_ISR_RX_DROPPED) {
944 aprint_error_dev(sc->vr_dev, "rx packet lost\n");
945 if_statinc(ifp, if_ierrors);
946 }
947
948 if (status &
949 (VR_ISR_RX_ERR | VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW))
950 vr_rxeoc(sc);
951
952
953 if (status & (VR_ISR_BUSERR | VR_ISR_TX_UNDERRUN)) {
954 if (status & VR_ISR_BUSERR)
955 aprint_error_dev(sc->vr_dev, "PCI bus error\n");
956 if (status & VR_ISR_TX_UNDERRUN)
957 aprint_error_dev(sc->vr_dev,
958 "transmit underrun\n");
959 /* vr_init() calls vr_start() */
960 dotx = 0;
961 (void)vr_init(ifp);
962
963 }
964
965 if (status & VR_ISR_TX_OK) {
966 dotx = 1;
967 vr_txeof(sc);
968 }
969
970 if (status &
971 (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2 | VR_ISR_TX_UDFI)) {
972 if (status & (VR_ISR_TX_ABRT | VR_ISR_TX_ABRT2))
973 aprint_error_dev(sc->vr_dev,
974 "transmit aborted\n");
975 if (status & VR_ISR_TX_UDFI)
976 aprint_error_dev(sc->vr_dev,
977 "transmit underflow\n");
978 if_statinc(ifp, if_oerrors);
979 dotx = 1;
980 vr_txeof(sc);
981 if (sc->vr_txpending) {
982 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON);
983 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
984 }
985 }
986 }
987
988 /* Re-enable interrupts. */
989 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
990
991 if (dotx)
992 if_schedule_deferred_start(ifp);
993
994 return (handled);
995 }
996
997 /*
998 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
999 * to the mbuf data regions directly in the transmit lists. We also save a
1000 * copy of the pointers since the transmit list fragment pointers are
1001 * physical addresses.
1002 */
1003 static void
vr_start(struct ifnet * ifp)1004 vr_start(struct ifnet *ifp)
1005 {
1006 struct vr_softc *sc = ifp->if_softc;
1007 struct mbuf *m0, *m;
1008 struct vr_desc *d;
1009 struct vr_descsoft *ds;
1010 int error, firsttx, nexttx, opending;
1011
1012 if ((ifp->if_flags & IFF_RUNNING) == 0)
1013 return;
1014 if (sc->vr_link == false)
1015 return;
1016
1017 /*
1018 * Remember the previous txpending and the first transmit
1019 * descriptor we use.
1020 */
1021 opending = sc->vr_txpending;
1022 firsttx = VR_NEXTTX(sc->vr_txlast);
1023
1024 /*
1025 * Loop through the send queue, setting up transmit descriptors
1026 * until we drain the queue, or use up all available transmit
1027 * descriptors.
1028 */
1029 while (sc->vr_txpending < VR_NTXDESC) {
1030 /*
1031 * Grab a packet off the queue.
1032 */
1033 IFQ_POLL(&ifp->if_snd, m0);
1034 if (m0 == NULL)
1035 break;
1036 m = NULL;
1037
1038 /*
1039 * Get the next available transmit descriptor.
1040 */
1041 nexttx = VR_NEXTTX(sc->vr_txlast);
1042 d = VR_CDTX(sc, nexttx);
1043 ds = VR_DSTX(sc, nexttx);
1044
1045 /*
1046 * Load the DMA map. If this fails, the packet didn't
1047 * fit in one DMA segment, and we need to copy. Note,
1048 * the packet must also be aligned.
1049 * if the packet is too small, copy it too, so we're sure
1050 * we have enough room for the pad buffer.
1051 */
1052 if ((mtod(m0, uintptr_t) & 3) != 0 ||
1053 m0->m_pkthdr.len < VR_MIN_FRAMELEN ||
1054 bus_dmamap_load_mbuf(sc->vr_dmat, ds->ds_dmamap, m0,
1055 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) {
1056 MGETHDR(m, M_DONTWAIT, MT_DATA);
1057 if (m == NULL) {
1058 aprint_error_dev(sc->vr_dev,
1059 "unable to allocate Tx mbuf\n");
1060 break;
1061 }
1062 if (m0->m_pkthdr.len > MHLEN) {
1063 MCLGET(m, M_DONTWAIT);
1064 if ((m->m_flags & M_EXT) == 0) {
1065 aprint_error_dev(sc->vr_dev,
1066 "unable to allocate Tx cluster\n");
1067 m_freem(m);
1068 break;
1069 }
1070 }
1071 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
1072 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
1073 /*
1074 * The Rhine doesn't auto-pad, so we have to do this
1075 * ourselves.
1076 */
1077 if (m0->m_pkthdr.len < VR_MIN_FRAMELEN) {
1078 memset(mtod(m, char *) + m0->m_pkthdr.len,
1079 0, VR_MIN_FRAMELEN - m0->m_pkthdr.len);
1080 m->m_pkthdr.len = m->m_len = VR_MIN_FRAMELEN;
1081 }
1082 error = bus_dmamap_load_mbuf(sc->vr_dmat,
1083 ds->ds_dmamap, m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
1084 if (error) {
1085 m_freem(m);
1086 aprint_error_dev(sc->vr_dev, "unable to load "
1087 "Tx buffer, error = %d\n", error);
1088 break;
1089 }
1090 }
1091
1092 IFQ_DEQUEUE(&ifp->if_snd, m0);
1093 if (m != NULL) {
1094 m_freem(m0);
1095 m0 = m;
1096 }
1097
1098 /* Sync the DMA map. */
1099 bus_dmamap_sync(sc->vr_dmat, ds->ds_dmamap, 0,
1100 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE);
1101
1102 /*
1103 * Store a pointer to the packet so we can free it later.
1104 */
1105 ds->ds_mbuf = m0;
1106
1107 /*
1108 * If there's a BPF listener, bounce a copy of this frame
1109 * to him.
1110 */
1111 bpf_mtap(ifp, m0, BPF_D_OUT);
1112
1113 /*
1114 * Fill in the transmit descriptor.
1115 */
1116 d->vr_data = htole32(ds->ds_dmamap->dm_segs[0].ds_addr);
1117 d->vr_ctl = htole32(m0->m_pkthdr.len);
1118 d->vr_ctl |= htole32(VR_TXCTL_FIRSTFRAG | VR_TXCTL_LASTFRAG);
1119
1120 /*
1121 * If this is the first descriptor we're enqueuing,
1122 * don't give it to the Rhine yet. That could cause
1123 * a race condition. We'll do it below.
1124 */
1125 if (nexttx == firsttx)
1126 d->vr_status = 0;
1127 else
1128 d->vr_status = htole32(VR_TXSTAT_OWN);
1129
1130 VR_CDTXSYNC(sc, nexttx,
1131 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1132
1133 /* Advance the tx pointer. */
1134 sc->vr_txpending++;
1135 sc->vr_txlast = nexttx;
1136 }
1137
1138 if (sc->vr_txpending != opending) {
1139 /*
1140 * We enqueued packets. If the transmitter was idle,
1141 * reset the txdirty pointer.
1142 */
1143 if (opending == 0)
1144 sc->vr_txdirty = firsttx;
1145
1146 /*
1147 * Cause a transmit interrupt to happen on the
1148 * last packet we enqueued.
1149 */
1150 VR_CDTX(sc, sc->vr_txlast)->vr_ctl |= htole32(VR_TXCTL_FINT);
1151 VR_CDTXSYNC(sc, sc->vr_txlast,
1152 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1153
1154 /*
1155 * The entire packet chain is set up. Give the
1156 * first descriptor to the Rhine now.
1157 */
1158 VR_CDTX(sc, firsttx)->vr_status = htole32(VR_TXSTAT_OWN);
1159 VR_CDTXSYNC(sc, firsttx,
1160 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1161
1162 /* Start the transmitter. */
1163 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO);
1164
1165 /* Set the watchdog timer in case the chip flakes out. */
1166 ifp->if_timer = 5;
1167 }
1168 }
1169
1170 /*
1171 * Initialize the interface. Must be called at splnet.
1172 */
1173 static int
vr_init(struct ifnet * ifp)1174 vr_init(struct ifnet *ifp)
1175 {
1176 struct vr_softc *sc = ifp->if_softc;
1177 struct vr_desc *d;
1178 struct vr_descsoft *ds;
1179 int i, error = 0;
1180
1181 /* Cancel pending I/O. */
1182 vr_stop(ifp, 0);
1183
1184 /* Reset the Rhine to a known state. */
1185 vr_reset(sc);
1186
1187 /* set DMA length in BCR0 and BCR1 */
1188 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1189 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1190
1191 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1192 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTH_128BYTES);
1193
1194 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1195 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTH_STORENFWD);
1196
1197 /* set DMA threshold length in RXCFG and TXCFG */
1198 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1199 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1200
1201 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1202 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1203
1204 /*
1205 * Initialize the transmit descriptor ring. txlast is initialized
1206 * to the end of the list so that it will wrap around to the first
1207 * descriptor when the first packet is transmitted.
1208 */
1209 for (i = 0; i < VR_NTXDESC; i++) {
1210 d = VR_CDTX(sc, i);
1211 memset(d, 0, sizeof(struct vr_desc));
1212 d->vr_next = htole32(VR_CDTXADDR(sc, VR_NEXTTX(i)));
1213 VR_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1214 }
1215 sc->vr_txpending = 0;
1216 sc->vr_txdirty = 0;
1217 sc->vr_txlast = VR_NTXDESC - 1;
1218
1219 /*
1220 * Initialize the receive descriptor ring.
1221 */
1222 for (i = 0; i < VR_NRXDESC; i++) {
1223 ds = VR_DSRX(sc, i);
1224 if (ds->ds_mbuf == NULL) {
1225 if ((error = vr_add_rxbuf(sc, i)) != 0) {
1226 aprint_error_dev(sc->vr_dev,
1227 "unable to allocate or map rx buffer %d, "
1228 "error = %d\n", i, error);
1229 /*
1230 * XXX Should attempt to run with fewer receive
1231 * XXX buffers instead of just failing.
1232 */
1233 vr_rxdrain(sc);
1234 goto out;
1235 }
1236 } else
1237 VR_INIT_RXDESC(sc, i);
1238 }
1239 sc->vr_rxptr = 0;
1240
1241 /* If we want promiscuous mode, set the allframes bit. */
1242 if (ifp->if_flags & IFF_PROMISC)
1243 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1244 else
1245 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1246
1247 /* Set capture broadcast bit to capture broadcast frames. */
1248 if (ifp->if_flags & IFF_BROADCAST)
1249 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1250 else
1251 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1252
1253 /* Program the multicast filter, if necessary. */
1254 vr_setmulti(sc);
1255
1256 /* Give the transmit and receive rings to the Rhine. */
1257 CSR_WRITE_4(sc, VR_RXADDR, VR_CDRXADDR(sc, sc->vr_rxptr));
1258 CSR_WRITE_4(sc, VR_TXADDR, VR_CDTXADDR(sc, VR_NEXTTX(sc->vr_txlast)));
1259
1260 /* Set current media. */
1261 sc->vr_link = true;
1262 if ((error = ether_mediachange(ifp)) != 0)
1263 goto out;
1264
1265 /* Enable receiver and transmitter. */
1266 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL | VR_CMD_START |
1267 VR_CMD_TX_ON | VR_CMD_RX_ON |
1268 VR_CMD_RX_GO);
1269
1270 /* Enable interrupts. */
1271 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1272 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1273
1274 ifp->if_flags |= IFF_RUNNING;
1275
1276 /* Start one second timer. */
1277 callout_schedule(&sc->vr_tick_ch, hz);
1278
1279 /* Attempt to start output on the interface. */
1280 vr_start(ifp);
1281
1282 out:
1283 if (error)
1284 aprint_error_dev(sc->vr_dev, "interface not running\n");
1285 return (error);
1286 }
1287
1288 static int
vr_ioctl(struct ifnet * ifp,u_long command,void * data)1289 vr_ioctl(struct ifnet *ifp, u_long command, void *data)
1290 {
1291 struct vr_softc *sc = ifp->if_softc;
1292 int s, error = 0;
1293
1294 s = splnet();
1295
1296 switch (command) {
1297 case SIOCSIFFLAGS:
1298 if ((error = ifioctl_common(ifp, command, data)) != 0)
1299 break;
1300
1301 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1302 case IFF_RUNNING:
1303 vr_stop(ifp, 1);
1304 break;
1305 case IFF_UP:
1306 vr_init(ifp);
1307 break;
1308 case IFF_UP | IFF_RUNNING:
1309 if ((ifp->if_flags ^ sc->vr_if_flags) == IFF_PROMISC)
1310 vr_setmulti(sc);
1311 else
1312 vr_init(ifp);
1313 break;
1314 }
1315 sc->vr_if_flags = ifp->if_flags;
1316 break;
1317 default:
1318 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
1319 break;
1320 error = 0;
1321 if (command == SIOCADDMULTI || command == SIOCDELMULTI)
1322 vr_setmulti(sc);
1323 }
1324 splx(s);
1325
1326 return error;
1327 }
1328
1329 static void
vr_watchdog(struct ifnet * ifp)1330 vr_watchdog(struct ifnet *ifp)
1331 {
1332 struct vr_softc *sc = ifp->if_softc;
1333
1334 aprint_error_dev(sc->vr_dev, "device timeout\n");
1335 if_statinc(ifp, if_oerrors);
1336
1337 (void) vr_init(ifp);
1338 }
1339
1340 /*
1341 * One second timer, used to tick MII.
1342 */
1343 static void
vr_tick(void * arg)1344 vr_tick(void *arg)
1345 {
1346 struct vr_softc *sc = arg;
1347 int s;
1348
1349 s = splnet();
1350 if (sc->vr_flags & VR_F_RESTART) {
1351 aprint_normal_dev(sc->vr_dev, "restarting\n");
1352 vr_init(&sc->vr_ec.ec_if);
1353 sc->vr_flags &= ~VR_F_RESTART;
1354 }
1355 mii_tick(&sc->vr_mii);
1356 splx(s);
1357
1358 callout_schedule(&sc->vr_tick_ch, hz);
1359 }
1360
1361 /*
1362 * Drain the receive queue.
1363 */
1364 static void
vr_rxdrain(struct vr_softc * sc)1365 vr_rxdrain(struct vr_softc *sc)
1366 {
1367 struct vr_descsoft *ds;
1368 int i;
1369
1370 for (i = 0; i < VR_NRXDESC; i++) {
1371 ds = VR_DSRX(sc, i);
1372 if (ds->ds_mbuf != NULL) {
1373 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap);
1374 m_freem(ds->ds_mbuf);
1375 ds->ds_mbuf = NULL;
1376 }
1377 }
1378 }
1379
1380 /*
1381 * Stop the adapter and free any mbufs allocated to the
1382 * transmit lists.
1383 */
1384 static void
vr_stop(struct ifnet * ifp,int disable)1385 vr_stop(struct ifnet *ifp, int disable)
1386 {
1387 struct vr_softc *sc = ifp->if_softc;
1388 struct vr_descsoft *ds;
1389 int i;
1390
1391 /* Cancel one second timer. */
1392 callout_stop(&sc->vr_tick_ch);
1393
1394 /* Down the MII. */
1395 mii_down(&sc->vr_mii);
1396
1397 ifp = &sc->vr_ec.ec_if;
1398 ifp->if_timer = 0;
1399
1400 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1401 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON | VR_CMD_TX_ON));
1402 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1403 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1404 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1405
1406 /*
1407 * Release any queued transmit buffers.
1408 */
1409 for (i = 0; i < VR_NTXDESC; i++) {
1410 ds = VR_DSTX(sc, i);
1411 if (ds->ds_mbuf != NULL) {
1412 bus_dmamap_unload(sc->vr_dmat, ds->ds_dmamap);
1413 m_freem(ds->ds_mbuf);
1414 ds->ds_mbuf = NULL;
1415 }
1416 }
1417
1418 /*
1419 * Mark the interface down and cancel the watchdog timer.
1420 */
1421 ifp->if_flags &= ~IFF_RUNNING;
1422 ifp->if_timer = 0;
1423
1424 if (disable)
1425 vr_rxdrain(sc);
1426 }
1427
1428 static int vr_probe(device_t, cfdata_t, void *);
1429 static void vr_attach(device_t, device_t, void *);
1430 static bool vr_shutdown(device_t, int);
1431
1432 CFATTACH_DECL_NEW(vr, sizeof (struct vr_softc),
1433 vr_probe, vr_attach, NULL, NULL);
1434
1435 static int
vr_probe(device_t parent,cfdata_t match,void * aux)1436 vr_probe(device_t parent, cfdata_t match, void *aux)
1437 {
1438 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
1439
1440 return pci_compatible_match(pa, compat_data);
1441 }
1442
1443 /*
1444 * Stop all chip I/O so that the kernel's probe routines don't
1445 * get confused by errant DMAs when rebooting.
1446 */
1447 static bool
vr_shutdown(device_t self,int howto)1448 vr_shutdown(device_t self, int howto)
1449 {
1450 struct vr_softc *sc = device_private(self);
1451
1452 vr_stop(&sc->vr_ec.ec_if, 1);
1453
1454 return true;
1455 }
1456
1457 /*
1458 * Attach the interface. Allocate softc structures, do ifmedia
1459 * setup and ethernet/BPF attach.
1460 */
1461 static void
vr_attach(device_t parent,device_t self,void * aux)1462 vr_attach(device_t parent, device_t self, void *aux)
1463 {
1464 struct vr_softc *sc = device_private(self);
1465 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
1466 bus_dma_segment_t seg;
1467 uint32_t reg;
1468 struct ifnet *ifp;
1469 struct mii_data * const mii = &sc->vr_mii;
1470 uint8_t eaddr[ETHER_ADDR_LEN], mac;
1471 int i, rseg, error;
1472 char intrbuf[PCI_INTRSTR_LEN];
1473
1474 #define PCI_CONF_WRITE(r, v) pci_conf_write(sc->vr_pc, sc->vr_tag, (r), (v))
1475 #define PCI_CONF_READ(r) pci_conf_read(sc->vr_pc, sc->vr_tag, (r))
1476
1477 sc->vr_dev = self;
1478 sc->vr_pc = pa->pa_pc;
1479 sc->vr_tag = pa->pa_tag;
1480 sc->vr_id = pa->pa_id;
1481 callout_init(&sc->vr_tick_ch, 0);
1482 callout_setfunc(&sc->vr_tick_ch, vr_tick, sc);
1483
1484 pci_aprint_devinfo(pa, NULL);
1485
1486 /*
1487 * Handle power management nonsense.
1488 */
1489
1490 sc->vr_save_iobase = PCI_CONF_READ(VR_PCI_LOIO);
1491 sc->vr_save_membase = PCI_CONF_READ(VR_PCI_LOMEM);
1492 sc->vr_save_irq = PCI_CONF_READ(PCI_INTERRUPT_REG);
1493
1494 /* power up chip */
1495 if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
1496 vr_restore_state)) && error != EOPNOTSUPP) {
1497 aprint_error_dev(self, "cannot activate %d\n", error);
1498 return;
1499 }
1500
1501 /* Make sure bus mastering is enabled. */
1502 reg = PCI_CONF_READ(PCI_COMMAND_STATUS_REG);
1503 reg |= PCI_COMMAND_MASTER_ENABLE;
1504 PCI_CONF_WRITE(PCI_COMMAND_STATUS_REG, reg);
1505
1506 /* Get revision */
1507 sc->vr_revid = PCI_REVISION(pa->pa_class);
1508
1509 /*
1510 * Map control/status registers.
1511 */
1512 {
1513 bus_space_tag_t iot, memt;
1514 bus_space_handle_t ioh, memh;
1515 int ioh_valid, memh_valid;
1516 pci_intr_handle_t intrhandle;
1517 const char *intrstr;
1518
1519 ioh_valid = (pci_mapreg_map(pa, VR_PCI_LOIO,
1520 PCI_MAPREG_TYPE_IO, 0,
1521 &iot, &ioh, NULL, NULL) == 0);
1522 memh_valid = (pci_mapreg_map(pa, VR_PCI_LOMEM,
1523 PCI_MAPREG_TYPE_MEM |
1524 PCI_MAPREG_MEM_TYPE_32BIT,
1525 0, &memt, &memh, NULL, NULL) == 0);
1526 #if defined(VR_USEIOSPACE)
1527 if (ioh_valid) {
1528 sc->vr_bst = iot;
1529 sc->vr_bsh = ioh;
1530 } else if (memh_valid) {
1531 sc->vr_bst = memt;
1532 sc->vr_bsh = memh;
1533 }
1534 #else
1535 if (memh_valid) {
1536 sc->vr_bst = memt;
1537 sc->vr_bsh = memh;
1538 } else if (ioh_valid) {
1539 sc->vr_bst = iot;
1540 sc->vr_bsh = ioh;
1541 }
1542 #endif
1543 else {
1544 aprint_error_dev(self,
1545 "unable to map device registers\n");
1546 return;
1547 }
1548
1549 /* Allocate interrupt */
1550 if (pci_intr_map(pa, &intrhandle)) {
1551 aprint_error_dev(self, "couldn't map interrupt\n");
1552 return;
1553 }
1554 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf,
1555 sizeof(intrbuf));
1556 sc->vr_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle,
1557 IPL_NET, vr_intr, sc, device_xname(self));
1558 if (sc->vr_ih == NULL) {
1559 aprint_error_dev(self, "couldn't establish interrupt");
1560 if (intrstr != NULL)
1561 aprint_error(" at %s", intrstr);
1562 aprint_error("\n");
1563 return;
1564 }
1565 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
1566 }
1567
1568 /*
1569 * Windows may put the chip in suspend mode when it
1570 * shuts down. Be sure to kick it in the head to wake it
1571 * up again.
1572 *
1573 * Don't touch this register on VT3043 since it causes
1574 * kernel MCHK trap on macppc.
1575 * (Note some VT86C100A chip returns a product ID of VT3043)
1576 */
1577 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT3043)
1578 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0 | VR_STICKHW_DS1));
1579
1580 /* Reset the adapter. */
1581 vr_reset(sc);
1582
1583 /*
1584 * Get station address. The way the Rhine chips work,
1585 * you're not allowed to directly access the EEPROM once
1586 * they've been programmed a special way. Consequently,
1587 * we need to read the node address from the PAR registers.
1588 *
1589 * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload
1590 * of the *whole* EEPROM, not just the MAC address. This is
1591 * pretty pointless since the chip does this automatically
1592 * at powerup/reset.
1593 * I suspect the same thing applies to the other Rhine
1594 * variants, but in the absence of a data sheet for those
1595 * (and the lack of anyone else noticing the problems this
1596 * causes) I'm going to retain the old behaviour for the
1597 * other parts.
1598 * In some cases, the chip really does startup without having
1599 * read the EEPROM (kern/34812). To handle this case, we force
1600 * a reload if we see an all-zeroes MAC address.
1601 */
1602 for (mac = 0, i = 0; i < ETHER_ADDR_LEN; i++)
1603 mac |= (eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i));
1604
1605 if (mac == 0 || (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105 &&
1606 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6102)) {
1607 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
1608 DELAY(200);
1609 for (i = 0; i < ETHER_ADDR_LEN; i++)
1610 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
1611 }
1612
1613 /*
1614 * A Rhine chip was detected. Inform the world.
1615 */
1616 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
1617
1618 memcpy(sc->vr_enaddr, eaddr, ETHER_ADDR_LEN);
1619
1620 sc->vr_dmat = pa->pa_dmat;
1621
1622 /*
1623 * Allocate the control data structures, and create and load
1624 * the DMA map for it.
1625 */
1626 if ((error = bus_dmamem_alloc(sc->vr_dmat,
1627 sizeof(struct vr_control_data), PAGE_SIZE, 0, &seg, 1, &rseg,
1628 0)) != 0) {
1629 aprint_error_dev(self,
1630 "unable to allocate control data, error = %d\n", error);
1631 goto fail_0;
1632 }
1633
1634 if ((error = bus_dmamem_map(sc->vr_dmat, &seg, rseg,
1635 sizeof(struct vr_control_data), (void **)&sc->vr_control_data,
1636 BUS_DMA_COHERENT)) != 0) {
1637 aprint_error_dev(self,
1638 "unable to map control data, error = %d\n", error);
1639 goto fail_1;
1640 }
1641
1642 if ((error = bus_dmamap_create(sc->vr_dmat,
1643 sizeof(struct vr_control_data), 1,
1644 sizeof(struct vr_control_data), 0, 0,
1645 &sc->vr_cddmamap)) != 0) {
1646 aprint_error_dev(self,
1647 "unable to create control data DMA map, error = %d\n",
1648 error);
1649 goto fail_2;
1650 }
1651
1652 if ((error = bus_dmamap_load(sc->vr_dmat, sc->vr_cddmamap,
1653 sc->vr_control_data, sizeof(struct vr_control_data), NULL,
1654 0)) != 0) {
1655 aprint_error_dev(self,
1656 "unable to load control data DMA map, error = %d\n",
1657 error);
1658 goto fail_3;
1659 }
1660
1661 /*
1662 * Create the transmit buffer DMA maps.
1663 */
1664 for (i = 0; i < VR_NTXDESC; i++) {
1665 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES,
1666 1, MCLBYTES, 0, 0,
1667 &VR_DSTX(sc, i)->ds_dmamap)) != 0) {
1668 aprint_error_dev(self,
1669 "unable to create tx DMA map %d, error = %d\n", i,
1670 error);
1671 goto fail_4;
1672 }
1673 }
1674
1675 /*
1676 * Create the receive buffer DMA maps.
1677 */
1678 for (i = 0; i < VR_NRXDESC; i++) {
1679 if ((error = bus_dmamap_create(sc->vr_dmat, MCLBYTES, 1,
1680 MCLBYTES, 0, 0,
1681 &VR_DSRX(sc, i)->ds_dmamap)) != 0) {
1682 aprint_error_dev(self,
1683 "unable to create rx DMA map %d, error = %d\n", i,
1684 error);
1685 goto fail_5;
1686 }
1687 VR_DSRX(sc, i)->ds_mbuf = NULL;
1688 }
1689
1690 ifp = &sc->vr_ec.ec_if;
1691 ifp->if_softc = sc;
1692 ifp->if_mtu = ETHERMTU;
1693 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1694 ifp->if_ioctl = vr_ioctl;
1695 ifp->if_start = vr_start;
1696 ifp->if_watchdog = vr_watchdog;
1697 ifp->if_init = vr_init;
1698 ifp->if_stop = vr_stop;
1699 IFQ_SET_READY(&ifp->if_snd);
1700
1701 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
1702
1703 /*
1704 * Initialize MII/media info.
1705 */
1706 mii->mii_ifp = ifp;
1707 mii->mii_readreg = vr_mii_readreg;
1708 mii->mii_writereg = vr_mii_writereg;
1709 mii->mii_statchg = vr_mii_statchg;
1710
1711 sc->vr_ec.ec_mii = mii;
1712 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
1713 ether_mediastatus);
1714 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY,
1715 MII_OFFSET_ANY, MIIF_FORCEANEG);
1716 if (LIST_FIRST(&sc->vr_mii.mii_phys) == NULL) {
1717 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
1718 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
1719 } else
1720 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1721
1722 sc->vr_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
1723
1724 /*
1725 * Call MI attach routines.
1726 */
1727 if_attach(ifp);
1728 if_deferred_start_init(ifp, NULL);
1729 ether_ifattach(ifp, sc->vr_enaddr);
1730
1731 rnd_attach_source(&sc->rnd_source, device_xname(self),
1732 RND_TYPE_NET, RND_FLAG_DEFAULT);
1733
1734 if (pmf_device_register1(self, NULL, vr_resume, vr_shutdown))
1735 pmf_class_network_register(self, ifp);
1736 else
1737 aprint_error_dev(self, "couldn't establish power handler\n");
1738
1739 return;
1740
1741 fail_5:
1742 for (i = 0; i < VR_NRXDESC; i++) {
1743 if (sc->vr_rxsoft[i].ds_dmamap != NULL)
1744 bus_dmamap_destroy(sc->vr_dmat,
1745 sc->vr_rxsoft[i].ds_dmamap);
1746 }
1747 fail_4:
1748 for (i = 0; i < VR_NTXDESC; i++) {
1749 if (sc->vr_txsoft[i].ds_dmamap != NULL)
1750 bus_dmamap_destroy(sc->vr_dmat,
1751 sc->vr_txsoft[i].ds_dmamap);
1752 }
1753 bus_dmamap_unload(sc->vr_dmat, sc->vr_cddmamap);
1754 fail_3:
1755 bus_dmamap_destroy(sc->vr_dmat, sc->vr_cddmamap);
1756 fail_2:
1757 bus_dmamem_unmap(sc->vr_dmat, (void *)sc->vr_control_data,
1758 sizeof(struct vr_control_data));
1759 fail_1:
1760 bus_dmamem_free(sc->vr_dmat, &seg, rseg);
1761 fail_0:
1762 return;
1763 }
1764
1765 static int
vr_restore_state(pci_chipset_tag_t pc,pcitag_t tag,device_t self,pcireg_t state)1766 vr_restore_state(pci_chipset_tag_t pc, pcitag_t tag, device_t self,
1767 pcireg_t state)
1768 {
1769 struct vr_softc *sc = device_private(self);
1770 int error;
1771
1772 if (state == PCI_PMCSR_STATE_D0)
1773 return 0;
1774 if ((error = pci_set_powerstate(pc, tag, PCI_PMCSR_STATE_D0)))
1775 return error;
1776
1777 /* Restore PCI config data. */
1778 PCI_CONF_WRITE(VR_PCI_LOIO, sc->vr_save_iobase);
1779 PCI_CONF_WRITE(VR_PCI_LOMEM, sc->vr_save_membase);
1780 PCI_CONF_WRITE(PCI_INTERRUPT_REG, sc->vr_save_irq);
1781 return 0;
1782 }
1783
1784 static bool
vr_resume(device_t self,const pmf_qual_t * qual)1785 vr_resume(device_t self, const pmf_qual_t *qual)
1786 {
1787 struct vr_softc *sc = device_private(self);
1788
1789 if (PCI_PRODUCT(sc->vr_id) != PCI_PRODUCT_VIATECH_VT3043)
1790 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0 | VR_STICKHW_DS1));
1791
1792 return true;
1793 }
1794