1 /* $NetBSD: amdgpu_vega12_hwmgr.c,v 1.4 2021/12/19 12:37:54 riastradh Exp $ */
2
3 /*
4 * Copyright 2017 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vega12_hwmgr.c,v 1.4 2021/12/19 12:37:54 riastradh Exp $");
28
29 #include <linux/delay.h>
30 #include <linux/fb.h>
31 #include <linux/module.h>
32 #include <linux/slab.h>
33
34 #include "hwmgr.h"
35 #include "amd_powerplay.h"
36 #include "vega12_smumgr.h"
37 #include "hardwaremanager.h"
38 #include "ppatomfwctrl.h"
39 #include "atomfirmware.h"
40 #include "cgs_common.h"
41 #include "vega12_inc.h"
42 #include "pppcielanes.h"
43 #include "vega12_hwmgr.h"
44 #include "vega12_processpptables.h"
45 #include "vega12_pptable.h"
46 #include "vega12_thermal.h"
47 #include "vega12_ppsmc.h"
48 #include "pp_debug.h"
49 #include "amd_pcie_helpers.h"
50 #include "ppinterrupt.h"
51 #include "pp_overdriver.h"
52 #include "pp_thermal.h"
53 #include "vega12_baco.h"
54
55 #include <linux/nbsd-namespace.h>
56
57
58 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
59 enum pp_clock_type type, uint32_t mask);
60 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
61 uint32_t *clock,
62 PPCLK_e clock_select,
63 bool max);
64
vega12_set_default_registry_data(struct pp_hwmgr * hwmgr)65 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
66 {
67 struct vega12_hwmgr *data =
68 (struct vega12_hwmgr *)(hwmgr->backend);
69
70 data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
71 data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
72 data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
73 data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
74 data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
75
76 data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
77 data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
78 data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
79 data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
80 data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
81 data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
82 data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
83 data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
84 data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
85 data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
86 data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
87 data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
88 data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
89
90 data->registry_data.disallowed_features = 0x0;
91 data->registry_data.od_state_in_dc_support = 0;
92 data->registry_data.thermal_support = 1;
93 data->registry_data.skip_baco_hardware = 0;
94
95 data->registry_data.log_avfs_param = 0;
96 data->registry_data.sclk_throttle_low_notification = 1;
97 data->registry_data.force_dpm_high = 0;
98 data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
99
100 data->registry_data.didt_support = 0;
101 if (data->registry_data.didt_support) {
102 data->registry_data.didt_mode = 6;
103 data->registry_data.sq_ramping_support = 1;
104 data->registry_data.db_ramping_support = 0;
105 data->registry_data.td_ramping_support = 0;
106 data->registry_data.tcp_ramping_support = 0;
107 data->registry_data.dbr_ramping_support = 0;
108 data->registry_data.edc_didt_support = 1;
109 data->registry_data.gc_didt_support = 0;
110 data->registry_data.psm_didt_support = 0;
111 }
112
113 data->registry_data.pcie_lane_override = 0xff;
114 data->registry_data.pcie_speed_override = 0xff;
115 data->registry_data.pcie_clock_override = 0xffffffff;
116 data->registry_data.regulator_hot_gpio_support = 1;
117 data->registry_data.ac_dc_switch_gpio_support = 0;
118 data->registry_data.quick_transition_support = 0;
119 data->registry_data.zrpm_start_temp = 0xffff;
120 data->registry_data.zrpm_stop_temp = 0xffff;
121 data->registry_data.odn_feature_enable = 1;
122 data->registry_data.disable_water_mark = 0;
123 data->registry_data.disable_pp_tuning = 0;
124 data->registry_data.disable_xlpp_tuning = 0;
125 data->registry_data.disable_workload_policy = 0;
126 data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
127 data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
128 data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
129 data->registry_data.force_workload_policy_mask = 0;
130 data->registry_data.disable_3d_fs_detection = 0;
131 data->registry_data.fps_support = 1;
132 data->registry_data.disable_auto_wattman = 1;
133 data->registry_data.auto_wattman_debug = 0;
134 data->registry_data.auto_wattman_sample_period = 100;
135 data->registry_data.auto_wattman_threshold = 50;
136 }
137
vega12_set_features_platform_caps(struct pp_hwmgr * hwmgr)138 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
139 {
140 struct vega12_hwmgr *data =
141 (struct vega12_hwmgr *)(hwmgr->backend);
142 struct amdgpu_device *adev = hwmgr->adev;
143
144 if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
145 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
146 PHM_PlatformCaps_ControlVDDCI);
147
148 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
149 PHM_PlatformCaps_TablelessHardwareInterface);
150
151 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
152 PHM_PlatformCaps_EnableSMU7ThermalManagement);
153
154 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
155 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
156 PHM_PlatformCaps_UVDPowerGating);
157 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
158 PHM_PlatformCaps_UVDDynamicPowerGating);
159 }
160
161 if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
162 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
163 PHM_PlatformCaps_VCEPowerGating);
164
165 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
166 PHM_PlatformCaps_UnTabledHardwareInterface);
167
168 if (data->registry_data.odn_feature_enable)
169 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
170 PHM_PlatformCaps_ODNinACSupport);
171 else {
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_OD6inACSupport);
174 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
175 PHM_PlatformCaps_OD6PlusinACSupport);
176 }
177
178 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
179 PHM_PlatformCaps_ActivityReporting);
180 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
181 PHM_PlatformCaps_FanSpeedInTableIsRPM);
182
183 if (data->registry_data.od_state_in_dc_support) {
184 if (data->registry_data.odn_feature_enable)
185 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
186 PHM_PlatformCaps_ODNinDCSupport);
187 else {
188 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
189 PHM_PlatformCaps_OD6inDCSupport);
190 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
191 PHM_PlatformCaps_OD6PlusinDCSupport);
192 }
193 }
194
195 if (data->registry_data.thermal_support
196 && data->registry_data.fuzzy_fan_control_support
197 && hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
198 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
199 PHM_PlatformCaps_ODFuzzyFanControlSupport);
200
201 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
202 PHM_PlatformCaps_DynamicPowerManagement);
203 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
204 PHM_PlatformCaps_SMC);
205 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
206 PHM_PlatformCaps_ThermalPolicyDelay);
207
208 if (data->registry_data.force_dpm_high)
209 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
210 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
211
212 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
213 PHM_PlatformCaps_DynamicUVDState);
214
215 if (data->registry_data.sclk_throttle_low_notification)
216 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
217 PHM_PlatformCaps_SclkThrottleLowNotification);
218
219 /* power tune caps */
220 /* assume disabled */
221 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
222 PHM_PlatformCaps_PowerContainment);
223 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
224 PHM_PlatformCaps_DiDtSupport);
225 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
226 PHM_PlatformCaps_SQRamping);
227 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
228 PHM_PlatformCaps_DBRamping);
229 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
230 PHM_PlatformCaps_TDRamping);
231 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
232 PHM_PlatformCaps_TCPRamping);
233 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
234 PHM_PlatformCaps_DBRRamping);
235 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
236 PHM_PlatformCaps_DiDtEDCEnable);
237 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
238 PHM_PlatformCaps_GCEDC);
239 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
240 PHM_PlatformCaps_PSM);
241
242 if (data->registry_data.didt_support) {
243 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
244 if (data->registry_data.sq_ramping_support)
245 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
246 if (data->registry_data.db_ramping_support)
247 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
248 if (data->registry_data.td_ramping_support)
249 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
250 if (data->registry_data.tcp_ramping_support)
251 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
252 if (data->registry_data.dbr_ramping_support)
253 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
254 if (data->registry_data.edc_didt_support)
255 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
256 if (data->registry_data.gc_didt_support)
257 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
258 if (data->registry_data.psm_didt_support)
259 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
260 }
261
262 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
263 PHM_PlatformCaps_RegulatorHot);
264
265 if (data->registry_data.ac_dc_switch_gpio_support) {
266 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
267 PHM_PlatformCaps_AutomaticDCTransition);
268 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
269 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
270 }
271
272 if (data->registry_data.quick_transition_support) {
273 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
274 PHM_PlatformCaps_AutomaticDCTransition);
275 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
276 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
277 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
278 PHM_PlatformCaps_Falcon_QuickTransition);
279 }
280
281 if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
282 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
283 PHM_PlatformCaps_LowestUclkReservedForUlv);
284 if (data->lowest_uclk_reserved_for_ulv == 1)
285 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
286 PHM_PlatformCaps_LowestUclkReservedForUlv);
287 }
288
289 if (data->registry_data.custom_fan_support)
290 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
291 PHM_PlatformCaps_CustomFanControlSupport);
292
293 return 0;
294 }
295
vega12_init_dpm_defaults(struct pp_hwmgr * hwmgr)296 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
297 {
298 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
299 struct amdgpu_device *adev = hwmgr->adev;
300 uint32_t top32, bottom32;
301 int i;
302
303 data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
304 FEATURE_DPM_PREFETCHER_BIT;
305 data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
306 FEATURE_DPM_GFXCLK_BIT;
307 data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
308 FEATURE_DPM_UCLK_BIT;
309 data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
310 FEATURE_DPM_SOCCLK_BIT;
311 data->smu_features[GNLD_DPM_UVD].smu_feature_id =
312 FEATURE_DPM_UVD_BIT;
313 data->smu_features[GNLD_DPM_VCE].smu_feature_id =
314 FEATURE_DPM_VCE_BIT;
315 data->smu_features[GNLD_ULV].smu_feature_id =
316 FEATURE_ULV_BIT;
317 data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
318 FEATURE_DPM_MP0CLK_BIT;
319 data->smu_features[GNLD_DPM_LINK].smu_feature_id =
320 FEATURE_DPM_LINK_BIT;
321 data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
322 FEATURE_DPM_DCEFCLK_BIT;
323 data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
324 FEATURE_DS_GFXCLK_BIT;
325 data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
326 FEATURE_DS_SOCCLK_BIT;
327 data->smu_features[GNLD_DS_LCLK].smu_feature_id =
328 FEATURE_DS_LCLK_BIT;
329 data->smu_features[GNLD_PPT].smu_feature_id =
330 FEATURE_PPT_BIT;
331 data->smu_features[GNLD_TDC].smu_feature_id =
332 FEATURE_TDC_BIT;
333 data->smu_features[GNLD_THERMAL].smu_feature_id =
334 FEATURE_THERMAL_BIT;
335 data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
336 FEATURE_GFX_PER_CU_CG_BIT;
337 data->smu_features[GNLD_RM].smu_feature_id =
338 FEATURE_RM_BIT;
339 data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
340 FEATURE_DS_DCEFCLK_BIT;
341 data->smu_features[GNLD_ACDC].smu_feature_id =
342 FEATURE_ACDC_BIT;
343 data->smu_features[GNLD_VR0HOT].smu_feature_id =
344 FEATURE_VR0HOT_BIT;
345 data->smu_features[GNLD_VR1HOT].smu_feature_id =
346 FEATURE_VR1HOT_BIT;
347 data->smu_features[GNLD_FW_CTF].smu_feature_id =
348 FEATURE_FW_CTF_BIT;
349 data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
350 FEATURE_LED_DISPLAY_BIT;
351 data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
352 FEATURE_FAN_CONTROL_BIT;
353 data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
354 data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
355 data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
356 data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
357
358 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
359 data->smu_features[i].smu_feature_bitmap =
360 (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
361 data->smu_features[i].allowed =
362 ((data->registry_data.disallowed_features >> i) & 1) ?
363 false : true;
364 }
365
366 /* Get the SN to turn into a Unique ID */
367 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
368 top32 = smum_get_argument(hwmgr);
369 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
370 bottom32 = smum_get_argument(hwmgr);
371
372 adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
373 }
374
vega12_set_private_data_based_on_pptable(struct pp_hwmgr * hwmgr)375 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
376 {
377 return 0;
378 }
379
vega12_hwmgr_backend_fini(struct pp_hwmgr * hwmgr)380 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
381 {
382 kfree(hwmgr->backend);
383 hwmgr->backend = NULL;
384
385 return 0;
386 }
387
vega12_hwmgr_backend_init(struct pp_hwmgr * hwmgr)388 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
389 {
390 int result = 0;
391 struct vega12_hwmgr *data;
392 struct amdgpu_device *adev = hwmgr->adev;
393
394 data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
395 if (data == NULL)
396 return -ENOMEM;
397
398 hwmgr->backend = data;
399
400 vega12_set_default_registry_data(hwmgr);
401
402 data->disable_dpm_mask = 0xff;
403 data->workload_mask = 0xff;
404
405 /* need to set voltage control types before EVV patching */
406 data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
407 data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
408 data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
409
410 data->water_marks_bitmap = 0;
411 data->avfs_exist = false;
412
413 vega12_set_features_platform_caps(hwmgr);
414
415 vega12_init_dpm_defaults(hwmgr);
416
417 /* Parse pptable data read from VBIOS */
418 vega12_set_private_data_based_on_pptable(hwmgr);
419
420 data->is_tlu_enabled = false;
421
422 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
423 VEGA12_MAX_HARDWARE_POWERLEVELS;
424 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
425 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
426
427 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
428 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
429 hwmgr->platform_descriptor.clockStep.engineClock = 500;
430 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
431
432 data->total_active_cus = adev->gfx.cu_info.number;
433 /* Setup default Overdrive Fan control settings */
434 data->odn_fan_table.target_fan_speed =
435 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
436 data->odn_fan_table.target_temperature =
437 hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
438 data->odn_fan_table.min_performance_clock =
439 hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
440 data->odn_fan_table.min_fan_limit =
441 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
442 hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
443
444 if (hwmgr->feature_mask & PP_GFXOFF_MASK)
445 data->gfxoff_controlled_by_driver = true;
446 else
447 data->gfxoff_controlled_by_driver = false;
448
449 return result;
450 }
451
vega12_init_sclk_threshold(struct pp_hwmgr * hwmgr)452 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
453 {
454 struct vega12_hwmgr *data =
455 (struct vega12_hwmgr *)(hwmgr->backend);
456
457 data->low_sclk_interrupt_threshold = 0;
458
459 return 0;
460 }
461
vega12_setup_asic_task(struct pp_hwmgr * hwmgr)462 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
463 {
464 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
465 "Failed to init sclk threshold!",
466 return -EINVAL);
467
468 return 0;
469 }
470
471 /*
472 * @fn vega12_init_dpm_state
473 * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
474 *
475 * @param dpm_state - the address of the DPM Table to initiailize.
476 * @return None.
477 */
vega12_init_dpm_state(struct vega12_dpm_state * dpm_state)478 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
479 {
480 dpm_state->soft_min_level = 0x0;
481 dpm_state->soft_max_level = 0xffff;
482 dpm_state->hard_min_level = 0x0;
483 dpm_state->hard_max_level = 0xffff;
484 }
485
vega12_get_number_of_dpm_level(struct pp_hwmgr * hwmgr,PPCLK_e clk_id,uint32_t * num_of_levels)486 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
487 PPCLK_e clk_id, uint32_t *num_of_levels)
488 {
489 int ret = 0;
490
491 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
492 PPSMC_MSG_GetDpmFreqByIndex,
493 (clk_id << 16 | 0xFF));
494 PP_ASSERT_WITH_CODE(!ret,
495 "[GetNumOfDpmLevel] failed to get dpm levels!",
496 return ret);
497
498 *num_of_levels = smum_get_argument(hwmgr);
499 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
500 "[GetNumOfDpmLevel] number of clk levels is invalid!",
501 return -EINVAL);
502
503 return ret;
504 }
505
vega12_get_dpm_frequency_by_index(struct pp_hwmgr * hwmgr,PPCLK_e clkID,uint32_t index,uint32_t * clock)506 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
507 PPCLK_e clkID, uint32_t index, uint32_t *clock)
508 {
509 /*
510 *SMU expects the Clock ID to be in the top 16 bits.
511 *Lower 16 bits specify the level
512 */
513 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
514 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index)) == 0,
515 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",
516 return -EINVAL);
517
518 *clock = smum_get_argument(hwmgr);
519
520 return 0;
521 }
522
vega12_setup_single_dpm_table(struct pp_hwmgr * hwmgr,struct vega12_single_dpm_table * dpm_table,PPCLK_e clk_id)523 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
524 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
525 {
526 int ret = 0;
527 uint32_t i, num_of_levels, clk;
528
529 ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
530 PP_ASSERT_WITH_CODE(!ret,
531 "[SetupSingleDpmTable] failed to get clk levels!",
532 return ret);
533
534 dpm_table->count = num_of_levels;
535
536 for (i = 0; i < num_of_levels; i++) {
537 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
538 PP_ASSERT_WITH_CODE(!ret,
539 "[SetupSingleDpmTable] failed to get clk of specific level!",
540 return ret);
541 dpm_table->dpm_levels[i].value = clk;
542 dpm_table->dpm_levels[i].enabled = true;
543 }
544
545 return ret;
546 }
547
548 /*
549 * This function is to initialize all DPM state tables
550 * for SMU based on the dependency table.
551 * Dynamic state patching function will then trim these
552 * state tables to the allowed range based
553 * on the power policy or external client requests,
554 * such as UVD request, etc.
555 */
vega12_setup_default_dpm_tables(struct pp_hwmgr * hwmgr)556 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
557 {
558
559 struct vega12_hwmgr *data =
560 (struct vega12_hwmgr *)(hwmgr->backend);
561 struct vega12_single_dpm_table *dpm_table;
562 int ret = 0;
563
564 memset(&data->dpm_table, 0, sizeof(data->dpm_table));
565
566 /* socclk */
567 dpm_table = &(data->dpm_table.soc_table);
568 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
569 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
570 PP_ASSERT_WITH_CODE(!ret,
571 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
572 return ret);
573 } else {
574 dpm_table->count = 1;
575 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
576 }
577 vega12_init_dpm_state(&(dpm_table->dpm_state));
578
579 /* gfxclk */
580 dpm_table = &(data->dpm_table.gfx_table);
581 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
582 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
583 PP_ASSERT_WITH_CODE(!ret,
584 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
585 return ret);
586 } else {
587 dpm_table->count = 1;
588 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
589 }
590 vega12_init_dpm_state(&(dpm_table->dpm_state));
591
592 /* memclk */
593 dpm_table = &(data->dpm_table.mem_table);
594 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
595 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
596 PP_ASSERT_WITH_CODE(!ret,
597 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
598 return ret);
599 } else {
600 dpm_table->count = 1;
601 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
602 }
603 vega12_init_dpm_state(&(dpm_table->dpm_state));
604
605 /* eclk */
606 dpm_table = &(data->dpm_table.eclk_table);
607 if (data->smu_features[GNLD_DPM_VCE].enabled) {
608 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
609 PP_ASSERT_WITH_CODE(!ret,
610 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
611 return ret);
612 } else {
613 dpm_table->count = 1;
614 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
615 }
616 vega12_init_dpm_state(&(dpm_table->dpm_state));
617
618 /* vclk */
619 dpm_table = &(data->dpm_table.vclk_table);
620 if (data->smu_features[GNLD_DPM_UVD].enabled) {
621 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
622 PP_ASSERT_WITH_CODE(!ret,
623 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
624 return ret);
625 } else {
626 dpm_table->count = 1;
627 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
628 }
629 vega12_init_dpm_state(&(dpm_table->dpm_state));
630
631 /* dclk */
632 dpm_table = &(data->dpm_table.dclk_table);
633 if (data->smu_features[GNLD_DPM_UVD].enabled) {
634 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
635 PP_ASSERT_WITH_CODE(!ret,
636 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
637 return ret);
638 } else {
639 dpm_table->count = 1;
640 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
641 }
642 vega12_init_dpm_state(&(dpm_table->dpm_state));
643
644 /* dcefclk */
645 dpm_table = &(data->dpm_table.dcef_table);
646 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
647 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
648 PP_ASSERT_WITH_CODE(!ret,
649 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
650 return ret);
651 } else {
652 dpm_table->count = 1;
653 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
654 }
655 vega12_init_dpm_state(&(dpm_table->dpm_state));
656
657 /* pixclk */
658 dpm_table = &(data->dpm_table.pixel_table);
659 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
660 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
661 PP_ASSERT_WITH_CODE(!ret,
662 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
663 return ret);
664 } else
665 dpm_table->count = 0;
666 vega12_init_dpm_state(&(dpm_table->dpm_state));
667
668 /* dispclk */
669 dpm_table = &(data->dpm_table.display_table);
670 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
671 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
672 PP_ASSERT_WITH_CODE(!ret,
673 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
674 return ret);
675 } else
676 dpm_table->count = 0;
677 vega12_init_dpm_state(&(dpm_table->dpm_state));
678
679 /* phyclk */
680 dpm_table = &(data->dpm_table.phy_table);
681 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
682 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
683 PP_ASSERT_WITH_CODE(!ret,
684 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
685 return ret);
686 } else
687 dpm_table->count = 0;
688 vega12_init_dpm_state(&(dpm_table->dpm_state));
689
690 /* save a copy of the default DPM table */
691 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
692 sizeof(struct vega12_dpm_table));
693
694 return 0;
695 }
696
697 #if 0
698 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
699 {
700 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
701 struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
702 uint32_t min_level;
703
704 hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
705 hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
706
707 /* Optimize compute power profile: Use only highest
708 * 2 power levels (if more than 2 are available)
709 */
710 if (dpm_table->count > 2)
711 min_level = dpm_table->count - 2;
712 else if (dpm_table->count == 2)
713 min_level = 1;
714 else
715 min_level = 0;
716
717 hwmgr->default_compute_power_profile.min_sclk =
718 dpm_table->dpm_levels[min_level].value;
719
720 hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
721 hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
722
723 return 0;
724 }
725 #endif
726
727 /**
728 * Initializes the SMC table and uploads it
729 *
730 * @param hwmgr the address of the powerplay hardware manager.
731 * @param pInput the pointer to input data (PowerState)
732 * @return always 0
733 */
vega12_init_smc_table(struct pp_hwmgr * hwmgr)734 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
735 {
736 int result;
737 struct vega12_hwmgr *data =
738 (struct vega12_hwmgr *)(hwmgr->backend);
739 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
740 struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
741 struct phm_ppt_v3_information *pptable_information =
742 (struct phm_ppt_v3_information *)hwmgr->pptable;
743
744 result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
745 if (!result) {
746 data->vbios_boot_state.vddc = boot_up_values.usVddc;
747 data->vbios_boot_state.vddci = boot_up_values.usVddci;
748 data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
749 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
750 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
751 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
752 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
753 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
754 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
755 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
756 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
757 smum_send_msg_to_smc_with_parameter(hwmgr,
758 PPSMC_MSG_SetMinDeepSleepDcefclk,
759 (uint32_t)(data->vbios_boot_state.dcef_clock / 100));
760 }
761
762 memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
763
764 result = smum_smc_table_manager(hwmgr,
765 (uint8_t *)pp_table, TABLE_PPTABLE, false);
766 PP_ASSERT_WITH_CODE(!result,
767 "Failed to upload PPtable!", return result);
768
769 return 0;
770 }
771
vega12_run_acg_btc(struct pp_hwmgr * hwmgr)772 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
773 {
774 uint32_t result;
775
776 PP_ASSERT_WITH_CODE(
777 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc) == 0,
778 "[Run_ACG_BTC] Attempt to run ACG BTC failed!",
779 return -EINVAL);
780
781 result = smum_get_argument(hwmgr);
782 PP_ASSERT_WITH_CODE(result == 1,
783 "Failed to run ACG BTC!", return -EINVAL);
784
785 return 0;
786 }
787
vega12_set_allowed_featuresmask(struct pp_hwmgr * hwmgr)788 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
789 {
790 struct vega12_hwmgr *data =
791 (struct vega12_hwmgr *)(hwmgr->backend);
792 int i;
793 uint32_t allowed_features_low = 0, allowed_features_high = 0;
794
795 for (i = 0; i < GNLD_FEATURES_MAX; i++)
796 if (data->smu_features[i].allowed)
797 data->smu_features[i].smu_feature_id > 31 ?
798 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
799 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
800
801 PP_ASSERT_WITH_CODE(
802 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high) == 0,
803 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
804 return -1);
805
806 PP_ASSERT_WITH_CODE(
807 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low) == 0,
808 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
809 return -1);
810
811 return 0;
812 }
813
vega12_init_powergate_state(struct pp_hwmgr * hwmgr)814 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
815 {
816 struct vega12_hwmgr *data =
817 (struct vega12_hwmgr *)(hwmgr->backend);
818
819 data->uvd_power_gated = true;
820 data->vce_power_gated = true;
821
822 if (data->smu_features[GNLD_DPM_UVD].enabled)
823 data->uvd_power_gated = false;
824
825 if (data->smu_features[GNLD_DPM_VCE].enabled)
826 data->vce_power_gated = false;
827 }
828
vega12_enable_all_smu_features(struct pp_hwmgr * hwmgr)829 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
830 {
831 struct vega12_hwmgr *data =
832 (struct vega12_hwmgr *)(hwmgr->backend);
833 uint64_t features_enabled;
834 int i;
835 bool enabled;
836
837 PP_ASSERT_WITH_CODE(
838 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures) == 0,
839 "[EnableAllSMUFeatures] Failed to enable all smu features!",
840 return -1);
841
842 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
843 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
844 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
845 data->smu_features[i].enabled = enabled;
846 data->smu_features[i].supported = enabled;
847 }
848 }
849
850 vega12_init_powergate_state(hwmgr);
851
852 return 0;
853 }
854
vega12_disable_all_smu_features(struct pp_hwmgr * hwmgr)855 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
856 {
857 struct vega12_hwmgr *data =
858 (struct vega12_hwmgr *)(hwmgr->backend);
859 uint64_t features_enabled;
860 int i;
861 bool enabled;
862
863 PP_ASSERT_WITH_CODE(
864 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures) == 0,
865 "[DisableAllSMUFeatures] Failed to disable all smu features!",
866 return -1);
867
868 if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
869 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
870 enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
871 data->smu_features[i].enabled = enabled;
872 data->smu_features[i].supported = enabled;
873 }
874 }
875
876 return 0;
877 }
878
vega12_odn_initialize_default_settings(struct pp_hwmgr * hwmgr)879 static int vega12_odn_initialize_default_settings(
880 struct pp_hwmgr *hwmgr)
881 {
882 return 0;
883 }
884
vega12_set_overdrive_target_percentage(struct pp_hwmgr * hwmgr,uint32_t adjust_percent)885 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
886 uint32_t adjust_percent)
887 {
888 return smum_send_msg_to_smc_with_parameter(hwmgr,
889 PPSMC_MSG_OverDriveSetPercentage, adjust_percent);
890 }
891
vega12_power_control_set_level(struct pp_hwmgr * hwmgr)892 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
893 {
894 int adjust_percent, result = 0;
895
896 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
897 adjust_percent =
898 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
899 hwmgr->platform_descriptor.TDPAdjustment :
900 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
901 result = vega12_set_overdrive_target_percentage(hwmgr,
902 (uint32_t)adjust_percent);
903 }
904 return result;
905 }
906
vega12_get_all_clock_ranges_helper(struct pp_hwmgr * hwmgr,PPCLK_e clkid,struct vega12_clock_range * clock)907 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
908 PPCLK_e clkid, struct vega12_clock_range *clock)
909 {
910 /* AC Max */
911 PP_ASSERT_WITH_CODE(
912 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16)) == 0,
913 "[GetClockRanges] Failed to get max ac clock from SMC!",
914 return -EINVAL);
915 clock->ACMax = smum_get_argument(hwmgr);
916
917 /* AC Min */
918 PP_ASSERT_WITH_CODE(
919 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16)) == 0,
920 "[GetClockRanges] Failed to get min ac clock from SMC!",
921 return -EINVAL);
922 clock->ACMin = smum_get_argument(hwmgr);
923
924 /* DC Max */
925 PP_ASSERT_WITH_CODE(
926 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16)) == 0,
927 "[GetClockRanges] Failed to get max dc clock from SMC!",
928 return -EINVAL);
929 clock->DCMax = smum_get_argument(hwmgr);
930
931 return 0;
932 }
933
vega12_get_all_clock_ranges(struct pp_hwmgr * hwmgr)934 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
935 {
936 struct vega12_hwmgr *data =
937 (struct vega12_hwmgr *)(hwmgr->backend);
938 uint32_t i;
939
940 for (i = 0; i < PPCLK_COUNT; i++)
941 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
942 i, &(data->clk_range[i])),
943 "Failed to get clk range from SMC!",
944 return -EINVAL);
945
946 return 0;
947 }
948
vega12_enable_dpm_tasks(struct pp_hwmgr * hwmgr)949 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
950 {
951 int tmp_result, result = 0;
952
953 smum_send_msg_to_smc_with_parameter(hwmgr,
954 PPSMC_MSG_NumOfDisplays, 0);
955
956 result = vega12_set_allowed_featuresmask(hwmgr);
957 PP_ASSERT_WITH_CODE(result == 0,
958 "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
959 return result);
960
961 tmp_result = vega12_init_smc_table(hwmgr);
962 PP_ASSERT_WITH_CODE(!tmp_result,
963 "Failed to initialize SMC table!",
964 result = tmp_result);
965
966 tmp_result = vega12_run_acg_btc(hwmgr);
967 PP_ASSERT_WITH_CODE(!tmp_result,
968 "Failed to run ACG BTC!",
969 result = tmp_result);
970
971 result = vega12_enable_all_smu_features(hwmgr);
972 PP_ASSERT_WITH_CODE(!result,
973 "Failed to enable all smu features!",
974 return result);
975
976 tmp_result = vega12_power_control_set_level(hwmgr);
977 PP_ASSERT_WITH_CODE(!tmp_result,
978 "Failed to power control set level!",
979 result = tmp_result);
980
981 result = vega12_get_all_clock_ranges(hwmgr);
982 PP_ASSERT_WITH_CODE(!result,
983 "Failed to get all clock ranges!",
984 return result);
985
986 result = vega12_odn_initialize_default_settings(hwmgr);
987 PP_ASSERT_WITH_CODE(!result,
988 "Failed to power control set level!",
989 return result);
990
991 result = vega12_setup_default_dpm_tables(hwmgr);
992 PP_ASSERT_WITH_CODE(!result,
993 "Failed to setup default DPM tables!",
994 return result);
995 return result;
996 }
997
vega12_patch_boot_state(struct pp_hwmgr * hwmgr,struct pp_hw_power_state * hw_ps)998 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
999 struct pp_hw_power_state *hw_ps)
1000 {
1001 return 0;
1002 }
1003
vega12_find_lowest_dpm_level(struct vega12_single_dpm_table * table)1004 static uint32_t vega12_find_lowest_dpm_level(
1005 struct vega12_single_dpm_table *table)
1006 {
1007 uint32_t i;
1008
1009 for (i = 0; i < table->count; i++) {
1010 if (table->dpm_levels[i].enabled)
1011 break;
1012 }
1013
1014 if (i >= table->count) {
1015 i = 0;
1016 table->dpm_levels[i].enabled = true;
1017 }
1018
1019 return i;
1020 }
1021
vega12_find_highest_dpm_level(struct vega12_single_dpm_table * table)1022 static uint32_t vega12_find_highest_dpm_level(
1023 struct vega12_single_dpm_table *table)
1024 {
1025 int32_t i = 0;
1026 PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1027 "[FindHighestDPMLevel] DPM Table has too many entries!",
1028 return MAX_REGULAR_DPM_NUMBER - 1);
1029
1030 for (i = table->count - 1; i >= 0; i--) {
1031 if (table->dpm_levels[i].enabled)
1032 break;
1033 }
1034
1035 if (i < 0) {
1036 i = 0;
1037 table->dpm_levels[i].enabled = true;
1038 }
1039
1040 return (uint32_t)i;
1041 }
1042
vega12_upload_dpm_min_level(struct pp_hwmgr * hwmgr)1043 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1044 {
1045 struct vega12_hwmgr *data = hwmgr->backend;
1046 uint32_t min_freq;
1047 int ret = 0;
1048
1049 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1050 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1051 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1052 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1053 (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))),
1054 "Failed to set soft min gfxclk !",
1055 return ret);
1056 }
1057
1058 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1059 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1060 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1061 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1062 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1063 "Failed to set soft min memclk !",
1064 return ret);
1065
1066 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1067 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1068 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1069 (PPCLK_UCLK << 16) | (min_freq & 0xffff))),
1070 "Failed to set hard min memclk !",
1071 return ret);
1072 }
1073
1074 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1075 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1076
1077 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1078 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1079 (PPCLK_VCLK << 16) | (min_freq & 0xffff))),
1080 "Failed to set soft min vclk!",
1081 return ret);
1082
1083 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1084
1085 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1086 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1087 (PPCLK_DCLK << 16) | (min_freq & 0xffff))),
1088 "Failed to set soft min dclk!",
1089 return ret);
1090 }
1091
1092 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1093 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1094
1095 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1096 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1097 (PPCLK_ECLK << 16) | (min_freq & 0xffff))),
1098 "Failed to set soft min eclk!",
1099 return ret);
1100 }
1101
1102 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1103 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1104
1105 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1106 hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1107 (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))),
1108 "Failed to set soft min socclk!",
1109 return ret);
1110 }
1111
1112 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1113 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1114
1115 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1116 hwmgr, PPSMC_MSG_SetHardMinByFreq,
1117 (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff))),
1118 "Failed to set hard min dcefclk!",
1119 return ret);
1120 }
1121
1122 return ret;
1123
1124 }
1125
vega12_upload_dpm_max_level(struct pp_hwmgr * hwmgr)1126 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1127 {
1128 struct vega12_hwmgr *data = hwmgr->backend;
1129 uint32_t max_freq;
1130 int ret = 0;
1131
1132 if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1133 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1134
1135 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1136 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1137 (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))),
1138 "Failed to set soft max gfxclk!",
1139 return ret);
1140 }
1141
1142 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1143 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1144
1145 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1146 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1147 (PPCLK_UCLK << 16) | (max_freq & 0xffff))),
1148 "Failed to set soft max memclk!",
1149 return ret);
1150 }
1151
1152 if (data->smu_features[GNLD_DPM_UVD].enabled) {
1153 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1154
1155 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1156 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1157 (PPCLK_VCLK << 16) | (max_freq & 0xffff))),
1158 "Failed to set soft max vclk!",
1159 return ret);
1160
1161 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1162 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1163 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1164 (PPCLK_DCLK << 16) | (max_freq & 0xffff))),
1165 "Failed to set soft max dclk!",
1166 return ret);
1167 }
1168
1169 if (data->smu_features[GNLD_DPM_VCE].enabled) {
1170 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1171
1172 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1173 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1174 (PPCLK_ECLK << 16) | (max_freq & 0xffff))),
1175 "Failed to set soft max eclk!",
1176 return ret);
1177 }
1178
1179 if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1180 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1181
1182 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1183 hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1184 (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))),
1185 "Failed to set soft max socclk!",
1186 return ret);
1187 }
1188
1189 return ret;
1190 }
1191
vega12_enable_disable_vce_dpm(struct pp_hwmgr * hwmgr,bool enable)1192 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1193 {
1194 struct vega12_hwmgr *data =
1195 (struct vega12_hwmgr *)(hwmgr->backend);
1196
1197 if (data->smu_features[GNLD_DPM_VCE].supported) {
1198 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
1199 enable,
1200 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
1201 "Attempt to Enable/Disable DPM VCE Failed!",
1202 return -1);
1203 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1204 }
1205
1206 return 0;
1207 }
1208
vega12_dpm_get_sclk(struct pp_hwmgr * hwmgr,bool low)1209 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1210 {
1211 struct vega12_hwmgr *data =
1212 (struct vega12_hwmgr *)(hwmgr->backend);
1213 uint32_t gfx_clk;
1214
1215 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1216 return -1;
1217
1218 if (low)
1219 PP_ASSERT_WITH_CODE(
1220 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
1221 "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1222 return -1);
1223 else
1224 PP_ASSERT_WITH_CODE(
1225 vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
1226 "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1227 return -1);
1228
1229 return (gfx_clk * 100);
1230 }
1231
vega12_dpm_get_mclk(struct pp_hwmgr * hwmgr,bool low)1232 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1233 {
1234 struct vega12_hwmgr *data =
1235 (struct vega12_hwmgr *)(hwmgr->backend);
1236 uint32_t mem_clk;
1237
1238 if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1239 return -1;
1240
1241 if (low)
1242 PP_ASSERT_WITH_CODE(
1243 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
1244 "[GetMclks]: fail to get min PPCLK_UCLK\n",
1245 return -1);
1246 else
1247 PP_ASSERT_WITH_CODE(
1248 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
1249 "[GetMclks]: fail to get max PPCLK_UCLK\n",
1250 return -1);
1251
1252 return (mem_clk * 100);
1253 }
1254
vega12_get_metrics_table(struct pp_hwmgr * hwmgr,SmuMetrics_t * metrics_table)1255 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
1256 {
1257 struct vega12_hwmgr *data =
1258 (struct vega12_hwmgr *)(hwmgr->backend);
1259 int ret = 0;
1260
1261 if (!data->metrics_time || time_after(jiffies, data->metrics_time + HZ / 2)) {
1262 ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
1263 TABLE_SMU_METRICS, true);
1264 if (ret) {
1265 pr_info("Failed to export SMU metrics table!\n");
1266 return ret;
1267 }
1268 memcpy(&data->metrics_table, metrics_table, sizeof(SmuMetrics_t));
1269 data->metrics_time = jiffies;
1270 } else
1271 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
1272
1273 return ret;
1274 }
1275
vega12_get_gpu_power(struct pp_hwmgr * hwmgr,uint32_t * query)1276 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
1277 {
1278 SmuMetrics_t metrics_table;
1279 int ret = 0;
1280
1281 ret = vega12_get_metrics_table(hwmgr, &metrics_table);
1282 if (ret)
1283 return ret;
1284
1285 *query = metrics_table.CurrSocketPower << 8;
1286
1287 return ret;
1288 }
1289
vega12_get_current_gfx_clk_freq(struct pp_hwmgr * hwmgr,uint32_t * gfx_freq)1290 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1291 {
1292 uint32_t gfx_clk = 0;
1293
1294 *gfx_freq = 0;
1295
1296 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
1297 PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16)) == 0,
1298 "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1299 return -EINVAL);
1300 gfx_clk = smum_get_argument(hwmgr);
1301
1302 *gfx_freq = gfx_clk * 100;
1303
1304 return 0;
1305 }
1306
vega12_get_current_mclk_freq(struct pp_hwmgr * hwmgr,uint32_t * mclk_freq)1307 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1308 {
1309 uint32_t mem_clk = 0;
1310
1311 *mclk_freq = 0;
1312
1313 PP_ASSERT_WITH_CODE(
1314 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0,
1315 "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1316 return -EINVAL);
1317 mem_clk = smum_get_argument(hwmgr);
1318
1319 *mclk_freq = mem_clk * 100;
1320
1321 return 0;
1322 }
1323
vega12_get_current_activity_percent(struct pp_hwmgr * hwmgr,int idx,uint32_t * activity_percent)1324 static int vega12_get_current_activity_percent(
1325 struct pp_hwmgr *hwmgr,
1326 int idx,
1327 uint32_t *activity_percent)
1328 {
1329 SmuMetrics_t metrics_table;
1330 int ret = 0;
1331
1332 ret = vega12_get_metrics_table(hwmgr, &metrics_table);
1333 if (ret)
1334 return ret;
1335
1336 switch (idx) {
1337 case AMDGPU_PP_SENSOR_GPU_LOAD:
1338 *activity_percent = metrics_table.AverageGfxActivity;
1339 break;
1340 case AMDGPU_PP_SENSOR_MEM_LOAD:
1341 *activity_percent = metrics_table.AverageUclkActivity;
1342 break;
1343 default:
1344 pr_err("Invalid index for retrieving clock activity\n");
1345 return -EINVAL;
1346 }
1347
1348 return ret;
1349 }
1350
vega12_read_sensor(struct pp_hwmgr * hwmgr,int idx,void * value,int * size)1351 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1352 void *value, int *size)
1353 {
1354 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1355 SmuMetrics_t metrics_table;
1356 int ret = 0;
1357
1358 switch (idx) {
1359 case AMDGPU_PP_SENSOR_GFX_SCLK:
1360 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1361 if (!ret)
1362 *size = 4;
1363 break;
1364 case AMDGPU_PP_SENSOR_GFX_MCLK:
1365 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1366 if (!ret)
1367 *size = 4;
1368 break;
1369 case AMDGPU_PP_SENSOR_GPU_LOAD:
1370 case AMDGPU_PP_SENSOR_MEM_LOAD:
1371 ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
1372 if (!ret)
1373 *size = 4;
1374 break;
1375 case AMDGPU_PP_SENSOR_GPU_TEMP:
1376 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
1377 *size = 4;
1378 break;
1379 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1380 ret = vega12_get_metrics_table(hwmgr, &metrics_table);
1381 if (ret)
1382 return ret;
1383
1384 *((uint32_t *)value) = metrics_table.TemperatureHotspot *
1385 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1386 *size = 4;
1387 break;
1388 case AMDGPU_PP_SENSOR_MEM_TEMP:
1389 ret = vega12_get_metrics_table(hwmgr, &metrics_table);
1390 if (ret)
1391 return ret;
1392
1393 *((uint32_t *)value) = metrics_table.TemperatureHBM *
1394 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1395 *size = 4;
1396 break;
1397 case AMDGPU_PP_SENSOR_UVD_POWER:
1398 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1399 *size = 4;
1400 break;
1401 case AMDGPU_PP_SENSOR_VCE_POWER:
1402 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1403 *size = 4;
1404 break;
1405 case AMDGPU_PP_SENSOR_GPU_POWER:
1406 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
1407 if (!ret)
1408 *size = 4;
1409 break;
1410 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1411 ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1412 if (!ret)
1413 *size = 8;
1414 break;
1415 default:
1416 ret = -EINVAL;
1417 break;
1418 }
1419 return ret;
1420 }
1421
vega12_notify_smc_display_change(struct pp_hwmgr * hwmgr,bool has_disp)1422 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1423 bool has_disp)
1424 {
1425 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1426
1427 if (data->smu_features[GNLD_DPM_UCLK].enabled)
1428 return smum_send_msg_to_smc_with_parameter(hwmgr,
1429 PPSMC_MSG_SetUclkFastSwitch,
1430 has_disp ? 1 : 0);
1431
1432 return 0;
1433 }
1434
vega12_display_clock_voltage_request(struct pp_hwmgr * hwmgr,struct pp_display_clock_request * clock_req)1435 int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1436 struct pp_display_clock_request *clock_req)
1437 {
1438 int result = 0;
1439 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1440 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1441 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1442 PPCLK_e clk_select = 0;
1443 uint32_t clk_request = 0;
1444
1445 if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1446 switch (clk_type) {
1447 case amd_pp_dcef_clock:
1448 clk_select = PPCLK_DCEFCLK;
1449 break;
1450 case amd_pp_disp_clock:
1451 clk_select = PPCLK_DISPCLK;
1452 break;
1453 case amd_pp_pixel_clock:
1454 clk_select = PPCLK_PIXCLK;
1455 break;
1456 case amd_pp_phy_clock:
1457 clk_select = PPCLK_PHYCLK;
1458 break;
1459 default:
1460 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
1461 result = -1;
1462 break;
1463 }
1464
1465 if (!result) {
1466 clk_request = (clk_select << 16) | clk_freq;
1467 result = smum_send_msg_to_smc_with_parameter(hwmgr,
1468 PPSMC_MSG_SetHardMinByFreq,
1469 clk_request);
1470 }
1471 }
1472
1473 return result;
1474 }
1475
vega12_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr * hwmgr)1476 static int vega12_notify_smc_display_config_after_ps_adjustment(
1477 struct pp_hwmgr *hwmgr)
1478 {
1479 struct vega12_hwmgr *data =
1480 (struct vega12_hwmgr *)(hwmgr->backend);
1481 struct PP_Clocks min_clocks = {0};
1482 struct pp_display_clock_request clock_req;
1483
1484 if ((hwmgr->display_config->num_display > 1) &&
1485 !hwmgr->display_config->multi_monitor_in_sync &&
1486 !hwmgr->display_config->nb_pstate_switch_disable)
1487 vega12_notify_smc_display_change(hwmgr, false);
1488 else
1489 vega12_notify_smc_display_change(hwmgr, true);
1490
1491 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1492 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1493 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1494
1495 if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1496 clock_req.clock_type = amd_pp_dcef_clock;
1497 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1498 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
1499 if (data->smu_features[GNLD_DS_DCEFCLK].supported)
1500 PP_ASSERT_WITH_CODE(
1501 !smum_send_msg_to_smc_with_parameter(
1502 hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
1503 min_clocks.dcefClockInSR /100),
1504 "Attempt to set divider for DCEFCLK Failed!",
1505 return -1);
1506 } else {
1507 pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1508 }
1509 }
1510
1511 return 0;
1512 }
1513
vega12_force_dpm_highest(struct pp_hwmgr * hwmgr)1514 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
1515 {
1516 struct vega12_hwmgr *data =
1517 (struct vega12_hwmgr *)(hwmgr->backend);
1518
1519 uint32_t soft_level;
1520
1521 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
1522
1523 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1524 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1525 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1526
1527 soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
1528
1529 data->dpm_table.mem_table.dpm_state.soft_min_level =
1530 data->dpm_table.mem_table.dpm_state.soft_max_level =
1531 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1532
1533 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1534 "Failed to upload boot level to highest!",
1535 return -1);
1536
1537 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1538 "Failed to upload dpm max level to highest!",
1539 return -1);
1540
1541 return 0;
1542 }
1543
vega12_force_dpm_lowest(struct pp_hwmgr * hwmgr)1544 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1545 {
1546 struct vega12_hwmgr *data =
1547 (struct vega12_hwmgr *)(hwmgr->backend);
1548 uint32_t soft_level;
1549
1550 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
1551
1552 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1553 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1554 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1555
1556 soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
1557
1558 data->dpm_table.mem_table.dpm_state.soft_min_level =
1559 data->dpm_table.mem_table.dpm_state.soft_max_level =
1560 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1561
1562 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1563 "Failed to upload boot level to highest!",
1564 return -1);
1565
1566 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1567 "Failed to upload dpm max level to highest!",
1568 return -1);
1569
1570 return 0;
1571
1572 }
1573
vega12_unforce_dpm_levels(struct pp_hwmgr * hwmgr)1574 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1575 {
1576 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1577 "Failed to upload DPM Bootup Levels!",
1578 return -1);
1579
1580 PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1581 "Failed to upload DPM Max Levels!",
1582 return -1);
1583
1584 return 0;
1585 }
1586
vega12_get_profiling_clk_mask(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)1587 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
1588 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1589 {
1590 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1591 struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1592 struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1593 struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
1594
1595 *sclk_mask = 0;
1596 *mclk_mask = 0;
1597 *soc_mask = 0;
1598
1599 if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1600 mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL &&
1601 soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) {
1602 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1603 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1604 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1605 }
1606
1607 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1608 *sclk_mask = 0;
1609 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1610 *mclk_mask = 0;
1611 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1612 *sclk_mask = gfx_dpm_table->count - 1;
1613 *mclk_mask = mem_dpm_table->count - 1;
1614 *soc_mask = soc_dpm_table->count - 1;
1615 }
1616
1617 return 0;
1618 }
1619
vega12_set_fan_control_mode(struct pp_hwmgr * hwmgr,uint32_t mode)1620 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
1621 {
1622 switch (mode) {
1623 case AMD_FAN_CTRL_NONE:
1624 break;
1625 case AMD_FAN_CTRL_MANUAL:
1626 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1627 vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
1628 break;
1629 case AMD_FAN_CTRL_AUTO:
1630 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1631 vega12_fan_ctrl_start_smc_fan_control(hwmgr);
1632 break;
1633 default:
1634 break;
1635 }
1636 }
1637
vega12_dpm_force_dpm_level(struct pp_hwmgr * hwmgr,enum amd_dpm_forced_level level)1638 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1639 enum amd_dpm_forced_level level)
1640 {
1641 int ret = 0;
1642 uint32_t sclk_mask = 0;
1643 uint32_t mclk_mask = 0;
1644 uint32_t soc_mask = 0;
1645
1646 switch (level) {
1647 case AMD_DPM_FORCED_LEVEL_HIGH:
1648 ret = vega12_force_dpm_highest(hwmgr);
1649 break;
1650 case AMD_DPM_FORCED_LEVEL_LOW:
1651 ret = vega12_force_dpm_lowest(hwmgr);
1652 break;
1653 case AMD_DPM_FORCED_LEVEL_AUTO:
1654 ret = vega12_unforce_dpm_levels(hwmgr);
1655 break;
1656 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1657 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1658 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1659 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1660 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1661 if (ret)
1662 return ret;
1663 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
1664 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1665 break;
1666 case AMD_DPM_FORCED_LEVEL_MANUAL:
1667 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1668 default:
1669 break;
1670 }
1671
1672 return ret;
1673 }
1674
vega12_get_fan_control_mode(struct pp_hwmgr * hwmgr)1675 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
1676 {
1677 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1678
1679 if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
1680 return AMD_FAN_CTRL_MANUAL;
1681 else
1682 return AMD_FAN_CTRL_AUTO;
1683 }
1684
vega12_get_dal_power_level(struct pp_hwmgr * hwmgr,struct amd_pp_simple_clock_info * info)1685 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
1686 struct amd_pp_simple_clock_info *info)
1687 {
1688 #if 0
1689 struct phm_ppt_v2_information *table_info =
1690 (struct phm_ppt_v2_information *)hwmgr->pptable;
1691 struct phm_clock_and_voltage_limits *max_limits =
1692 &table_info->max_clock_voltage_on_ac;
1693
1694 info->engine_max_clock = max_limits->sclk;
1695 info->memory_max_clock = max_limits->mclk;
1696 #endif
1697 return 0;
1698 }
1699
vega12_get_clock_ranges(struct pp_hwmgr * hwmgr,uint32_t * clock,PPCLK_e clock_select,bool max)1700 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
1701 uint32_t *clock,
1702 PPCLK_e clock_select,
1703 bool max)
1704 {
1705 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1706
1707 if (max)
1708 *clock = data->clk_range[clock_select].ACMax;
1709 else
1710 *clock = data->clk_range[clock_select].ACMin;
1711
1712 return 0;
1713 }
1714
vega12_get_sclks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1715 static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
1716 struct pp_clock_levels_with_latency *clocks)
1717 {
1718 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1719 uint32_t ucount;
1720 int i;
1721 struct vega12_single_dpm_table *dpm_table;
1722
1723 if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1724 return -1;
1725
1726 dpm_table = &(data->dpm_table.gfx_table);
1727 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1728 MAX_NUM_CLOCKS : dpm_table->count;
1729
1730 for (i = 0; i < ucount; i++) {
1731 clocks->data[i].clocks_in_khz =
1732 dpm_table->dpm_levels[i].value * 1000;
1733
1734 clocks->data[i].latency_in_us = 0;
1735 }
1736
1737 clocks->num_levels = ucount;
1738
1739 return 0;
1740 }
1741
vega12_get_mem_latency(struct pp_hwmgr * hwmgr,uint32_t clock)1742 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
1743 uint32_t clock)
1744 {
1745 return 25;
1746 }
1747
vega12_get_memclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1748 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
1749 struct pp_clock_levels_with_latency *clocks)
1750 {
1751 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1752 uint32_t ucount;
1753 int i;
1754 struct vega12_single_dpm_table *dpm_table;
1755 if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1756 return -1;
1757
1758 dpm_table = &(data->dpm_table.mem_table);
1759 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1760 MAX_NUM_CLOCKS : dpm_table->count;
1761
1762 for (i = 0; i < ucount; i++) {
1763 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1764 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
1765 clocks->data[i].latency_in_us =
1766 data->mclk_latency_table.entries[i].latency =
1767 vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
1768 }
1769
1770 clocks->num_levels = data->mclk_latency_table.count = ucount;
1771
1772 return 0;
1773 }
1774
vega12_get_dcefclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1775 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
1776 struct pp_clock_levels_with_latency *clocks)
1777 {
1778 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1779 uint32_t ucount;
1780 int i;
1781 struct vega12_single_dpm_table *dpm_table;
1782
1783 if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
1784 return -1;
1785
1786
1787 dpm_table = &(data->dpm_table.dcef_table);
1788 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1789 MAX_NUM_CLOCKS : dpm_table->count;
1790
1791 for (i = 0; i < ucount; i++) {
1792 clocks->data[i].clocks_in_khz =
1793 dpm_table->dpm_levels[i].value * 1000;
1794
1795 clocks->data[i].latency_in_us = 0;
1796 }
1797
1798 clocks->num_levels = ucount;
1799
1800 return 0;
1801 }
1802
vega12_get_socclocks(struct pp_hwmgr * hwmgr,struct pp_clock_levels_with_latency * clocks)1803 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
1804 struct pp_clock_levels_with_latency *clocks)
1805 {
1806 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1807 uint32_t ucount;
1808 int i;
1809 struct vega12_single_dpm_table *dpm_table;
1810
1811 if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
1812 return -1;
1813
1814
1815 dpm_table = &(data->dpm_table.soc_table);
1816 ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1817 MAX_NUM_CLOCKS : dpm_table->count;
1818
1819 for (i = 0; i < ucount; i++) {
1820 clocks->data[i].clocks_in_khz =
1821 dpm_table->dpm_levels[i].value * 1000;
1822
1823 clocks->data[i].latency_in_us = 0;
1824 }
1825
1826 clocks->num_levels = ucount;
1827
1828 return 0;
1829
1830 }
1831
vega12_get_clock_by_type_with_latency(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)1832 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1833 enum amd_pp_clock_type type,
1834 struct pp_clock_levels_with_latency *clocks)
1835 {
1836 int ret;
1837
1838 switch (type) {
1839 case amd_pp_sys_clock:
1840 ret = vega12_get_sclks(hwmgr, clocks);
1841 break;
1842 case amd_pp_mem_clock:
1843 ret = vega12_get_memclocks(hwmgr, clocks);
1844 break;
1845 case amd_pp_dcef_clock:
1846 ret = vega12_get_dcefclocks(hwmgr, clocks);
1847 break;
1848 case amd_pp_soc_clock:
1849 ret = vega12_get_socclocks(hwmgr, clocks);
1850 break;
1851 default:
1852 return -EINVAL;
1853 }
1854
1855 return ret;
1856 }
1857
vega12_get_clock_by_type_with_voltage(struct pp_hwmgr * hwmgr,enum amd_pp_clock_type type,struct pp_clock_levels_with_voltage * clocks)1858 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1859 enum amd_pp_clock_type type,
1860 struct pp_clock_levels_with_voltage *clocks)
1861 {
1862 clocks->num_levels = 0;
1863
1864 return 0;
1865 }
1866
vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr * hwmgr,void * clock_ranges)1867 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1868 void *clock_ranges)
1869 {
1870 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1871 Watermarks_t *table = &(data->smc_state_table.water_marks_table);
1872 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1873
1874 if (!data->registry_data.disable_water_mark &&
1875 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
1876 data->smu_features[GNLD_DPM_SOCCLK].supported) {
1877 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
1878 data->water_marks_bitmap |= WaterMarksExist;
1879 data->water_marks_bitmap &= ~WaterMarksLoaded;
1880 }
1881
1882 return 0;
1883 }
1884
vega12_force_clock_level(struct pp_hwmgr * hwmgr,enum pp_clock_type type,uint32_t mask)1885 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
1886 enum pp_clock_type type, uint32_t mask)
1887 {
1888 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1889 uint32_t soft_min_level, soft_max_level, hard_min_level;
1890 int ret = 0;
1891
1892 switch (type) {
1893 case PP_SCLK:
1894 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1895 soft_max_level = mask ? (fls(mask) - 1) : 0;
1896
1897 data->dpm_table.gfx_table.dpm_state.soft_min_level =
1898 data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
1899 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1900 data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
1901
1902 ret = vega12_upload_dpm_min_level(hwmgr);
1903 PP_ASSERT_WITH_CODE(!ret,
1904 "Failed to upload boot level to lowest!",
1905 return ret);
1906
1907 ret = vega12_upload_dpm_max_level(hwmgr);
1908 PP_ASSERT_WITH_CODE(!ret,
1909 "Failed to upload dpm max level to highest!",
1910 return ret);
1911 break;
1912
1913 case PP_MCLK:
1914 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1915 soft_max_level = mask ? (fls(mask) - 1) : 0;
1916
1917 data->dpm_table.mem_table.dpm_state.soft_min_level =
1918 data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
1919 data->dpm_table.mem_table.dpm_state.soft_max_level =
1920 data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
1921
1922 ret = vega12_upload_dpm_min_level(hwmgr);
1923 PP_ASSERT_WITH_CODE(!ret,
1924 "Failed to upload boot level to lowest!",
1925 return ret);
1926
1927 ret = vega12_upload_dpm_max_level(hwmgr);
1928 PP_ASSERT_WITH_CODE(!ret,
1929 "Failed to upload dpm max level to highest!",
1930 return ret);
1931
1932 break;
1933
1934 case PP_SOCCLK:
1935 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1936 soft_max_level = mask ? (fls(mask) - 1) : 0;
1937
1938 if (soft_max_level >= data->dpm_table.soc_table.count) {
1939 pr_err("Clock level specified %d is over max allowed %d\n",
1940 soft_max_level,
1941 data->dpm_table.soc_table.count - 1);
1942 return -EINVAL;
1943 }
1944
1945 data->dpm_table.soc_table.dpm_state.soft_min_level =
1946 data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
1947 data->dpm_table.soc_table.dpm_state.soft_max_level =
1948 data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
1949
1950 ret = vega12_upload_dpm_min_level(hwmgr);
1951 PP_ASSERT_WITH_CODE(!ret,
1952 "Failed to upload boot level to lowest!",
1953 return ret);
1954
1955 ret = vega12_upload_dpm_max_level(hwmgr);
1956 PP_ASSERT_WITH_CODE(!ret,
1957 "Failed to upload dpm max level to highest!",
1958 return ret);
1959
1960 break;
1961
1962 case PP_DCEFCLK:
1963 hard_min_level = mask ? (ffs(mask) - 1) : 0;
1964
1965 if (hard_min_level >= data->dpm_table.dcef_table.count) {
1966 pr_err("Clock level specified %d is over max allowed %d\n",
1967 hard_min_level,
1968 data->dpm_table.dcef_table.count - 1);
1969 return -EINVAL;
1970 }
1971
1972 data->dpm_table.dcef_table.dpm_state.hard_min_level =
1973 data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
1974
1975 ret = vega12_upload_dpm_min_level(hwmgr);
1976 PP_ASSERT_WITH_CODE(!ret,
1977 "Failed to upload boot level to lowest!",
1978 return ret);
1979
1980 //TODO: Setting DCEFCLK max dpm level is not supported
1981
1982 break;
1983
1984 case PP_PCIE:
1985 break;
1986
1987 default:
1988 break;
1989 }
1990
1991 return 0;
1992 }
1993
vega12_get_ppfeature_status(struct pp_hwmgr * hwmgr,char * buf)1994 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
1995 {
1996 static const char *ppfeature_name[] = {
1997 "DPM_PREFETCHER",
1998 "GFXCLK_DPM",
1999 "UCLK_DPM",
2000 "SOCCLK_DPM",
2001 "UVD_DPM",
2002 "VCE_DPM",
2003 "ULV",
2004 "MP0CLK_DPM",
2005 "LINK_DPM",
2006 "DCEFCLK_DPM",
2007 "GFXCLK_DS",
2008 "SOCCLK_DS",
2009 "LCLK_DS",
2010 "PPT",
2011 "TDC",
2012 "THERMAL",
2013 "GFX_PER_CU_CG",
2014 "RM",
2015 "DCEFCLK_DS",
2016 "ACDC",
2017 "VR0HOT",
2018 "VR1HOT",
2019 "FW_CTF",
2020 "LED_DISPLAY",
2021 "FAN_CONTROL",
2022 "DIDT",
2023 "GFXOFF",
2024 "CG",
2025 "ACG"};
2026 static const char *output_title[] = {
2027 "FEATURES",
2028 "BITMASK",
2029 "ENABLEMENT"};
2030 uint64_t features_enabled;
2031 int i;
2032 int ret = 0;
2033 int size = 0;
2034
2035 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2036 PP_ASSERT_WITH_CODE(!ret,
2037 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
2038 return ret);
2039
2040 size += sprintf(buf + size, "Current ppfeatures: 0x%016"PRIx64"\n", features_enabled);
2041 size += sprintf(buf + size, "%-19s %-22s %s\n",
2042 output_title[0],
2043 output_title[1],
2044 output_title[2]);
2045 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2046 size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
2047 ppfeature_name[i],
2048 1ULL << i,
2049 (features_enabled & (1ULL << i)) ? "Y" : "N");
2050 }
2051
2052 return size;
2053 }
2054
vega12_set_ppfeature_status(struct pp_hwmgr * hwmgr,uint64_t new_ppfeature_masks)2055 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
2056 {
2057 uint64_t features_enabled;
2058 uint64_t features_to_enable;
2059 uint64_t features_to_disable;
2060 int ret = 0;
2061
2062 if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2063 return -EINVAL;
2064
2065 ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2066 if (ret)
2067 return ret;
2068
2069 features_to_disable =
2070 features_enabled & ~new_ppfeature_masks;
2071 features_to_enable =
2072 ~features_enabled & new_ppfeature_masks;
2073
2074 pr_debug("features_to_disable 0x%"PRIx64"\n", features_to_disable);
2075 pr_debug("features_to_enable 0x%"PRIx64"\n", features_to_enable);
2076
2077 if (features_to_disable) {
2078 ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
2079 if (ret)
2080 return ret;
2081 }
2082
2083 if (features_to_enable) {
2084 ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);
2085 if (ret)
2086 return ret;
2087 }
2088
2089 return 0;
2090 }
2091
vega12_print_clock_levels(struct pp_hwmgr * hwmgr,enum pp_clock_type type,char * buf)2092 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
2093 enum pp_clock_type type, char *buf)
2094 {
2095 int i, now, size = 0;
2096 struct pp_clock_levels_with_latency clocks;
2097
2098 switch (type) {
2099 case PP_SCLK:
2100 PP_ASSERT_WITH_CODE(
2101 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
2102 "Attempt to get current gfx clk Failed!",
2103 return -1);
2104
2105 PP_ASSERT_WITH_CODE(
2106 vega12_get_sclks(hwmgr, &clocks) == 0,
2107 "Attempt to get gfx clk levels Failed!",
2108 return -1);
2109 for (i = 0; i < clocks.num_levels; i++)
2110 size += sprintf(buf + size, "%d: %uMhz %s\n",
2111 i, clocks.data[i].clocks_in_khz / 1000,
2112 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2113 break;
2114
2115 case PP_MCLK:
2116 PP_ASSERT_WITH_CODE(
2117 vega12_get_current_mclk_freq(hwmgr, &now) == 0,
2118 "Attempt to get current mclk freq Failed!",
2119 return -1);
2120
2121 PP_ASSERT_WITH_CODE(
2122 vega12_get_memclocks(hwmgr, &clocks) == 0,
2123 "Attempt to get memory clk levels Failed!",
2124 return -1);
2125 for (i = 0; i < clocks.num_levels; i++)
2126 size += sprintf(buf + size, "%d: %uMhz %s\n",
2127 i, clocks.data[i].clocks_in_khz / 1000,
2128 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2129 break;
2130
2131 case PP_SOCCLK:
2132 PP_ASSERT_WITH_CODE(
2133 smum_send_msg_to_smc_with_parameter(hwmgr,
2134 PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16)) == 0,
2135 "Attempt to get Current SOCCLK Frequency Failed!",
2136 return -EINVAL);
2137 now = smum_get_argument(hwmgr);
2138
2139 PP_ASSERT_WITH_CODE(
2140 vega12_get_socclocks(hwmgr, &clocks) == 0,
2141 "Attempt to get soc clk levels Failed!",
2142 return -1);
2143 for (i = 0; i < clocks.num_levels; i++)
2144 size += sprintf(buf + size, "%d: %uMhz %s\n",
2145 i, clocks.data[i].clocks_in_khz / 1000,
2146 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2147 break;
2148
2149 case PP_DCEFCLK:
2150 PP_ASSERT_WITH_CODE(
2151 smum_send_msg_to_smc_with_parameter(hwmgr,
2152 PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16)) == 0,
2153 "Attempt to get Current DCEFCLK Frequency Failed!",
2154 return -EINVAL);
2155 now = smum_get_argument(hwmgr);
2156
2157 PP_ASSERT_WITH_CODE(
2158 vega12_get_dcefclocks(hwmgr, &clocks) == 0,
2159 "Attempt to get dcef clk levels Failed!",
2160 return -1);
2161 for (i = 0; i < clocks.num_levels; i++)
2162 size += sprintf(buf + size, "%d: %uMhz %s\n",
2163 i, clocks.data[i].clocks_in_khz / 1000,
2164 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2165 break;
2166
2167 case PP_PCIE:
2168 break;
2169
2170 default:
2171 break;
2172 }
2173 return size;
2174 }
2175
vega12_apply_clocks_adjust_rules(struct pp_hwmgr * hwmgr)2176 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
2177 {
2178 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2179 struct vega12_single_dpm_table *dpm_table;
2180 bool vblank_too_short = false;
2181 bool disable_mclk_switching;
2182 uint32_t i, latency;
2183
2184 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2185 !hwmgr->display_config->multi_monitor_in_sync) ||
2186 vblank_too_short;
2187 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
2188
2189 /* gfxclk */
2190 dpm_table = &(data->dpm_table.gfx_table);
2191 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2192 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2193 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2194 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2195
2196 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2197 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2198 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2199 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2200 }
2201
2202 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2203 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2204 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2205 }
2206
2207 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2208 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2209 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2210 }
2211 }
2212
2213 /* memclk */
2214 dpm_table = &(data->dpm_table.mem_table);
2215 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2216 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2217 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2218 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2219
2220 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2221 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2222 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2223 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2224 }
2225
2226 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2227 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2228 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2229 }
2230
2231 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2232 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2233 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2234 }
2235 }
2236
2237 /* honour DAL's UCLK Hardmin */
2238 if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
2239 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
2240
2241 /* Hardmin is dependent on displayconfig */
2242 if (disable_mclk_switching) {
2243 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2244 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
2245 if (data->mclk_latency_table.entries[i].latency <= latency) {
2246 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
2247 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2248 break;
2249 }
2250 }
2251 }
2252 }
2253
2254 if (hwmgr->display_config->nb_pstate_switch_disable)
2255 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2256
2257 /* vclk */
2258 dpm_table = &(data->dpm_table.vclk_table);
2259 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2260 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2261 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2262 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2263
2264 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2265 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2266 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2267 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2268 }
2269
2270 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2271 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2272 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2273 }
2274 }
2275
2276 /* dclk */
2277 dpm_table = &(data->dpm_table.dclk_table);
2278 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2279 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2280 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2281 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2282
2283 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2284 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2285 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2286 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2287 }
2288
2289 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2290 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2291 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2292 }
2293 }
2294
2295 /* socclk */
2296 dpm_table = &(data->dpm_table.soc_table);
2297 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2298 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2299 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2300 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2301
2302 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2303 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2304 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2305 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2306 }
2307
2308 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2309 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2310 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2311 }
2312 }
2313
2314 /* eclk */
2315 dpm_table = &(data->dpm_table.eclk_table);
2316 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2317 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2318 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2319 dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2320
2321 if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2322 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2323 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2324 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2325 }
2326
2327 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2328 dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2329 dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2330 }
2331 }
2332
2333 return 0;
2334 }
2335
vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr * hwmgr,struct vega12_single_dpm_table * dpm_table)2336 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2337 struct vega12_single_dpm_table *dpm_table)
2338 {
2339 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2340 int ret = 0;
2341
2342 if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2343 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2344 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2345 return -EINVAL);
2346 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2347 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2348 return -EINVAL);
2349
2350 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2351 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2352 PPSMC_MSG_SetHardMinByFreq,
2353 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
2354 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2355 return ret);
2356 }
2357
2358 return ret;
2359 }
2360
vega12_pre_display_configuration_changed_task(struct pp_hwmgr * hwmgr)2361 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2362 {
2363 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2364 int ret = 0;
2365
2366 smum_send_msg_to_smc_with_parameter(hwmgr,
2367 PPSMC_MSG_NumOfDisplays, 0);
2368
2369 ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
2370 &data->dpm_table.mem_table);
2371
2372 return ret;
2373 }
2374
vega12_display_configuration_changed_task(struct pp_hwmgr * hwmgr)2375 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2376 {
2377 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2378 int result = 0;
2379 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2380
2381 if ((data->water_marks_bitmap & WaterMarksExist) &&
2382 !(data->water_marks_bitmap & WaterMarksLoaded)) {
2383 result = smum_smc_table_manager(hwmgr,
2384 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2385 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return EINVAL);
2386 data->water_marks_bitmap |= WaterMarksLoaded;
2387 }
2388
2389 if ((data->water_marks_bitmap & WaterMarksExist) &&
2390 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2391 data->smu_features[GNLD_DPM_SOCCLK].supported)
2392 smum_send_msg_to_smc_with_parameter(hwmgr,
2393 PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
2394
2395 return result;
2396 }
2397
vega12_enable_disable_uvd_dpm(struct pp_hwmgr * hwmgr,bool enable)2398 int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2399 {
2400 struct vega12_hwmgr *data =
2401 (struct vega12_hwmgr *)(hwmgr->backend);
2402
2403 if (data->smu_features[GNLD_DPM_UVD].supported) {
2404 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
2405 enable,
2406 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
2407 "Attempt to Enable/Disable DPM UVD Failed!",
2408 return -1);
2409 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2410 }
2411
2412 return 0;
2413 }
2414
vega12_power_gate_vce(struct pp_hwmgr * hwmgr,bool bgate)2415 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2416 {
2417 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2418
2419 if (data->vce_power_gated == bgate)
2420 return;
2421
2422 data->vce_power_gated = bgate;
2423 vega12_enable_disable_vce_dpm(hwmgr, !bgate);
2424 }
2425
vega12_power_gate_uvd(struct pp_hwmgr * hwmgr,bool bgate)2426 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2427 {
2428 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2429
2430 if (data->uvd_power_gated == bgate)
2431 return;
2432
2433 data->uvd_power_gated = bgate;
2434 vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
2435 }
2436
2437 static bool
vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr * hwmgr)2438 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
2439 {
2440 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2441 bool is_update_required = false;
2442
2443 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2444 is_update_required = true;
2445
2446 if (data->registry_data.gfx_clk_deep_sleep_support) {
2447 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
2448 is_update_required = true;
2449 }
2450
2451 return is_update_required;
2452 }
2453
vega12_disable_dpm_tasks(struct pp_hwmgr * hwmgr)2454 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2455 {
2456 int tmp_result, result = 0;
2457
2458 tmp_result = vega12_disable_all_smu_features(hwmgr);
2459 PP_ASSERT_WITH_CODE((tmp_result == 0),
2460 "Failed to disable all smu features!", result = tmp_result);
2461
2462 return result;
2463 }
2464
vega12_power_off_asic(struct pp_hwmgr * hwmgr)2465 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
2466 {
2467 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2468 int result;
2469
2470 result = vega12_disable_dpm_tasks(hwmgr);
2471 PP_ASSERT_WITH_CODE((0 == result),
2472 "[disable_dpm_tasks] Failed to disable DPM!",
2473 );
2474 data->water_marks_bitmap &= ~(WaterMarksLoaded);
2475
2476 return result;
2477 }
2478
2479 #if 0
2480 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2481 uint32_t *sclk_idx, uint32_t *mclk_idx,
2482 uint32_t min_sclk, uint32_t min_mclk)
2483 {
2484 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2485 struct vega12_dpm_table *dpm_table = &(data->dpm_table);
2486 uint32_t i;
2487
2488 for (i = 0; i < dpm_table->gfx_table.count; i++) {
2489 if (dpm_table->gfx_table.dpm_levels[i].enabled &&
2490 dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
2491 *sclk_idx = i;
2492 break;
2493 }
2494 }
2495
2496 for (i = 0; i < dpm_table->mem_table.count; i++) {
2497 if (dpm_table->mem_table.dpm_levels[i].enabled &&
2498 dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
2499 *mclk_idx = i;
2500 break;
2501 }
2502 }
2503 }
2504 #endif
2505
2506 #if 0
2507 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2508 struct amd_pp_profile *request)
2509 {
2510 return 0;
2511 }
2512
2513 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2514 {
2515 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2516 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2517 struct vega12_single_dpm_table *golden_sclk_table =
2518 &(data->golden_dpm_table.gfx_table);
2519 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2520 int golden_value = golden_sclk_table->dpm_levels
2521 [golden_sclk_table->count - 1].value;
2522
2523 value -= golden_value;
2524 value = DIV_ROUND_UP(value * 100, golden_value);
2525
2526 return value;
2527 }
2528
2529 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2530 {
2531 return 0;
2532 }
2533
2534 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2535 {
2536 struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2537 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2538 struct vega12_single_dpm_table *golden_mclk_table =
2539 &(data->golden_dpm_table.mem_table);
2540 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2541 int golden_value = golden_mclk_table->dpm_levels
2542 [golden_mclk_table->count - 1].value;
2543
2544 value -= golden_value;
2545 value = DIV_ROUND_UP(value * 100, golden_value);
2546
2547 return value;
2548 }
2549
2550 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2551 {
2552 return 0;
2553 }
2554 #endif
2555
vega12_notify_cac_buffer_info(struct pp_hwmgr * hwmgr,uint32_t virtual_addr_low,uint32_t virtual_addr_hi,uint32_t mc_addr_low,uint32_t mc_addr_hi,uint32_t size)2556 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
2557 uint32_t virtual_addr_low,
2558 uint32_t virtual_addr_hi,
2559 uint32_t mc_addr_low,
2560 uint32_t mc_addr_hi,
2561 uint32_t size)
2562 {
2563 smum_send_msg_to_smc_with_parameter(hwmgr,
2564 PPSMC_MSG_SetSystemVirtualDramAddrHigh,
2565 virtual_addr_hi);
2566 smum_send_msg_to_smc_with_parameter(hwmgr,
2567 PPSMC_MSG_SetSystemVirtualDramAddrLow,
2568 virtual_addr_low);
2569 smum_send_msg_to_smc_with_parameter(hwmgr,
2570 PPSMC_MSG_DramLogSetDramAddrHigh,
2571 mc_addr_hi);
2572
2573 smum_send_msg_to_smc_with_parameter(hwmgr,
2574 PPSMC_MSG_DramLogSetDramAddrLow,
2575 mc_addr_low);
2576
2577 smum_send_msg_to_smc_with_parameter(hwmgr,
2578 PPSMC_MSG_DramLogSetDramSize,
2579 size);
2580 return 0;
2581 }
2582
vega12_get_thermal_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * thermal_data)2583 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2584 struct PP_TemperatureRange *thermal_data)
2585 {
2586 struct vega12_hwmgr *data =
2587 (struct vega12_hwmgr *)(hwmgr->backend);
2588 PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2589
2590 memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
2591
2592 thermal_data->max = pp_table->TedgeLimit *
2593 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2594 thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
2595 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2596 thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
2597 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2598 thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2599 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2600 thermal_data->mem_crit_max = pp_table->ThbmLimit *
2601 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2602 thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
2603 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2604
2605 return 0;
2606 }
2607
vega12_enable_gfx_off(struct pp_hwmgr * hwmgr)2608 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
2609 {
2610 struct vega12_hwmgr *data =
2611 (struct vega12_hwmgr *)(hwmgr->backend);
2612 int ret = 0;
2613
2614 if (data->gfxoff_controlled_by_driver)
2615 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff);
2616
2617 return ret;
2618 }
2619
vega12_disable_gfx_off(struct pp_hwmgr * hwmgr)2620 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
2621 {
2622 struct vega12_hwmgr *data =
2623 (struct vega12_hwmgr *)(hwmgr->backend);
2624 int ret = 0;
2625
2626 if (data->gfxoff_controlled_by_driver)
2627 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff);
2628
2629 return ret;
2630 }
2631
vega12_gfx_off_control(struct pp_hwmgr * hwmgr,bool enable)2632 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
2633 {
2634 if (enable)
2635 return vega12_enable_gfx_off(hwmgr);
2636 else
2637 return vega12_disable_gfx_off(hwmgr);
2638 }
2639
vega12_get_performance_level(struct pp_hwmgr * hwmgr,const struct pp_hw_power_state * state,PHM_PerformanceLevelDesignation designation,uint32_t index,PHM_PerformanceLevel * level)2640 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2641 PHM_PerformanceLevelDesignation designation, uint32_t index,
2642 PHM_PerformanceLevel *level)
2643 {
2644 return 0;
2645 }
2646
vega12_set_mp1_state(struct pp_hwmgr * hwmgr,enum pp_mp1_state mp1_state)2647 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
2648 enum pp_mp1_state mp1_state)
2649 {
2650 uint16_t msg;
2651 int ret;
2652
2653 switch (mp1_state) {
2654 case PP_MP1_STATE_UNLOAD:
2655 msg = PPSMC_MSG_PrepareMp1ForUnload;
2656 break;
2657 case PP_MP1_STATE_SHUTDOWN:
2658 case PP_MP1_STATE_RESET:
2659 case PP_MP1_STATE_NONE:
2660 default:
2661 return 0;
2662 }
2663
2664 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
2665 "[PrepareMp1] Failed!",
2666 return ret);
2667
2668 return 0;
2669 }
2670
2671 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2672 .backend_init = vega12_hwmgr_backend_init,
2673 .backend_fini = vega12_hwmgr_backend_fini,
2674 .asic_setup = vega12_setup_asic_task,
2675 .dynamic_state_management_enable = vega12_enable_dpm_tasks,
2676 .dynamic_state_management_disable = vega12_disable_dpm_tasks,
2677 .patch_boot_state = vega12_patch_boot_state,
2678 .get_sclk = vega12_dpm_get_sclk,
2679 .get_mclk = vega12_dpm_get_mclk,
2680 .notify_smc_display_config_after_ps_adjustment =
2681 vega12_notify_smc_display_config_after_ps_adjustment,
2682 .force_dpm_level = vega12_dpm_force_dpm_level,
2683 .stop_thermal_controller = vega12_thermal_stop_thermal_controller,
2684 .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
2685 .reset_fan_speed_to_default =
2686 vega12_fan_ctrl_reset_fan_speed_to_default,
2687 .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
2688 .set_fan_control_mode = vega12_set_fan_control_mode,
2689 .get_fan_control_mode = vega12_get_fan_control_mode,
2690 .read_sensor = vega12_read_sensor,
2691 .get_dal_power_level = vega12_get_dal_power_level,
2692 .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
2693 .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
2694 .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
2695 .display_clock_voltage_request = vega12_display_clock_voltage_request,
2696 .force_clock_level = vega12_force_clock_level,
2697 .print_clock_levels = vega12_print_clock_levels,
2698 .apply_clocks_adjust_rules =
2699 vega12_apply_clocks_adjust_rules,
2700 .pre_display_config_changed =
2701 vega12_pre_display_configuration_changed_task,
2702 .display_config_changed = vega12_display_configuration_changed_task,
2703 .powergate_uvd = vega12_power_gate_uvd,
2704 .powergate_vce = vega12_power_gate_vce,
2705 .check_smc_update_required_for_display_configuration =
2706 vega12_check_smc_update_required_for_display_configuration,
2707 .power_off_asic = vega12_power_off_asic,
2708 .disable_smc_firmware_ctf = vega12_thermal_disable_alert,
2709 #if 0
2710 .set_power_profile_state = vega12_set_power_profile_state,
2711 .get_sclk_od = vega12_get_sclk_od,
2712 .set_sclk_od = vega12_set_sclk_od,
2713 .get_mclk_od = vega12_get_mclk_od,
2714 .set_mclk_od = vega12_set_mclk_od,
2715 #endif
2716 .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2717 .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2718 .register_irq_handlers = smu9_register_irq_handlers,
2719 .start_thermal_controller = vega12_start_thermal_controller,
2720 .powergate_gfx = vega12_gfx_off_control,
2721 .get_performance_level = vega12_get_performance_level,
2722 .get_asic_baco_capability = smu9_baco_get_capability,
2723 .get_asic_baco_state = smu9_baco_get_state,
2724 .set_asic_baco_state = vega12_baco_set_state,
2725 .get_ppfeature_status = vega12_get_ppfeature_status,
2726 .set_ppfeature_status = vega12_set_ppfeature_status,
2727 .set_mp1_state = vega12_set_mp1_state,
2728 };
2729
vega12_hwmgr_init(struct pp_hwmgr * hwmgr)2730 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
2731 {
2732 hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
2733 hwmgr->pptable_func = &vega12_pptable_funcs;
2734
2735 return 0;
2736 }
2737