1 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the ARM specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 14 #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 15 16 #include "ARMBaseInstrInfo.h" 17 #include "ARMBaseRegisterInfo.h" 18 #include "ARMConstantPoolValue.h" 19 #include "ARMFrameLowering.h" 20 #include "ARMISelLowering.h" 21 #include "ARMMachineFunctionInfo.h" 22 #include "ARMSelectionDAGInfo.h" 23 #include "llvm/Analysis/TargetTransformInfo.h" 24 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 25 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 26 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/RegisterBankInfo.h" 29 #include "llvm/CodeGen/TargetSubtargetInfo.h" 30 #include "llvm/MC/MCInstrItineraries.h" 31 #include "llvm/MC/MCSchedule.h" 32 #include "llvm/Target/TargetMachine.h" 33 #include "llvm/Target/TargetOptions.h" 34 #include "llvm/TargetParser/Triple.h" 35 #include <bitset> 36 #include <memory> 37 #include <string> 38 39 #define GET_SUBTARGETINFO_HEADER 40 #include "ARMGenSubtargetInfo.inc" 41 42 namespace llvm { 43 44 class ARMBaseTargetMachine; 45 class GlobalValue; 46 class StringRef; 47 48 class ARMSubtarget : public ARMGenSubtargetInfo { 49 protected: 50 enum ARMProcFamilyEnum { 51 Others, 52 #define ARM_PROCESSOR_FAMILY(ENUM) ENUM, 53 #include "llvm/TargetParser/ARMTargetParserDef.inc" 54 #undef ARM_PROCESSOR_FAMILY 55 }; 56 enum ARMProcClassEnum { 57 None, 58 59 AClass, 60 MClass, 61 RClass 62 }; 63 enum ARMArchEnum { 64 #define ARM_ARCHITECTURE(ENUM) ENUM, 65 #include "llvm/TargetParser/ARMTargetParserDef.inc" 66 #undef ARM_ARCHITECTURE 67 }; 68 69 public: 70 /// What kind of timing do load multiple/store multiple instructions have. 71 enum ARMLdStMultipleTiming { 72 /// Can load/store 2 registers/cycle. 73 DoubleIssue, 74 /// Can load/store 2 registers/cycle, but needs an extra cycle if the access 75 /// is not 64-bit aligned. 76 DoubleIssueCheckUnalignedAccess, 77 /// Can load/store 1 register/cycle. 78 SingleIssue, 79 /// Can load/store 1 register/cycle, but needs an extra cycle for address 80 /// computation and potentially also for register writeback. 81 SingleIssuePlusExtras, 82 }; 83 84 /// How the push and pop instructions of callee saved general-purpose 85 /// registers should be split. 86 enum PushPopSplitVariation { 87 /// All GPRs can be pushed in a single instruction. 88 /// push {r0-r12, lr} 89 /// vpush {d8-d15} 90 NoSplit, 91 92 /// R7 and LR must be adjacent, because R7 is the frame pointer, and must 93 /// point to a frame record consisting of the previous frame pointer and the 94 /// return address. 95 /// push {r0-r7, lr} 96 /// push {r8-r12} 97 /// vpush {d8-d15} 98 /// Note that Thumb1 changes this layout when the frame pointer is R11, 99 /// using a longer sequence of instructions because R11 can't be used by a 100 /// Thumb1 push instruction. This doesn't currently have a separate enum 101 /// value, and is handled entriely within Thumb1FrameLowering::emitPrologue. 102 SplitR7, 103 104 /// When the stack frame size is not known (because of variable-sized 105 /// objects or realignment), Windows SEH requires the callee-saved registers 106 /// to be stored in three regions, with R11 and LR below the floating-point 107 /// registers. 108 /// push {r0-r10, r12} 109 /// vpush {d8-d15} 110 /// push {r11, lr} 111 SplitR11WindowsSEH, 112 113 /// When generating AAPCS-compilant frame chains, R11 is the frame pointer, 114 /// and must be pushed adjacent to the return address (LR). Normally this 115 /// isn't a problem, because the only register between them is r12, which is 116 /// the intra-procedure-call scratch register, so doesn't need to be saved. 117 /// However, when PACBTI is in use, r12 contains the authentication code, so 118 /// does need to be saved. This means that we need a separate push for R11 119 /// and LR. 120 /// push {r0-r10, r12} 121 /// push {r11, lr} 122 /// vpush {d8-d15} 123 SplitR11AAPCSSignRA, 124 }; 125 126 protected: 127 // Bool members corresponding to the SubtargetFeatures defined in tablegen 128 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ 129 bool ATTRIBUTE = DEFAULT; 130 #include "ARMGenSubtargetInfo.inc" 131 132 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 133 ARMProcFamilyEnum ARMProcFamily = Others; 134 135 /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass. 136 ARMProcClassEnum ARMProcClass = None; 137 138 /// ARMArch - ARM architecture 139 ARMArchEnum ARMArch = ARMv4t; 140 141 /// UseMulOps - True if non-microcoded fused integer multiply-add and 142 /// multiply-subtract instructions should be used. 143 bool UseMulOps = false; 144 145 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker 146 /// must be able to synthesize call stubs for interworking between ARM and 147 /// Thumb. 148 bool SupportsTailCall = false; 149 150 /// RestrictIT - If true, the subtarget disallows generation of complex IT 151 /// blocks. 152 bool RestrictIT = false; 153 154 /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). 155 bool UseSjLjEH = false; 156 157 /// stackAlignment - The minimum alignment known to hold of the stack frame on 158 /// entry to the function and which must be maintained by every function. 159 Align stackAlignment = Align(4); 160 161 /// CPUString - String name of used CPU. 162 std::string CPUString; 163 164 unsigned MaxInterleaveFactor = 1; 165 166 /// Clearance before partial register updates (in number of instructions) 167 unsigned PartialUpdateClearance = 0; 168 169 /// What kind of timing do load multiple/store multiple have (double issue, 170 /// single issue etc). 171 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue; 172 173 /// The adjustment that we need to apply to get the operand latency from the 174 /// operand cycle returned by the itinerary data for pre-ISel operands. 175 int PreISelOperandLatencyAdjustment = 2; 176 177 /// What alignment is preferred for loop bodies and functions, in log2(bytes). 178 unsigned PreferBranchLogAlignment = 0; 179 180 /// The cost factor for MVE instructions, representing the multiple beats an 181 // instruction can take. The default is 2, (set in initSubtargetFeatures so 182 // that we can use subtarget features less than 2). 183 unsigned MVEVectorCostFactor = 0; 184 185 /// OptMinSize - True if we're optimising for minimum code size, equal to 186 /// the function attribute. 187 bool OptMinSize = false; 188 189 /// IsLittle - The target is Little Endian 190 bool IsLittle; 191 192 /// TargetTriple - What processor and OS we're targeting. 193 Triple TargetTriple; 194 195 /// SchedModel - Processor specific instruction costs. 196 MCSchedModel SchedModel; 197 198 /// Selected instruction itineraries (one entry per itinerary class.) 199 InstrItineraryData InstrItins; 200 201 /// Options passed via command line that could influence the target 202 const TargetOptions &Options; 203 204 const ARMBaseTargetMachine &TM; 205 206 public: 207 /// This constructor initializes the data members to match that 208 /// of the specified triple. 209 /// 210 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, 211 const ARMBaseTargetMachine &TM, bool IsLittle, 212 bool MinSize = false); 213 214 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 215 /// that still makes it profitable to inline the call. 216 unsigned getMaxInlineSizeThreshold() const { 217 return 64; 218 } 219 220 /// getMaxMemcpyTPInlineSizeThreshold - Returns the maximum size 221 /// that still makes it profitable to inline a llvm.memcpy as a Tail 222 /// Predicated loop. 223 /// This threshold should only be used for constant size inputs. 224 unsigned getMaxMemcpyTPInlineSizeThreshold() const { return 128; } 225 226 /// ParseSubtargetFeatures - Parses features string setting specified 227 /// subtarget options. Definition of function is auto generated by tblgen. 228 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 229 230 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 231 /// so that we can use initializer lists for subtarget initialization. 232 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 233 234 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override { 235 return &TSInfo; 236 } 237 238 const ARMBaseInstrInfo *getInstrInfo() const override { 239 return InstrInfo.get(); 240 } 241 242 const ARMTargetLowering *getTargetLowering() const override { 243 return &TLInfo; 244 } 245 246 const ARMFrameLowering *getFrameLowering() const override { 247 return FrameLowering.get(); 248 } 249 250 const ARMBaseRegisterInfo *getRegisterInfo() const override { 251 return &InstrInfo->getRegisterInfo(); 252 } 253 254 const CallLowering *getCallLowering() const override; 255 InstructionSelector *getInstructionSelector() const override; 256 const LegalizerInfo *getLegalizerInfo() const override; 257 const RegisterBankInfo *getRegBankInfo() const override; 258 259 private: 260 ARMSelectionDAGInfo TSInfo; 261 // Either Thumb1FrameLowering or ARMFrameLowering. 262 std::unique_ptr<ARMFrameLowering> FrameLowering; 263 // Either Thumb1InstrInfo or Thumb2InstrInfo. 264 std::unique_ptr<ARMBaseInstrInfo> InstrInfo; 265 ARMTargetLowering TLInfo; 266 267 /// GlobalISel related APIs. 268 std::unique_ptr<CallLowering> CallLoweringInfo; 269 std::unique_ptr<InstructionSelector> InstSelector; 270 std::unique_ptr<LegalizerInfo> Legalizer; 271 std::unique_ptr<RegisterBankInfo> RegBankInfo; 272 273 void initializeEnvironment(); 274 void initSubtargetFeatures(StringRef CPU, StringRef FS); 275 ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS); 276 277 std::bitset<8> CoprocCDE = {}; 278 public: 279 // Getters for SubtargetFeatures defined in tablegen 280 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ 281 bool GETTER() const { return ATTRIBUTE; } 282 #include "ARMGenSubtargetInfo.inc" 283 284 /// @{ 285 /// These functions are obsolete, please consider adding subtarget features 286 /// or properties instead of calling them. 287 bool isCortexA5() const { return ARMProcFamily == CortexA5; } 288 bool isCortexA7() const { return ARMProcFamily == CortexA7; } 289 bool isCortexA8() const { return ARMProcFamily == CortexA8; } 290 bool isCortexA9() const { return ARMProcFamily == CortexA9; } 291 bool isCortexA15() const { return ARMProcFamily == CortexA15; } 292 bool isSwift() const { return ARMProcFamily == Swift; } 293 bool isCortexM3() const { return ARMProcFamily == CortexM3; } 294 bool isCortexM55() const { return ARMProcFamily == CortexM55; } 295 bool isCortexM7() const { return ARMProcFamily == CortexM7; } 296 bool isCortexM85() const { return ARMProcFamily == CortexM85; } 297 bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); } 298 bool isCortexR5() const { return ARMProcFamily == CortexR5; } 299 bool isKrait() const { return ARMProcFamily == Krait; } 300 /// @} 301 302 bool hasARMOps() const { return !NoARM; } 303 304 bool useNEONForSinglePrecisionFP() const { 305 return hasNEON() && hasNEONForFP(); 306 } 307 308 bool hasVFP2Base() const { return hasVFPv2SP(); } 309 bool hasVFP3Base() const { return hasVFPv3D16SP(); } 310 bool hasVFP4Base() const { return hasVFPv4D16SP(); } 311 bool hasFPARMv8Base() const { return hasFPARMv8D16SP(); } 312 313 bool hasAnyDataBarrier() const { 314 return HasDataBarrier || (hasV6Ops() && !isThumb()); 315 } 316 317 bool useMulOps() const { return UseMulOps; } 318 bool useFPVMLx() const { return !SlowFPVMLx; } 319 bool useFPVFMx() const { 320 return !isTargetDarwin() && hasVFP4Base() && !SlowFPVFMx; 321 } 322 bool useFPVFMx16() const { return useFPVFMx() && hasFullFP16(); } 323 bool useFPVFMx64() const { return useFPVFMx() && hasFP64(); } 324 bool useSjLjEH() const { return UseSjLjEH; } 325 bool hasBaseDSP() const { 326 if (isThumb()) 327 return hasThumb2() && hasDSP(); 328 else 329 return hasV5TEOps(); 330 } 331 332 /// Return true if the CPU supports any kind of instruction fusion. 333 bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); } 334 335 const Triple &getTargetTriple() const { return TargetTriple; } 336 337 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 338 bool isTargetIOS() const { return TargetTriple.isiOS(); } 339 bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); } 340 bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); } 341 bool isTargetDriverKit() const { return TargetTriple.isDriverKit(); } 342 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } 343 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 344 bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); } 345 bool isTargetWindows() const { return TargetTriple.isOSWindows(); } 346 347 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 348 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 349 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 350 351 // ARM EABI is the bare-metal EABI described in ARM ABI documents and 352 // can be accessed via -target arm-none-eabi. This is NOT GNUEABI. 353 // FIXME: Add a flag for bare-metal for that target and set Triple::EABI 354 // even for GNUEABI, so we can make a distinction here and still conform to 355 // the EABI on GNU (and Android) mode. This requires change in Clang, too. 356 // FIXME: The Darwin exception is temporary, while we move users to 357 // "*-*-*-macho" triples as quickly as possible. 358 bool isTargetAEABI() const { 359 return (TargetTriple.getEnvironment() == Triple::EABI || 360 TargetTriple.getEnvironment() == Triple::EABIHF) && 361 !isTargetDarwin() && !isTargetWindows(); 362 } 363 bool isTargetGNUAEABI() const { 364 return (TargetTriple.getEnvironment() == Triple::GNUEABI || 365 TargetTriple.getEnvironment() == Triple::GNUEABIT64 || 366 TargetTriple.getEnvironment() == Triple::GNUEABIHF || 367 TargetTriple.getEnvironment() == Triple::GNUEABIHFT64) && 368 !isTargetDarwin() && !isTargetWindows(); 369 } 370 bool isTargetMuslAEABI() const { 371 return (TargetTriple.getEnvironment() == Triple::MuslEABI || 372 TargetTriple.getEnvironment() == Triple::MuslEABIHF || 373 TargetTriple.getEnvironment() == Triple::OpenHOS) && 374 !isTargetDarwin() && !isTargetWindows(); 375 } 376 377 // ARM Targets that support EHABI exception handling standard 378 // Darwin uses SjLj. Other targets might need more checks. 379 bool isTargetEHABICompatible() const { 380 return TargetTriple.isTargetEHABICompatible(); 381 } 382 383 bool isTargetHardFloat() const; 384 385 bool isReadTPSoft() const { 386 return !(isReadTPTPIDRURW() || isReadTPTPIDRURO() || isReadTPTPIDRPRW()); 387 } 388 389 bool isTargetAndroid() const { return TargetTriple.isAndroid(); } 390 391 bool isXRaySupported() const override; 392 393 bool isAPCS_ABI() const; 394 bool isAAPCS_ABI() const; 395 bool isAAPCS16_ABI() const; 396 397 bool isROPI() const; 398 bool isRWPI() const; 399 400 bool useMachineScheduler() const { return UseMISched; } 401 bool useMachinePipeliner() const { return UseMIPipeliner; } 402 bool hasMinSize() const { return OptMinSize; } 403 bool isThumb1Only() const { return isThumb() && !hasThumb2(); } 404 bool isThumb2() const { return isThumb() && hasThumb2(); } 405 bool isMClass() const { return ARMProcClass == MClass; } 406 bool isRClass() const { return ARMProcClass == RClass; } 407 bool isAClass() const { return ARMProcClass == AClass; } 408 409 bool isR9Reserved() const { 410 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9; 411 } 412 413 MCPhysReg getFramePointerReg() const { 414 if (isTargetDarwin() || 415 (!isTargetWindows() && isThumb() && !createAAPCSFrameChain())) 416 return ARM::R7; 417 return ARM::R11; 418 } 419 420 enum PushPopSplitVariation 421 getPushPopSplitVariation(const MachineFunction &MF) const; 422 423 bool useStride4VFPs() const; 424 425 bool useMovt() const; 426 427 bool supportsTailCall() const { return SupportsTailCall; } 428 429 bool allowsUnalignedMem() const { return !StrictAlign; } 430 431 bool restrictIT() const { return RestrictIT; } 432 433 const std::string & getCPUString() const { return CPUString; } 434 435 bool isLittle() const { return IsLittle; } 436 437 unsigned getMispredictionPenalty() const; 438 439 /// Returns true if machine scheduler should be enabled. 440 bool enableMachineScheduler() const override; 441 442 /// Returns true if machine pipeliner should be enabled. 443 bool enableMachinePipeliner() const override; 444 bool useDFAforSMS() const override; 445 446 /// True for some subtargets at > -O0. 447 bool enablePostRAScheduler() const override; 448 449 /// True for some subtargets at > -O0. 450 bool enablePostRAMachineScheduler() const override; 451 452 /// Check whether this subtarget wants to use subregister liveness. 453 bool enableSubRegLiveness() const override; 454 455 /// Enable use of alias analysis during code generation (during MI 456 /// scheduling, DAGCombine, etc.). 457 bool useAA() const override { return true; } 458 459 /// getInstrItins - Return the instruction itineraries based on subtarget 460 /// selection. 461 const InstrItineraryData *getInstrItineraryData() const override { 462 return &InstrItins; 463 } 464 465 /// getStackAlignment - Returns the minimum alignment known to hold of the 466 /// stack frame on entry to the function and which must be maintained by every 467 /// function for this subtarget. 468 Align getStackAlignment() const { return stackAlignment; } 469 470 // Returns the required alignment for LDRD/STRD instructions 471 Align getDualLoadStoreAlignment() const { 472 return Align(hasV7Ops() || allowsUnalignedMem() ? 4 : 8); 473 } 474 475 unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; } 476 477 unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; } 478 479 ARMLdStMultipleTiming getLdStMultipleTiming() const { 480 return LdStMultipleTiming; 481 } 482 483 int getPreISelOperandLatencyAdjustment() const { 484 return PreISelOperandLatencyAdjustment; 485 } 486 487 /// True if the GV will be accessed via an indirect symbol. 488 bool isGVIndirectSymbol(const GlobalValue *GV) const; 489 490 /// Returns the constant pool modifier needed to access the GV. 491 bool isGVInGOT(const GlobalValue *GV) const; 492 493 /// True if fast-isel is used. 494 bool useFastISel() const; 495 496 /// Returns the correct return opcode for the current feature set. 497 /// Use BX if available to allow mixing thumb/arm code, but fall back 498 /// to plain mov pc,lr on ARMv4. 499 unsigned getReturnOpcode() const { 500 if (isThumb()) 501 return ARM::tBX_RET; 502 if (hasV4TOps()) 503 return ARM::BX_RET; 504 return ARM::MOVPCLR; 505 } 506 507 /// Allow movt+movw for PIC global address calculation. 508 /// ELF does not have GOT relocations for movt+movw. 509 /// ROPI does not use GOT. 510 bool allowPositionIndependentMovt() const { 511 return isROPI() || !isTargetELF(); 512 } 513 514 unsigned getPreferBranchLogAlignment() const { 515 return PreferBranchLogAlignment; 516 } 517 518 unsigned 519 getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const { 520 if (CostKind == TargetTransformInfo::TCK_CodeSize) 521 return 1; 522 return MVEVectorCostFactor; 523 } 524 525 bool ignoreCSRForAllocationOrder(const MachineFunction &MF, 526 MCRegister PhysReg) const override; 527 unsigned getGPRAllocationOrder(const MachineFunction &MF) const; 528 }; 529 530 } // end namespace llvm 531 532 #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H 533