1 /* $OpenBSD: atw.c,v 1.102 2024/10/06 01:12:15 jsg Exp $ */ 2 /* $NetBSD: atw.c,v 1.69 2004/07/23 07:07:55 dyoung Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP. 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/mbuf.h> 42 #include <sys/malloc.h> 43 #include <sys/kernel.h> 44 #include <sys/socket.h> 45 #include <sys/ioctl.h> 46 #include <sys/errno.h> 47 #include <sys/device.h> 48 #include <sys/time.h> 49 #include <sys/endian.h> 50 51 #include <net/if.h> 52 #include <net/if_media.h> 53 54 #if NBPFILTER > 0 55 #include <net/bpf.h> 56 #endif 57 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 61 #include <net80211/ieee80211_var.h> 62 #include <net80211/ieee80211_radiotap.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 67 #include <dev/ic/atwreg.h> 68 #include <dev/ic/rf3000reg.h> 69 #include <dev/ic/si4136reg.h> 70 #include <dev/ic/atwvar.h> 71 #include <dev/ic/smc93cx6var.h> 72 73 /* XXX TBD open questions 74 * 75 * 76 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps 77 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC 78 * handle this for me? 79 * 80 */ 81 /* device attachment 82 * 83 * print TOFS[012] 84 * 85 * device initialization 86 * 87 * clear ATW_FRCTL_MAXPSP to disable max power saving 88 * set ATW_TXBR_ALCUPDATE to enable ALC 89 * set TOFS[012]? (hope not) 90 * disable rx/tx 91 * set ATW_PAR_SWR (software reset) 92 * wait for ATW_PAR_SWR clear 93 * disable interrupts 94 * ack status register 95 * enable interrupts 96 * 97 * rx/tx initialization 98 * 99 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 100 * allocate and init descriptor rings 101 * write ATW_PAR_DSL (descriptor skip length) 102 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB 103 * write ATW_NAR_SQ for one/both transmit descriptor rings 104 * write ATW_NAR_SQ for one/both transmit descriptor rings 105 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 106 * 107 * rx/tx end 108 * 109 * stop DMA 110 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST 111 * flush tx w/ ATW_NAR_HF 112 * 113 * scan 114 * 115 * initialize rx/tx 116 * 117 * BSS join: (re)association response 118 * 119 * set ATW_FRCTL_AID 120 * 121 * optimizations ??? 122 * 123 */ 124 125 #define ATW_REFSLAVE /* slavishly do what the reference driver does */ 126 127 int atw_bbp_io_enable_delay = 20 * 1000; 128 int atw_bbp_io_disable_delay = 2 * 1000; 129 int atw_writewep_delay = 1000; 130 int atw_dwelltime = 200; 131 int atw_xindiv2 = 0; 132 133 #ifdef ATW_DEBUG 134 int atw_debug = 0; 135 136 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x 137 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x 138 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x 139 #define DPRINTF(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) printf x 140 #define DPRINTF2(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x) 141 #define DPRINTF3(sc, x) if ((sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x) 142 void atw_print_regs(struct atw_softc *, const char *); 143 void atw_dump_pkt(struct ifnet *, struct mbuf *); 144 145 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */ 146 # ifdef ATW_BBPDEBUG 147 int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *); 148 void atw_rf3000_print(struct atw_softc *); 149 # endif /* ATW_BBPDEBUG */ 150 151 # ifdef ATW_SYNDEBUG 152 int atw_si4126_read(struct atw_softc *, u_int, u_int *); 153 void atw_si4126_print(struct atw_softc *); 154 # endif /* ATW_SYNDEBUG */ 155 156 #else 157 #define ATW_DPRINTF(x) 158 #define ATW_DPRINTF2(x) 159 #define ATW_DPRINTF3(x) 160 #define DPRINTF(sc, x) /* nothing */ 161 #define DPRINTF2(sc, x) /* nothing */ 162 #define DPRINTF3(sc, x) /* nothing */ 163 #endif 164 165 const char *atw_printmac(u_int8_t); 166 167 /* ifnet methods */ 168 void atw_start(struct ifnet *); 169 void atw_watchdog(struct ifnet *); 170 int atw_ioctl(struct ifnet *, u_long, caddr_t); 171 int atw_init(struct ifnet *); 172 void atw_stop(struct ifnet *, int); 173 174 /* Rx/Tx process */ 175 void atw_rxdrain(struct atw_softc *); 176 void atw_txdrain(struct atw_softc *); 177 int atw_add_rxbuf(struct atw_softc *, int); 178 void atw_idle(struct atw_softc *, u_int32_t); 179 180 /* Device (de)activation and power state */ 181 void atw_disable(struct atw_softc *); 182 void atw_reset(struct atw_softc *); 183 184 /* Interrupt handlers */ 185 void atw_rxintr(struct atw_softc *); 186 void atw_txintr(struct atw_softc *); 187 void atw_linkintr(struct atw_softc *, u_int32_t); 188 189 /* 802.11 state machine */ 190 int atw_newstate(struct ieee80211com *, enum ieee80211_state, int); 191 int atw_tune(struct atw_softc *); 192 #ifndef IEEE80211_STA_ONLY 193 void atw_recv_mgmt(struct ieee80211com *, struct mbuf *, 194 struct ieee80211_node *, struct ieee80211_rxinfo *, int); 195 #endif 196 void atw_next_scan(void *); 197 198 /* Device initialization */ 199 void atw_wcsr_init(struct atw_softc *); 200 void atw_cmdr_init(struct atw_softc *); 201 void atw_tofs2_init(struct atw_softc *); 202 void atw_txlmt_init(struct atw_softc *); 203 void atw_test1_init(struct atw_softc *); 204 void atw_rf_reset(struct atw_softc *); 205 void atw_cfp_init(struct atw_softc *); 206 void atw_tofs0_init(struct atw_softc *); 207 void atw_ifs_init(struct atw_softc *); 208 void atw_response_times_init(struct atw_softc *); 209 void atw_bbp_io_init(struct atw_softc *); 210 void atw_nar_init(struct atw_softc *); 211 212 /* RAM/ROM utilities */ 213 void atw_clear_sram(struct atw_softc *); 214 void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int); 215 int atw_read_srom(struct atw_softc *); 216 217 /* BSS setup */ 218 void atw_predict_beacon(struct atw_softc *sc); 219 void atw_start_beacon(struct atw_softc *, int); 220 void atw_write_bssid(struct atw_softc *); 221 void atw_write_ssid(struct atw_softc *); 222 void atw_write_sup_rates(struct atw_softc *); 223 void atw_write_wep(struct atw_softc *); 224 225 /* Media */ 226 int atw_media_change(struct ifnet *); 227 void atw_media_status(struct ifnet *, struct ifmediareq *); 228 229 void atw_filter_setup(struct atw_softc *); 230 231 /* 802.11 utilities */ 232 struct ieee80211_node *atw_node_alloc(struct ieee80211com *); 233 void atw_node_free(struct ieee80211com *, struct ieee80211_node *); 234 static __inline uint32_t atw_last_even_tsft(uint32_t, uint32_t, uint32_t); 235 uint64_t atw_get_tsft(struct atw_softc *sc); 236 void atw_change_ibss(struct atw_softc *); 237 int atw_compute_duration1(int, int, uint32_t, int, struct atw_duration *); 238 int atw_compute_duration(struct ieee80211_frame *, int, uint32_t, int, 239 int, struct atw_duration *, struct atw_duration *, int *, int); 240 241 /* 242 * Tuner/transceiver/modem 243 */ 244 void atw_bbp_io_enable(struct atw_softc *, int); 245 246 /* RFMD RF3000 Baseband Processor */ 247 int atw_rf3000_init(struct atw_softc *); 248 int atw_rf3000_tune(struct atw_softc *, u_int); 249 int atw_rf3000_write(struct atw_softc *, u_int, u_int); 250 251 /* Silicon Laboratories Si4126 RF/IF Synthesizer */ 252 void atw_si4126_tune(struct atw_softc *, u_int); 253 void atw_si4126_write(struct atw_softc *, u_int, u_int); 254 void atw_si4126_init(struct atw_softc *); 255 256 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = { 257 { ATW_NAR_TR_L64, "64 bytes" }, 258 { ATW_NAR_TR_L160, "160 bytes" }, 259 { ATW_NAR_TR_L192, "192 bytes" }, 260 { ATW_NAR_SF, "store and forward" }, 261 { 0, NULL } 262 }; 263 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = { 264 { ATW_NAR_TR_H96, "96 bytes" }, 265 { ATW_NAR_TR_H288, "288 bytes" }, 266 { ATW_NAR_TR_H544, "544 bytes" }, 267 { ATW_NAR_SF, "store and forward" }, 268 { 0, NULL } 269 }; 270 271 struct cfdriver atw_cd = { 272 NULL, "atw", DV_IFNET 273 }; 274 275 static const u_int atw_rfmd2958_ifn[] = { 276 0x22bd, 0x22d2, 0x22e8, 0x22fe, 0x2314, 0x232a, 0x2340, 277 0x2355, 0x236b, 0x2381, 0x2397, 0x23ad, 0x23c2, 0x23f7 278 }; 279 280 static const u_int atw_rfmd2958_rf1r[] = { 281 0x05d17, 0x3a2e8, 0x2e8ba, 0x22e8b, 0x1745d, 0x0ba2e, 0x00000, 282 0x345d1, 0x28ba2, 0x1d174, 0x11745, 0x05d17, 0x3a2e8, 0x11745 283 }; 284 285 286 #ifdef ATW_DEBUG 287 288 const char *atw_tx_state[] = { 289 "STOPPED", 290 "RUNNING - read descriptor", 291 "RUNNING - transmitting", 292 "RUNNING - filling fifo", /* XXX */ 293 "SUSPENDED", 294 "RUNNING -- write descriptor", 295 "RUNNING -- write last descriptor", 296 "RUNNING - fifo full" 297 }; 298 299 const char *atw_rx_state[] = { 300 "STOPPED", 301 "RUNNING - read descriptor", 302 "RUNNING - check this packet, pre-fetch next", 303 "RUNNING - wait for reception", 304 "SUSPENDED", 305 "RUNNING - write descriptor", 306 "RUNNING - flush fifo", 307 "RUNNING - fifo drain" 308 }; 309 310 #endif 311 312 /* 313 * atw_enable: 314 * 315 * Enable the ADM8211 chip. 316 */ 317 int 318 atw_enable(struct atw_softc *sc) 319 { 320 321 if (ATW_IS_ENABLED(sc) == 0) { 322 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) { 323 printf("%s: device enable failed\n", 324 sc->sc_dev.dv_xname); 325 return (EIO); 326 } 327 sc->sc_flags |= ATWF_ENABLED; 328 } 329 return (0); 330 } 331 332 /* 333 * atw_disable: 334 * 335 * Disable the ADM8211 chip. 336 */ 337 void 338 atw_disable(struct atw_softc *sc) 339 { 340 if (!ATW_IS_ENABLED(sc)) 341 return; 342 if (sc->sc_disable != NULL) 343 (*sc->sc_disable)(sc); 344 sc->sc_flags &= ~ATWF_ENABLED; 345 } 346 347 /* Returns -1 on failure. */ 348 int 349 atw_read_srom(struct atw_softc *sc) 350 { 351 struct seeprom_descriptor sd; 352 u_int32_t test0, fail_bits; 353 354 (void)memset(&sd, 0, sizeof(sd)); 355 356 test0 = ATW_READ(sc, ATW_TEST0); 357 358 switch (sc->sc_rev) { 359 case ATW_REVISION_BA: 360 case ATW_REVISION_CA: 361 fail_bits = ATW_TEST0_EPNE; 362 break; 363 default: 364 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM; 365 break; 366 } 367 if ((test0 & fail_bits) != 0) { 368 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname); 369 return -1; 370 } 371 372 switch (test0 & ATW_TEST0_EPTYP_MASK) { 373 case ATW_TEST0_EPTYP_93c66: 374 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname)); 375 sc->sc_sromsz = 512; 376 sd.sd_chip = C56_66; 377 break; 378 case ATW_TEST0_EPTYP_93c46: 379 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname)); 380 sc->sc_sromsz = 128; 381 sd.sd_chip = C46; 382 break; 383 default: 384 printf("%s: unknown SROM type %d\n", sc->sc_dev.dv_xname, 385 MASK_AND_RSHIFT(test0, ATW_TEST0_EPTYP_MASK)); 386 return -1; 387 } 388 389 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT | M_ZERO); 390 if (sc->sc_srom == NULL) { 391 printf("%s: unable to allocate SROM buffer\n", 392 sc->sc_dev.dv_xname); 393 return -1; 394 } 395 396 /* 397 * ADM8211 has a single 32-bit register for controlling the 398 * 93cx6 SROM. Bit SRS enables the serial port. There is no 399 * "ready" bit. The ADM8211 input/output sense is the reverse 400 * of read_seeprom's. 401 */ 402 sd.sd_tag = sc->sc_st; 403 sd.sd_bsh = sc->sc_sh; 404 sd.sd_regsize = 4; 405 sd.sd_control_offset = ATW_SPR; 406 sd.sd_status_offset = ATW_SPR; 407 sd.sd_dataout_offset = ATW_SPR; 408 sd.sd_CK = ATW_SPR_SCLK; 409 sd.sd_CS = ATW_SPR_SCS; 410 sd.sd_DI = ATW_SPR_SDO; 411 sd.sd_DO = ATW_SPR_SDI; 412 sd.sd_MS = ATW_SPR_SRS; 413 sd.sd_RDY = 0; 414 415 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) { 416 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname); 417 free(sc->sc_srom, M_DEVBUF, sc->sc_sromsz); 418 return -1; 419 } 420 #ifdef ATW_DEBUG 421 { 422 int i; 423 ATW_DPRINTF(("\nSerial EEPROM:\n\t")); 424 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) { 425 if (((i % 8) == 0) && (i != 0)) { 426 ATW_DPRINTF(("\n\t")); 427 } 428 ATW_DPRINTF((" 0x%x", sc->sc_srom[i])); 429 } 430 ATW_DPRINTF(("\n")); 431 } 432 #endif /* ATW_DEBUG */ 433 return 0; 434 } 435 436 #ifdef ATW_DEBUG 437 void 438 atw_print_regs(struct atw_softc *sc, const char *where) 439 { 440 #define PRINTREG(sc, reg) \ 441 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \ 442 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg))) 443 444 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where)); 445 446 PRINTREG(sc, ATW_PAR); 447 PRINTREG(sc, ATW_FRCTL); 448 PRINTREG(sc, ATW_TDR); 449 PRINTREG(sc, ATW_WTDP); 450 PRINTREG(sc, ATW_RDR); 451 PRINTREG(sc, ATW_WRDP); 452 PRINTREG(sc, ATW_RDB); 453 PRINTREG(sc, ATW_CSR3A); 454 PRINTREG(sc, ATW_TDBD); 455 PRINTREG(sc, ATW_TDBP); 456 PRINTREG(sc, ATW_STSR); 457 PRINTREG(sc, ATW_CSR5A); 458 PRINTREG(sc, ATW_NAR); 459 PRINTREG(sc, ATW_CSR6A); 460 PRINTREG(sc, ATW_IER); 461 PRINTREG(sc, ATW_CSR7A); 462 PRINTREG(sc, ATW_LPC); 463 PRINTREG(sc, ATW_TEST1); 464 PRINTREG(sc, ATW_SPR); 465 PRINTREG(sc, ATW_TEST0); 466 PRINTREG(sc, ATW_WCSR); 467 PRINTREG(sc, ATW_WPDR); 468 PRINTREG(sc, ATW_GPTMR); 469 PRINTREG(sc, ATW_GPIO); 470 PRINTREG(sc, ATW_BBPCTL); 471 PRINTREG(sc, ATW_SYNCTL); 472 PRINTREG(sc, ATW_PLCPHD); 473 PRINTREG(sc, ATW_MMIWADDR); 474 PRINTREG(sc, ATW_MMIRADDR1); 475 PRINTREG(sc, ATW_MMIRADDR2); 476 PRINTREG(sc, ATW_TXBR); 477 PRINTREG(sc, ATW_CSR15A); 478 PRINTREG(sc, ATW_ALCSTAT); 479 PRINTREG(sc, ATW_TOFS2); 480 PRINTREG(sc, ATW_CMDR); 481 PRINTREG(sc, ATW_PCIC); 482 PRINTREG(sc, ATW_PMCSR); 483 PRINTREG(sc, ATW_PAR0); 484 PRINTREG(sc, ATW_PAR1); 485 PRINTREG(sc, ATW_MAR0); 486 PRINTREG(sc, ATW_MAR1); 487 PRINTREG(sc, ATW_ATIMDA0); 488 PRINTREG(sc, ATW_ABDA1); 489 PRINTREG(sc, ATW_BSSID0); 490 PRINTREG(sc, ATW_TXLMT); 491 PRINTREG(sc, ATW_MIBCNT); 492 PRINTREG(sc, ATW_BCNT); 493 PRINTREG(sc, ATW_TSFTH); 494 PRINTREG(sc, ATW_TSC); 495 PRINTREG(sc, ATW_SYNRF); 496 PRINTREG(sc, ATW_BPLI); 497 PRINTREG(sc, ATW_CAP0); 498 PRINTREG(sc, ATW_CAP1); 499 PRINTREG(sc, ATW_RMD); 500 PRINTREG(sc, ATW_CFPP); 501 PRINTREG(sc, ATW_TOFS0); 502 PRINTREG(sc, ATW_TOFS1); 503 PRINTREG(sc, ATW_IFST); 504 PRINTREG(sc, ATW_RSPT); 505 PRINTREG(sc, ATW_TSFTL); 506 PRINTREG(sc, ATW_WEPCTL); 507 PRINTREG(sc, ATW_WESK); 508 PRINTREG(sc, ATW_WEPCNT); 509 PRINTREG(sc, ATW_MACTEST); 510 PRINTREG(sc, ATW_FER); 511 PRINTREG(sc, ATW_FEMR); 512 PRINTREG(sc, ATW_FPSR); 513 PRINTREG(sc, ATW_FFER); 514 #undef PRINTREG 515 } 516 #endif /* ATW_DEBUG */ 517 518 const char* 519 atw_printmac(u_int8_t rev) { 520 switch (rev) { 521 case ATW_REVISION_AB: 522 return "ADM8211AB"; 523 case ATW_REVISION_AF: 524 return "ADM8211AF"; 525 case ATW_REVISION_BA: 526 return "ADM8211BA"; 527 case ATW_REVISION_CA: 528 return "ADM8211CA"; 529 default: 530 return "unknown"; 531 } 532 } 533 534 /* 535 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end. 536 */ 537 void 538 atw_attach(struct atw_softc *sc) 539 { 540 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = { 541 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 542 }; 543 struct ieee80211com *ic = &sc->sc_ic; 544 struct ifnet *ifp = &ic->ic_if; 545 int country_code, error, i, srom_major; 546 u_int32_t reg; 547 static const char *type_strings[] = {"Intersil (not supported)", 548 "RFMD", "Marvel (not supported)"}; 549 550 sc->sc_txth = atw_txthresh_tab_lo; 551 552 SIMPLEQ_INIT(&sc->sc_txfreeq); 553 SIMPLEQ_INIT(&sc->sc_txdirtyq); 554 555 #ifdef ATW_DEBUG 556 atw_print_regs(sc, "atw_attach"); 557 #endif /* ATW_DEBUG */ 558 559 /* 560 * Allocate the control data structures, and create and load the 561 * DMA map for it. 562 */ 563 if ((error = bus_dmamem_alloc(sc->sc_dmat, 564 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 565 1, &sc->sc_cdnseg, 0)) != 0) { 566 printf("%s: unable to allocate control data, error = %d\n", 567 sc->sc_dev.dv_xname, error); 568 goto fail_0; 569 } 570 571 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg, 572 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data, 573 BUS_DMA_COHERENT)) != 0) { 574 printf("%s: unable to map control data, error = %d\n", 575 sc->sc_dev.dv_xname, error); 576 goto fail_1; 577 } 578 579 if ((error = bus_dmamap_create(sc->sc_dmat, 580 sizeof(struct atw_control_data), 1, 581 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 582 printf("%s: unable to create control data DMA map, " 583 "error = %d\n", sc->sc_dev.dv_xname, error); 584 goto fail_2; 585 } 586 587 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 588 sc->sc_control_data, sizeof(struct atw_control_data), NULL, 589 0)) != 0) { 590 printf("%s: unable to load control data DMA map, error = %d\n", 591 sc->sc_dev.dv_xname, error); 592 goto fail_3; 593 } 594 595 /* 596 * Create the transmit buffer DMA maps. 597 */ 598 sc->sc_ntxsegs = ATW_NTXSEGS; 599 for (i = 0; i < ATW_TXQUEUELEN; i++) { 600 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 601 sc->sc_ntxsegs, MCLBYTES, 0, 0, 602 &sc->sc_txsoft[i].txs_dmamap)) != 0) { 603 printf("%s: unable to create tx DMA map %d, " 604 "error = %d\n", sc->sc_dev.dv_xname, i, error); 605 goto fail_4; 606 } 607 } 608 609 /* 610 * Create the receive buffer DMA maps. 611 */ 612 for (i = 0; i < ATW_NRXDESC; i++) { 613 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 614 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 615 printf("%s: unable to create rx DMA map %d, " 616 "error = %d\n", sc->sc_dev.dv_xname, i, error); 617 goto fail_5; 618 } 619 } 620 for (i = 0; i < ATW_NRXDESC; i++) { 621 sc->sc_rxsoft[i].rxs_mbuf = NULL; 622 } 623 624 switch (sc->sc_rev) { 625 case ATW_REVISION_AB: 626 case ATW_REVISION_AF: 627 sc->sc_sramlen = ATW_SRAM_A_SIZE; 628 break; 629 case ATW_REVISION_BA: 630 case ATW_REVISION_CA: 631 sc->sc_sramlen = ATW_SRAM_B_SIZE; 632 break; 633 } 634 635 /* Reset the chip to a known state. */ 636 atw_reset(sc); 637 638 if (atw_read_srom(sc) == -1) 639 return; 640 641 sc->sc_rftype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 642 ATW_SR_RFTYPE_MASK); 643 644 sc->sc_bbptype = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CSR20], 645 ATW_SR_BBPTYPE_MASK); 646 647 if (sc->sc_rftype >= nitems(type_strings)) { 648 printf("%s: unknown RF\n", sc->sc_dev.dv_xname); 649 return; 650 } 651 if (sc->sc_bbptype >= nitems(type_strings)) { 652 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname); 653 return; 654 } 655 656 printf("%s: MAC %s, BBP %s, RF %s", sc->sc_dev.dv_xname, 657 atw_printmac(sc->sc_rev), type_strings[sc->sc_bbptype], 658 type_strings[sc->sc_rftype]); 659 660 /* XXX There exists a Linux driver which seems to use RFType = 0 for 661 * MARVEL. My bug, or theirs? 662 */ 663 664 reg = LSHIFT(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK); 665 666 switch (sc->sc_rftype) { 667 case ATW_RFTYPE_INTERSIL: 668 reg |= ATW_SYNCTL_CS1; 669 break; 670 case ATW_RFTYPE_RFMD: 671 reg |= ATW_SYNCTL_CS0; 672 break; 673 case ATW_RFTYPE_MARVEL: 674 break; 675 } 676 677 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD; 678 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR; 679 680 reg = LSHIFT(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK); 681 682 switch (sc->sc_bbptype) { 683 case ATW_BBPTYPE_INTERSIL: 684 reg |= ATW_BBPCTL_TWI; 685 break; 686 case ATW_BBPTYPE_RFMD: 687 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO | 688 ATW_BBPCTL_CCA_ACTLO; 689 break; 690 case ATW_BBPTYPE_MARVEL: 691 break; 692 case ATW_C_BBPTYPE_RFMD: 693 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n", 694 sc->sc_dev.dv_xname); 695 break; 696 } 697 698 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR; 699 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD; 700 701 /* 702 * From this point forward, the attachment cannot fail. A failure 703 * before this point releases all resources that may have been 704 * allocated. 705 */ 706 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */; 707 708 ATW_DPRINTF((" SROM MAC %04x%04x%04x", 709 htole16(sc->sc_srom[ATW_SR_MAC00]), 710 htole16(sc->sc_srom[ATW_SR_MAC01]), 711 htole16(sc->sc_srom[ATW_SR_MAC10]))); 712 713 srom_major = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_FORMAT_VERSION], 714 ATW_SR_MAJOR_MASK); 715 716 if (srom_major < 2) 717 sc->sc_rf3000_options1 = 0; 718 else if (sc->sc_rev == ATW_REVISION_BA) { 719 sc->sc_rf3000_options1 = 720 MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CR28_CR03], 721 ATW_SR_CR28_MASK); 722 } else 723 sc->sc_rf3000_options1 = 0; 724 725 sc->sc_rf3000_options2 = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 726 ATW_SR_CR29_MASK); 727 728 country_code = MASK_AND_RSHIFT(sc->sc_srom[ATW_SR_CTRY_CR29], 729 ATW_SR_CTRY_MASK); 730 731 #define ADD_CHANNEL(_ic, _chan) do { \ 732 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \ 733 _ic->ic_channels[_chan].ic_freq = \ 734 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\ 735 } while (0) 736 737 /* Find available channels */ 738 switch (country_code) { 739 case COUNTRY_MMK2: /* 1-14 */ 740 ADD_CHANNEL(ic, 14); 741 /*FALLTHROUGH*/ 742 case COUNTRY_ETSI: /* 1-13 */ 743 for (i = 1; i <= 13; i++) 744 ADD_CHANNEL(ic, i); 745 break; 746 case COUNTRY_FCC: /* 1-11 */ 747 case COUNTRY_IC: /* 1-11 */ 748 for (i = 1; i <= 11; i++) 749 ADD_CHANNEL(ic, i); 750 break; 751 case COUNTRY_MMK: /* 14 */ 752 ADD_CHANNEL(ic, 14); 753 break; 754 case COUNTRY_FRANCE: /* 10-13 */ 755 for (i = 10; i <= 13; i++) 756 ADD_CHANNEL(ic, i); 757 break; 758 default: /* assume channels 10-11 */ 759 case COUNTRY_SPAIN: /* 10-11 */ 760 for (i = 10; i <= 11; i++) 761 ADD_CHANNEL(ic, i); 762 break; 763 } 764 765 /* Read the MAC address. */ 766 reg = ATW_READ(sc, ATW_PAR0); 767 ic->ic_myaddr[0] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB0_MASK); 768 ic->ic_myaddr[1] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB1_MASK); 769 ic->ic_myaddr[2] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB2_MASK); 770 ic->ic_myaddr[3] = MASK_AND_RSHIFT(reg, ATW_PAR0_PAB3_MASK); 771 reg = ATW_READ(sc, ATW_PAR1); 772 ic->ic_myaddr[4] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB4_MASK); 773 ic->ic_myaddr[5] = MASK_AND_RSHIFT(reg, ATW_PAR1_PAB5_MASK); 774 775 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) { 776 printf(" could not get mac address, attach failed\n"); 777 return; 778 } 779 780 printf(", address %s\n", ether_sprintf(ic->ic_myaddr)); 781 782 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 783 ifp->if_softc = sc; 784 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 785 ifp->if_ioctl = atw_ioctl; 786 ifp->if_start = atw_start; 787 ifp->if_watchdog = atw_watchdog; 788 789 ic->ic_phytype = IEEE80211_T_DS; 790 ic->ic_opmode = IEEE80211_M_STA; 791 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_MONITOR | IEEE80211_C_WEP; 792 #ifndef IEEE80211_STA_ONLY 793 ic->ic_caps |= IEEE80211_C_IBSS; 794 #endif 795 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 796 797 /* 798 * Call MI attach routines. 799 */ 800 801 if_attach(ifp); 802 ieee80211_ifattach(ifp); 803 804 sc->sc_newstate = ic->ic_newstate; 805 ic->ic_newstate = atw_newstate; 806 807 #ifndef IEEE80211_STA_ONLY 808 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 809 ic->ic_recv_mgmt = atw_recv_mgmt; 810 #endif 811 812 sc->sc_node_free = ic->ic_node_free; 813 ic->ic_node_free = atw_node_free; 814 815 sc->sc_node_alloc = ic->ic_node_alloc; 816 ic->ic_node_alloc = atw_node_alloc; 817 818 /* possibly we should fill in our own sc_send_prresp, since 819 * the ADM8211 is probably sending probe responses in ad hoc 820 * mode. 821 */ 822 823 /* complete initialization */ 824 ieee80211_media_init(ifp, atw_media_change, atw_media_status); 825 timeout_set(&sc->sc_scan_to, atw_next_scan, sc); 826 827 #if NBPFILTER > 0 828 bpfattach(&sc->sc_radiobpf, ifp, DLT_IEEE802_11_RADIO, 829 sizeof(struct ieee80211_frame) + 64); 830 #endif 831 832 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu)); 833 sc->sc_rxtap.ar_ihdr.it_len = sizeof(sc->sc_rxtapu); 834 sc->sc_rxtap.ar_ihdr.it_present = ATW_RX_RADIOTAP_PRESENT; 835 836 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu)); 837 sc->sc_txtap.at_ihdr.it_len = sizeof(sc->sc_txtapu); 838 sc->sc_txtap.at_ihdr.it_present = ATW_TX_RADIOTAP_PRESENT; 839 840 return; 841 842 /* 843 * Free any resources we've allocated during the failed attach 844 * attempt. Do this in reverse order and fall through. 845 */ 846 fail_5: 847 for (i = 0; i < ATW_NRXDESC; i++) { 848 if (sc->sc_rxsoft[i].rxs_dmamap == NULL) 849 continue; 850 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap); 851 } 852 fail_4: 853 for (i = 0; i < ATW_TXQUEUELEN; i++) { 854 if (sc->sc_txsoft[i].txs_dmamap == NULL) 855 continue; 856 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap); 857 } 858 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 859 fail_3: 860 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 861 fail_2: 862 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 863 sizeof(struct atw_control_data)); 864 fail_1: 865 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 866 fail_0: 867 return; 868 } 869 870 struct ieee80211_node * 871 atw_node_alloc(struct ieee80211com *ic) 872 { 873 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 874 struct ieee80211_node *ni = (*sc->sc_node_alloc)(ic); 875 876 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni)); 877 return ni; 878 } 879 880 void 881 atw_node_free(struct ieee80211com *ic, struct ieee80211_node *ni) 882 { 883 struct atw_softc *sc = (struct atw_softc *)ic->ic_if.if_softc; 884 885 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni, 886 ether_sprintf(ni->ni_bssid))); 887 (*sc->sc_node_free)(ic, ni); 888 } 889 890 891 static void 892 atw_test1_reset(struct atw_softc *sc) 893 { 894 switch (sc->sc_rev) { 895 case ATW_REVISION_BA: 896 if (1 /* XXX condition on transceiver type */) { 897 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR); 898 } 899 break; 900 case ATW_REVISION_CA: 901 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK); 902 break; 903 default: 904 break; 905 } 906 } 907 908 /* 909 * atw_reset: 910 * 911 * Perform a soft reset on the ADM8211. 912 */ 913 void 914 atw_reset(struct atw_softc *sc) 915 { 916 int i; 917 uint32_t lpc; 918 919 ATW_WRITE(sc, ATW_NAR, 0x0); 920 DELAY(20 * 1000); 921 922 /* Reference driver has a cryptic remark indicating that this might 923 * power-on the chip. I know that it turns off power-saving.... 924 */ 925 ATW_WRITE(sc, ATW_FRCTL, 0x0); 926 927 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR); 928 929 for (i = 0; i < 50; i++) { 930 if (ATW_READ(sc, ATW_PAR) == 0) 931 break; 932 DELAY(1000); 933 } 934 935 /* ... and then pause 100ms longer for good measure. */ 936 DELAY(100 * 1000); 937 938 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i)); 939 940 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR)) 941 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname); 942 943 atw_test1_reset(sc); 944 /* 945 * Initialize the PCI Access Register. 946 */ 947 sc->sc_busmode = ATW_PAR_PBL_8DW; 948 949 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 950 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 951 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 952 953 /* Turn off maximum power saving, etc. 954 * 955 * XXX Following example of reference driver, should I set 956 * an AID of 1? It didn't seem to help.... 957 */ 958 ATW_WRITE(sc, ATW_FRCTL, 0x0); 959 960 DELAY(100 * 1000); 961 962 /* Recall EEPROM. */ 963 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD); 964 965 DELAY(10 * 1000); 966 967 lpc = ATW_READ(sc, ATW_LPC); 968 969 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc)); 970 971 /* A reset seems to affect the SRAM contents, so put them into 972 * a known state. 973 */ 974 atw_clear_sram(sc); 975 976 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid)); 977 } 978 979 void 980 atw_clear_sram(struct atw_softc *sc) 981 { 982 memset(sc->sc_sram, 0, sizeof(sc->sc_sram)); 983 /* XXX not for revision 0x20. */ 984 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen); 985 } 986 987 /* TBD atw_init 988 * 989 * set MAC based on ic->ic_bss->myaddr 990 * write WEP keys 991 * set TX rate 992 */ 993 994 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass 995 * without receiving a beacon with the preferred BSSID & SSID. 996 * atw_write_bssid & atw_write_ssid set the BSSID & SSID. 997 */ 998 void 999 atw_wcsr_init(struct atw_softc *sc) 1000 { 1001 uint32_t wcsr; 1002 1003 wcsr = ATW_READ(sc, ATW_WCSR); 1004 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE); 1005 wcsr |= LSHIFT(7, ATW_WCSR_BLN_MASK); 1006 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */ 1007 1008 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n", 1009 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR))); 1010 } 1011 1012 /* Turn off power management. Set Rx store-and-forward mode. */ 1013 void 1014 atw_cmdr_init(struct atw_softc *sc) 1015 { 1016 uint32_t cmdr; 1017 cmdr = ATW_READ(sc, ATW_CMDR); 1018 cmdr &= ~ATW_CMDR_APM; 1019 cmdr |= ATW_CMDR_RTE; 1020 cmdr &= ~ATW_CMDR_DRT_MASK; 1021 cmdr |= ATW_CMDR_DRT_SF; 1022 1023 ATW_WRITE(sc, ATW_CMDR, cmdr); 1024 } 1025 1026 void 1027 atw_tofs2_init(struct atw_softc *sc) 1028 { 1029 uint32_t tofs2; 1030 /* XXX this magic can probably be figured out from the RFMD docs */ 1031 #ifndef ATW_REFSLAVE 1032 tofs2 = LSHIFT(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1033 LSHIFT(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1034 LSHIFT(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1035 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1036 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1037 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1038 LSHIFT(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1039 LSHIFT(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1040 #else 1041 /* XXX new magic from reference driver source */ 1042 tofs2 = LSHIFT(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */ 1043 LSHIFT(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */ 1044 LSHIFT(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */ 1045 LSHIFT(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */ 1046 LSHIFT(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */ 1047 LSHIFT(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */ 1048 LSHIFT(1, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */ 1049 LSHIFT(8, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */ 1050 #endif 1051 ATW_WRITE(sc, ATW_TOFS2, tofs2); 1052 } 1053 1054 void 1055 atw_nar_init(struct atw_softc *sc) 1056 { 1057 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB); 1058 } 1059 1060 void 1061 atw_txlmt_init(struct atw_softc *sc) 1062 { 1063 ATW_WRITE(sc, ATW_TXLMT, LSHIFT(512, ATW_TXLMT_MTMLT_MASK) | 1064 LSHIFT(1, ATW_TXLMT_SRTYLIM_MASK)); 1065 } 1066 1067 void 1068 atw_test1_init(struct atw_softc *sc) 1069 { 1070 uint32_t test1; 1071 1072 test1 = ATW_READ(sc, ATW_TEST1); 1073 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL); 1074 /* XXX magic 0x1 */ 1075 test1 |= LSHIFT(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL; 1076 ATW_WRITE(sc, ATW_TEST1, test1); 1077 } 1078 1079 void 1080 atw_rf_reset(struct atw_softc *sc) 1081 { 1082 /* XXX this resets an Intersil RF front-end? */ 1083 /* TBD condition on Intersil RFType? */ 1084 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN); 1085 DELAY(10 * 1000); 1086 ATW_WRITE(sc, ATW_SYNRF, 0); 1087 DELAY(5 * 1000); 1088 } 1089 1090 /* Set 16 TU max duration for the contention-free period (CFP). */ 1091 void 1092 atw_cfp_init(struct atw_softc *sc) 1093 { 1094 uint32_t cfpp; 1095 1096 cfpp = ATW_READ(sc, ATW_CFPP); 1097 cfpp &= ~ATW_CFPP_CFPMD; 1098 cfpp |= LSHIFT(16, ATW_CFPP_CFPMD); 1099 ATW_WRITE(sc, ATW_CFPP, cfpp); 1100 } 1101 1102 void 1103 atw_tofs0_init(struct atw_softc *sc) 1104 { 1105 /* XXX I guess that the Cardbus clock is 22MHz? 1106 * I am assuming that the role of ATW_TOFS0_USCNT is 1107 * to divide the bus clock to get a 1MHz clock---the datasheet is not 1108 * very clear on this point. It says in the datasheet that it is 1109 * possible for the ADM8211 to accommodate bus speeds between 22MHz 1110 * and 33MHz; maybe this is the way? I see a binary-only driver write 1111 * these values. These values are also the power-on default. 1112 */ 1113 ATW_WRITE(sc, ATW_TOFS0, 1114 LSHIFT(22, ATW_TOFS0_USCNT_MASK) | 1115 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */); 1116 } 1117 1118 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */ 1119 void 1120 atw_ifs_init(struct atw_softc *sc) 1121 { 1122 uint32_t ifst; 1123 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver. 1124 * Go figure. 1125 */ 1126 ifst = LSHIFT(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) | 1127 LSHIFT(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22MHz cycles */, 1128 ATW_IFST_SIFS_MASK) | 1129 LSHIFT(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) | 1130 LSHIFT(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK); 1131 1132 ATW_WRITE(sc, ATW_IFST, ifst); 1133 } 1134 1135 void 1136 atw_response_times_init(struct atw_softc *sc) 1137 { 1138 /* XXX More magic. Relates to ACK timing? The datasheet seems to 1139 * indicate that the MAC expects at least SIFS + MIRT microseconds 1140 * to pass after it transmits a frame that requires a response; 1141 * it waits at most SIFS + MART microseconds for the response. 1142 * Surely this is not the ACK timeout? 1143 */ 1144 ATW_WRITE(sc, ATW_RSPT, LSHIFT(0xffff, ATW_RSPT_MART_MASK) | 1145 LSHIFT(0xff, ATW_RSPT_MIRT_MASK)); 1146 } 1147 1148 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx 1149 * engines read and write baseband registers after Rx and before 1150 * Tx, respectively. 1151 */ 1152 void 1153 atw_bbp_io_init(struct atw_softc *sc) 1154 { 1155 uint32_t mmiraddr2; 1156 1157 /* XXX The reference driver does this, but is it *really* 1158 * necessary? 1159 */ 1160 switch (sc->sc_rev) { 1161 case ATW_REVISION_AB: 1162 case ATW_REVISION_AF: 1163 mmiraddr2 = 0x0; 1164 break; 1165 default: 1166 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2); 1167 mmiraddr2 &= 1168 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK); 1169 break; 1170 } 1171 1172 switch (sc->sc_bbptype) { 1173 case ATW_BBPTYPE_INTERSIL: 1174 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL); 1175 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL); 1176 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL; 1177 break; 1178 case ATW_BBPTYPE_MARVEL: 1179 /* TBD find out the Marvel settings. */ 1180 break; 1181 case ATW_BBPTYPE_RFMD: 1182 default: 1183 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD); 1184 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD); 1185 mmiraddr2 |= ATW_MMIRADDR2_RFMD; 1186 break; 1187 } 1188 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2); 1189 1190 atw_si4126_init(sc); 1191 1192 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK); 1193 } 1194 1195 void 1196 atw_si4126_init(struct atw_softc *sc) 1197 { 1198 switch (sc->sc_rftype) { 1199 case ATW_RFTYPE_RFMD: 1200 if (sc->sc_rev >= ATW_REVISION_BA) { 1201 atw_si4126_write(sc, 0x1f, 0x00000); 1202 atw_si4126_write(sc, 0x0c, 0x3001f); 1203 atw_si4126_write(sc, SI4126_GAIN, 0x29c03); 1204 atw_si4126_write(sc, SI4126_RF1N, 0x1ff6f); 1205 atw_si4126_write(sc, SI4126_RF2N, 0x29403); 1206 atw_si4126_write(sc, SI4126_RF2R, 0x1456f); 1207 atw_si4126_write(sc, 0x09, 0x10050); 1208 atw_si4126_write(sc, SI4126_IFR, 0x3fff8); 1209 } 1210 break; 1211 default: 1212 break; 1213 } 1214 } 1215 1216 /* 1217 * atw_init: [ ifnet interface function ] 1218 * 1219 * Initialize the interface. Must be called at splnet(). 1220 */ 1221 int 1222 atw_init(struct ifnet *ifp) 1223 { 1224 struct atw_softc *sc = ifp->if_softc; 1225 struct ieee80211com *ic = &sc->sc_ic; 1226 struct atw_txsoft *txs; 1227 struct atw_rxsoft *rxs; 1228 int i, error = 0; 1229 1230 if ((error = atw_enable(sc)) != 0) 1231 goto out; 1232 1233 /* 1234 * Cancel any pending I/O. This also resets. 1235 */ 1236 atw_stop(ifp, 0); 1237 1238 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 1239 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n", 1240 __func__, ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan), 1241 ic->ic_bss->ni_chan->ic_freq, ic->ic_bss->ni_chan->ic_flags)); 1242 1243 atw_wcsr_init(sc); 1244 1245 atw_cmdr_init(sc); 1246 1247 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s. 1248 * 1249 * XXX Set transmit power for ATIM, RTS, Beacon. 1250 */ 1251 ATW_WRITE(sc, ATW_PLCPHD, LSHIFT(10, ATW_PLCPHD_SIGNAL_MASK) | 1252 LSHIFT(0xb0, ATW_PLCPHD_SERVICE_MASK)); 1253 1254 atw_tofs2_init(sc); 1255 1256 atw_nar_init(sc); 1257 1258 atw_txlmt_init(sc); 1259 1260 atw_test1_init(sc); 1261 1262 atw_rf_reset(sc); 1263 1264 atw_cfp_init(sc); 1265 1266 atw_tofs0_init(sc); 1267 1268 atw_ifs_init(sc); 1269 1270 /* XXX Fall asleep after one second of inactivity. 1271 * XXX A frame may only dribble in for 65536us. 1272 */ 1273 ATW_WRITE(sc, ATW_RMD, 1274 LSHIFT(1, ATW_RMD_PCNT) | LSHIFT(0xffff, ATW_RMD_RMRD_MASK)); 1275 1276 atw_response_times_init(sc); 1277 1278 atw_bbp_io_init(sc); 1279 1280 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1281 1282 if ((error = atw_rf3000_init(sc)) != 0) 1283 goto out; 1284 1285 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode); 1286 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname, 1287 ATW_READ(sc, ATW_PAR), sc->sc_busmode)); 1288 1289 /* 1290 * Initialize the transmit descriptor ring. 1291 */ 1292 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 1293 for (i = 0; i < ATW_NTXDESC; i++) { 1294 sc->sc_txdescs[i].at_ctl = 0; 1295 /* no transmit chaining */ 1296 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; 1297 sc->sc_txdescs[i].at_buf2 = 1298 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i))); 1299 } 1300 /* use ring mode */ 1301 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); 1302 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC, 1303 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1304 sc->sc_txfree = ATW_NTXDESC; 1305 sc->sc_txnext = 0; 1306 1307 /* 1308 * Initialize the transmit job descriptors. 1309 */ 1310 SIMPLEQ_INIT(&sc->sc_txfreeq); 1311 SIMPLEQ_INIT(&sc->sc_txdirtyq); 1312 for (i = 0; i < ATW_TXQUEUELEN; i++) { 1313 txs = &sc->sc_txsoft[i]; 1314 txs->txs_mbuf = NULL; 1315 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1316 } 1317 1318 /* 1319 * Initialize the receive descriptor and receive job 1320 * descriptor rings. 1321 */ 1322 for (i = 0; i < ATW_NRXDESC; i++) { 1323 rxs = &sc->sc_rxsoft[i]; 1324 if (rxs->rxs_mbuf == NULL) { 1325 if ((error = atw_add_rxbuf(sc, i)) != 0) { 1326 printf("%s: unable to allocate or map rx " 1327 "buffer %d, error = %d\n", 1328 sc->sc_dev.dv_xname, i, error); 1329 /* 1330 * XXX Should attempt to run with fewer receive 1331 * XXX buffers instead of just failing. 1332 */ 1333 atw_rxdrain(sc); 1334 goto out; 1335 } 1336 } else 1337 ATW_INIT_RXDESC(sc, i); 1338 } 1339 sc->sc_rxptr = 0; 1340 1341 /* 1342 * Initialize the interrupt mask and enable interrupts. 1343 */ 1344 /* normal interrupts */ 1345 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI | 1346 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC; 1347 1348 /* abnormal interrupts */ 1349 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT | 1350 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS | 1351 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1352 1353 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF | 1354 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ; 1355 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU; 1356 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT | 1357 ATW_INTR_TRT; 1358 1359 sc->sc_linkint_mask &= sc->sc_inten; 1360 sc->sc_rxint_mask &= sc->sc_inten; 1361 sc->sc_txint_mask &= sc->sc_inten; 1362 1363 ATW_WRITE(sc, ATW_IER, sc->sc_inten); 1364 ATW_WRITE(sc, ATW_STSR, 0xffffffff); 1365 1366 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n", 1367 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten)); 1368 1369 /* 1370 * Give the transmit and receive rings to the ADM8211. 1371 */ 1372 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr)); 1373 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext)); 1374 1375 sc->sc_txthresh = 0; 1376 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST | 1377 sc->sc_txth[sc->sc_txthresh].txth_opmode; 1378 1379 /* common 802.11 configuration */ 1380 ic->ic_flags &= ~IEEE80211_F_IBSSON; 1381 switch (ic->ic_opmode) { 1382 case IEEE80211_M_STA: 1383 break; 1384 #ifndef IEEE80211_STA_ONLY 1385 case IEEE80211_M_AHDEMO: /* XXX */ 1386 case IEEE80211_M_IBSS: 1387 ic->ic_flags |= IEEE80211_F_IBSSON; 1388 /*FALLTHROUGH*/ 1389 #endif 1390 default: /* XXX */ 1391 break; 1392 } 1393 1394 #ifndef IEEE80211_STA_ONLY 1395 switch (ic->ic_opmode) { 1396 case IEEE80211_M_AHDEMO: 1397 ic->ic_bss->ni_intval = ic->ic_lintval; 1398 ic->ic_bss->ni_rssi = 0; 1399 ic->ic_bss->ni_rstamp = 0; 1400 break; 1401 default: /* XXX */ 1402 break; 1403 } 1404 #endif 1405 sc->sc_wepctl = 0; 1406 1407 atw_write_ssid(sc); 1408 atw_write_sup_rates(sc); 1409 if (ic->ic_caps & IEEE80211_C_WEP) 1410 atw_write_wep(sc); 1411 1412 ic->ic_state = IEEE80211_S_INIT; 1413 1414 /* 1415 * Set the receive filter. This will start the transmit and 1416 * receive processes. 1417 */ 1418 atw_filter_setup(sc); 1419 1420 /* 1421 * Start the receive process. 1422 */ 1423 ATW_WRITE(sc, ATW_RDR, 0x1); 1424 1425 /* 1426 * Note that the interface is now running. 1427 */ 1428 ifp->if_flags |= IFF_RUNNING; 1429 ifq_clr_oactive(&ifp->if_snd); 1430 1431 /* send no beacons, yet. */ 1432 atw_start_beacon(sc, 0); 1433 1434 if (ic->ic_opmode == IEEE80211_M_MONITOR) 1435 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 1436 else 1437 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 1438 out: 1439 if (error) { 1440 ifp->if_flags &= ~IFF_RUNNING; 1441 ifq_clr_oactive(&ifp->if_snd); 1442 ifp->if_timer = 0; 1443 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1444 } 1445 #ifdef ATW_DEBUG 1446 atw_print_regs(sc, "end of init"); 1447 #endif /* ATW_DEBUG */ 1448 1449 return (error); 1450 } 1451 1452 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL. 1453 * 0: MAC control of RF3000/Si4126. 1454 * 1455 * Applies power, or selects RF front-end? Sets reset condition. 1456 * 1457 * TBD support non-RFMD BBP, non-SiLabs synth. 1458 */ 1459 void 1460 atw_bbp_io_enable(struct atw_softc *sc, int enable) 1461 { 1462 if (enable) { 1463 ATW_WRITE(sc, ATW_SYNRF, 1464 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST); 1465 DELAY(atw_bbp_io_enable_delay); 1466 } else { 1467 ATW_WRITE(sc, ATW_SYNRF, 0); 1468 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */ 1469 } 1470 } 1471 1472 int 1473 atw_tune(struct atw_softc *sc) 1474 { 1475 int rc; 1476 u_int chan; 1477 struct ieee80211com *ic = &sc->sc_ic; 1478 1479 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 1480 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1481 return 0; 1482 1483 if (chan == sc->sc_cur_chan) 1484 return 0; 1485 1486 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname, 1487 sc->sc_cur_chan, chan)); 1488 1489 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST); 1490 1491 atw_si4126_tune(sc, chan); 1492 if ((rc = atw_rf3000_tune(sc, chan)) != 0) 1493 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname, 1494 chan); 1495 1496 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 1497 DELAY(20 * 1000); 1498 ATW_WRITE(sc, ATW_RDR, 0x1); 1499 1500 if (rc == 0) 1501 sc->sc_cur_chan = chan; 1502 1503 return rc; 1504 } 1505 1506 #ifdef ATW_SYNDEBUG 1507 void 1508 atw_si4126_print(struct atw_softc *sc) 1509 { 1510 struct ifnet *ifp = &sc->sc_ic.ic_if; 1511 u_int addr, val; 1512 1513 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1514 return; 1515 1516 for (addr = 0; addr <= 8; addr++) { 1517 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr); 1518 if (atw_si4126_read(sc, addr, &val) == 0) { 1519 printf("<unknown> (quitting print-out)\n"); 1520 break; 1521 } 1522 printf("%05x\n", val); 1523 } 1524 } 1525 #endif /* ATW_SYNDEBUG */ 1526 1527 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer. 1528 * 1529 * The RF/IF synthesizer produces two reference frequencies for 1530 * the RF2948B transceiver. The first frequency the RF2948B requires 1531 * is two times the so-called "intermediate frequency" (IF). Since 1532 * a SAW filter on the radio fixes the IF at 374MHz, I program the 1533 * Si4126 to generate IF LO = 374MHz x 2 = 748MHz. The second 1534 * frequency required by the transceiver is the radio frequency 1535 * (RF). This is a superheterodyne transceiver; for f(chan) the 1536 * center frequency of the channel we are tuning, RF = f(chan) - 1537 * IF. 1538 * 1539 * XXX I am told by SiLabs that the Si4126 will accept a broader range 1540 * of XIN than the 2-25MHz mentioned by the datasheet, even *without* 1541 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it 1542 * works, but I have still programmed for XINDIV2 = 1 to be safe. 1543 */ 1544 void 1545 atw_si4126_tune(struct atw_softc *sc, u_int chan) 1546 { 1547 u_int mhz; 1548 u_int R; 1549 u_int32_t gpio; 1550 u_int16_t gain; 1551 1552 #ifdef ATW_SYNDEBUG 1553 atw_si4126_print(sc); 1554 #endif /* ATW_SYNDEBUG */ 1555 1556 if (sc->sc_rev >= ATW_REVISION_BA) { 1557 atw_si4126_write(sc, SI4126_MAIN, 0x04007); 1558 atw_si4126_write(sc, SI4126_POWER, 0x00033); 1559 atw_si4126_write(sc, SI4126_IFN, 1560 atw_rfmd2958_ifn[chan - 1]); 1561 atw_si4126_write(sc, SI4126_RF1R, 1562 atw_rfmd2958_rf1r[chan - 1]); 1563 #ifdef NOTYET 1564 /* set TX POWER? */ 1565 atw_si4126_write(sc, 0x0a, 1566 (sc->sc_srom[ATW_SR_CSR20] & mask) | 1567 power << 9); 1568 #endif 1569 /* set TX GAIN */ 1570 atw_si4126_write(sc, 0x09, 0x00050 | 1571 sc->sc_srom[ATW_SR_TXPOWER(chan - 1)]); 1572 /* wait 100us from power-up for RF, IF to settle */ 1573 DELAY(100); 1574 1575 return; 1576 } 1577 1578 if (chan == 14) 1579 mhz = 2484; 1580 else 1581 mhz = 2412 + 5 * (chan - 1); 1582 1583 /* Tune IF to 748MHz to suit the IF LO input of the 1584 * RF2494B, which is 2 x IF. No need to set an IF divider 1585 * because an IF in 526MHz - 952MHz is allowed. 1586 * 1587 * XIN is 44.000MHz, so divide it by two to get allowable 1588 * range of 2-25MHz. SiLabs tells me that this is not 1589 * strictly necessary. 1590 */ 1591 1592 if (atw_xindiv2) 1593 R = 44; 1594 else 1595 R = 88; 1596 1597 /* Power-up RF, IF synthesizers. */ 1598 atw_si4126_write(sc, SI4126_POWER, 1599 SI4126_POWER_PDIB|SI4126_POWER_PDRB); 1600 1601 /* set LPWR, too? */ 1602 atw_si4126_write(sc, SI4126_MAIN, 1603 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0); 1604 1605 /* Set the phase-locked loop gain. If RF2 N > 2047, then 1606 * set KP2 to 1. 1607 * 1608 * REFDIF This is different from the reference driver, which 1609 * always sets SI4126_GAIN to 0. 1610 */ 1611 gain = LSHIFT(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK); 1612 1613 atw_si4126_write(sc, SI4126_GAIN, gain); 1614 1615 /* XIN = 44MHz. 1616 * 1617 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496, 1618 * R = 44 so that 1496/(2 * 44) * 44MHz = 748MHz. 1619 * 1620 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88 1621 * so that 1496/88 * 44MHz = 748MHz. 1622 */ 1623 atw_si4126_write(sc, SI4126_IFN, 1496); 1624 1625 atw_si4126_write(sc, SI4126_IFR, R); 1626 1627 #ifndef ATW_REFSLAVE 1628 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because 1629 * then RF1 becomes the active RF synthesizer, even on the Si4126, 1630 * which has no RF1! 1631 */ 1632 atw_si4126_write(sc, SI4126_RF1R, R); 1633 1634 atw_si4126_write(sc, SI4126_RF1N, mhz - 374); 1635 #endif 1636 1637 /* N/R * XIN = RF. XIN = 44MHz. We desire RF = mhz - IF, 1638 * where IF = 374MHz. Let's divide XIN to 1MHz. So R = 44. 1639 * Now let's multiply it to mhz. So mhz - IF = N. 1640 */ 1641 atw_si4126_write(sc, SI4126_RF2R, R); 1642 1643 atw_si4126_write(sc, SI4126_RF2N, mhz - 374); 1644 1645 /* wait 100us from power-up for RF, IF to settle */ 1646 DELAY(100); 1647 1648 gpio = ATW_READ(sc, ATW_GPIO); 1649 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK); 1650 gpio |= LSHIFT(1, ATW_GPIO_EN_MASK); 1651 1652 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) { 1653 /* Set a Prism RF front-end to a special mode for channel 14? 1654 * 1655 * Apparently the SMC2635W needs this, although I don't think 1656 * it has a Prism RF. 1657 */ 1658 gpio |= LSHIFT(1, ATW_GPIO_O_MASK); 1659 } 1660 ATW_WRITE(sc, ATW_GPIO, gpio); 1661 1662 #ifdef ATW_SYNDEBUG 1663 atw_si4126_print(sc); 1664 #endif /* ATW_SYNDEBUG */ 1665 } 1666 1667 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna 1668 * diversity. 1669 * 1670 * !!! 1671 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR). 1672 * !!! 1673 */ 1674 int 1675 atw_rf3000_init(struct atw_softc *sc) 1676 { 1677 int rc = 0; 1678 1679 atw_bbp_io_enable(sc, 1); 1680 1681 /* CCA is acquisition sensitive */ 1682 rc = atw_rf3000_write(sc, RF3000_CCACTL, 1683 LSHIFT(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK)); 1684 1685 if (rc != 0) 1686 goto out; 1687 1688 /* enable diversity */ 1689 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE); 1690 1691 if (rc != 0) 1692 goto out; 1693 1694 /* sensible setting from a binary-only driver */ 1695 rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1696 LSHIFT(0x1d, RF3000_GAINCTL_TXVGC_MASK)); 1697 1698 if (rc != 0) 1699 goto out; 1700 1701 /* magic from a binary-only driver */ 1702 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, 1703 LSHIFT(0x38, RF3000_LOGAINCAL_CAL_MASK)); 1704 1705 if (rc != 0) 1706 goto out; 1707 1708 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD); 1709 1710 if (rc != 0) 1711 goto out; 1712 1713 /* 1714 * XXX Reference driver remarks that Abocom sets this to 50. 1715 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit 1716 * in the "reserved" area of register RF3000_OPTIONS1. 1717 */ 1718 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1); 1719 1720 if (rc != 0) 1721 goto out; 1722 1723 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2); 1724 1725 if (rc != 0) 1726 goto out; 1727 1728 out: 1729 atw_bbp_io_enable(sc, 0); 1730 return rc; 1731 } 1732 1733 #ifdef ATW_BBPDEBUG 1734 void 1735 atw_rf3000_print(struct atw_softc *sc) 1736 { 1737 struct ifnet *ifp = &sc->sc_ic.ic_if; 1738 u_int addr, val; 1739 1740 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0) 1741 return; 1742 1743 for (addr = 0x01; addr <= 0x15; addr++) { 1744 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr); 1745 if (atw_rf3000_read(sc, addr, &val) != 0) { 1746 printf("<unknown> (quitting print-out)\n"); 1747 break; 1748 } 1749 printf("%08x\n", val); 1750 } 1751 } 1752 #endif /* ATW_BBPDEBUG */ 1753 1754 /* Set the power settings on the BBP for channel `chan'. */ 1755 int 1756 atw_rf3000_tune(struct atw_softc *sc, u_int chan) 1757 { 1758 int rc = 0; 1759 u_int32_t reg; 1760 u_int16_t txpower, lpf_cutoff, lna_gs_thresh; 1761 1762 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)]; 1763 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)]; 1764 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)]; 1765 1766 /* odd channels: LSB, even channels: MSB */ 1767 if (chan % 2 == 1) { 1768 txpower &= 0xFF; 1769 lpf_cutoff &= 0xFF; 1770 lna_gs_thresh &= 0xFF; 1771 } else { 1772 txpower >>= 8; 1773 lpf_cutoff >>= 8; 1774 lna_gs_thresh >>= 8; 1775 } 1776 1777 #ifdef ATW_BBPDEBUG 1778 atw_rf3000_print(sc); 1779 #endif /* ATW_BBPDEBUG */ 1780 1781 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, " 1782 "lna_gs_thresh %02x\n", 1783 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh)); 1784 1785 atw_bbp_io_enable(sc, 1); 1786 1787 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL, 1788 LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0) 1789 goto out; 1790 1791 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0) 1792 goto out; 1793 1794 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0) 1795 goto out; 1796 1797 if ((rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0)) != 0) 1798 goto out; 1799 1800 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY); 1801 if (rc != 0) 1802 goto out; 1803 1804 #ifdef ATW_BBPDEBUG 1805 atw_rf3000_print(sc); 1806 #endif /* ATW_BBPDEBUG */ 1807 1808 out: 1809 atw_bbp_io_enable(sc, 0); 1810 1811 /* set beacon, rts, atim transmit power */ 1812 reg = ATW_READ(sc, ATW_PLCPHD); 1813 reg &= ~ATW_PLCPHD_SERVICE_MASK; 1814 reg |= LSHIFT(LSHIFT(txpower, RF3000_GAINCTL_TXVGC_MASK), 1815 ATW_PLCPHD_SERVICE_MASK); 1816 ATW_WRITE(sc, ATW_PLCPHD, reg); 1817 DELAY(2 * 1000); 1818 1819 return rc; 1820 } 1821 1822 /* Write a register on the RF3000 baseband processor using the 1823 * registers provided by the ADM8211 for this purpose. 1824 * 1825 * Return 0 on success. 1826 */ 1827 int 1828 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val) 1829 { 1830 u_int32_t reg; 1831 int i; 1832 1833 reg = sc->sc_bbpctl_wr | 1834 LSHIFT(val & 0xff, ATW_BBPCTL_DATA_MASK) | 1835 LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1836 1837 for (i = 10; --i >= 0; ) { 1838 ATW_WRITE(sc, ATW_BBPCTL, reg); 1839 DELAY(2000); 1840 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0) 1841 break; 1842 } 1843 1844 if (i < 0) { 1845 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname); 1846 return ETIMEDOUT; 1847 } 1848 return 0; 1849 } 1850 1851 /* Read a register on the RF3000 baseband processor using the registers 1852 * the ADM8211 provides for this purpose. 1853 * 1854 * The 7-bit register address is addr. Record the 8-bit data in the register 1855 * in *val. 1856 * 1857 * Return 0 on success. 1858 * 1859 * XXX This does not seem to work. The ADM8211 must require more or 1860 * different magic to read the chip than to write it. Possibly some 1861 * of the magic I have derived from a binary-only driver concerns 1862 * the "chip address" (see the RF3000 manual). 1863 */ 1864 #ifdef ATW_BBPDEBUG 1865 int 1866 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val) 1867 { 1868 u_int32_t reg; 1869 int i; 1870 1871 for (i = 1000; --i >= 0; ) { 1872 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0) 1873 break; 1874 DELAY(100); 1875 } 1876 1877 if (i < 0) { 1878 printf("%s: start atw_rf3000_read, BBPCTL busy\n", 1879 sc->sc_dev.dv_xname); 1880 return ETIMEDOUT; 1881 } 1882 1883 reg = sc->sc_bbpctl_rd | LSHIFT(addr & 0x7f, ATW_BBPCTL_ADDR_MASK); 1884 1885 ATW_WRITE(sc, ATW_BBPCTL, reg); 1886 1887 for (i = 1000; --i >= 0; ) { 1888 DELAY(100); 1889 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0) 1890 break; 1891 } 1892 1893 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD); 1894 1895 if (i < 0) { 1896 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n", 1897 sc->sc_dev.dv_xname, reg); 1898 return ETIMEDOUT; 1899 } 1900 if (val != NULL) 1901 *val = MASK_AND_RSHIFT(reg, ATW_BBPCTL_DATA_MASK); 1902 return 0; 1903 } 1904 #endif /* ATW_BBPDEBUG */ 1905 1906 /* Write a register on the Si4126 RF/IF synthesizer using the registers 1907 * provided by the ADM8211 for that purpose. 1908 * 1909 * val is 18 bits of data, and val is the 4-bit address of the register. 1910 * 1911 * Return 0 on success. 1912 */ 1913 void 1914 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val) 1915 { 1916 uint32_t bits, mask, reg; 1917 int nbits; 1918 1919 if (sc->sc_rev >= ATW_REVISION_BA) { 1920 nbits = 24; 1921 1922 val &= 0x3ffff; 1923 addr &= 0x1f; 1924 bits = val | (addr << 18); 1925 } else { 1926 nbits = 22; 1927 1928 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1929 KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0); 1930 1931 bits = LSHIFT(val, SI4126_TWI_DATA_MASK) | 1932 LSHIFT(addr, SI4126_TWI_ADDR_MASK); 1933 } 1934 1935 reg = ATW_SYNRF_SELSYN; 1936 /* reference driver: reset Si4126 serial bus to initial 1937 * conditions? 1938 */ 1939 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1940 ATW_WRITE(sc, ATW_SYNRF, reg); 1941 1942 for (mask = (1 << (nbits - 1)); mask != 0; mask >>= 1) { 1943 if ((bits & mask) != 0) 1944 reg |= ATW_SYNRF_SYNDATA; 1945 else 1946 reg &= ~ATW_SYNRF_SYNDATA; 1947 ATW_WRITE(sc, ATW_SYNRF, reg); 1948 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK); 1949 ATW_WRITE(sc, ATW_SYNRF, reg); 1950 } 1951 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF); 1952 ATW_WRITE(sc, ATW_SYNRF, 0x0); 1953 } 1954 1955 /* Read 18-bit data from the 4-bit address addr in Si4126 1956 * RF synthesizer and write the data to *val. Return 0 on success. 1957 * 1958 * XXX This does not seem to work. The ADM8211 must require more or 1959 * different magic to read the chip than to write it. 1960 */ 1961 #ifdef ATW_SYNDEBUG 1962 int 1963 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val) 1964 { 1965 u_int32_t reg; 1966 int i; 1967 1968 KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0); 1969 1970 for (i = 1000; --i >= 0; ) { 1971 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0) 1972 break; 1973 DELAY(100); 1974 } 1975 1976 if (i < 0) { 1977 printf("%s: start atw_si4126_read, SYNCTL busy\n", 1978 sc->sc_dev.dv_xname); 1979 return ETIMEDOUT; 1980 } 1981 1982 reg = sc->sc_synctl_rd | LSHIFT(addr, ATW_SYNCTL_DATA_MASK); 1983 1984 ATW_WRITE(sc, ATW_SYNCTL, reg); 1985 1986 for (i = 1000; --i >= 0; ) { 1987 DELAY(100); 1988 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0) 1989 break; 1990 } 1991 1992 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD); 1993 1994 if (i < 0) { 1995 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n", 1996 sc->sc_dev.dv_xname, reg); 1997 return ETIMEDOUT; 1998 } 1999 if (val != NULL) 2000 *val = MASK_AND_RSHIFT(ATW_READ(sc, ATW_SYNCTL), 2001 ATW_SYNCTL_DATA_MASK); 2002 return 0; 2003 } 2004 #endif /* ATW_SYNDEBUG */ 2005 2006 /* XXX is the endianness correct? test. */ 2007 #define atw_calchash(addr) \ 2008 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & 0x3f) 2009 2010 /* 2011 * atw_filter_setup: 2012 * 2013 * Set the ADM8211's receive filter. 2014 */ 2015 void 2016 atw_filter_setup(struct atw_softc *sc) 2017 { 2018 struct ieee80211com *ic = &sc->sc_ic; 2019 struct arpcom *ac = &ic->ic_ac; 2020 struct ifnet *ifp = &sc->sc_ic.ic_if; 2021 int hash; 2022 u_int32_t hashes[2]; 2023 struct ether_multi *enm; 2024 struct ether_multistep step; 2025 2026 /* According to comments in tlp_al981_filter_setup 2027 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its 2028 * multicast filter to be set while it is running. Hopefully 2029 * the ADM8211 is not the same! 2030 */ 2031 if ((ifp->if_flags & IFF_RUNNING) != 0) 2032 atw_idle(sc, ATW_NAR_SR); 2033 2034 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM); 2035 2036 /* XXX in scan mode, do not filter packets. Maybe this is 2037 * unnecessary. 2038 */ 2039 if (ic->ic_state == IEEE80211_S_SCAN || 2040 (ifp->if_flags & IFF_PROMISC) != 0) { 2041 sc->sc_opmode |= ATW_NAR_PR; 2042 goto allmulti; 2043 } 2044 2045 hashes[0] = hashes[1] = 0x0; 2046 2047 if (ac->ac_multirangecnt > 0) 2048 goto allmulti; 2049 2050 /* 2051 * Program the 64-bit multicast hash filter. 2052 */ 2053 ETHER_FIRST_MULTI(step, ac, enm); 2054 while (enm != NULL) { 2055 hash = atw_calchash(enm->enm_addrlo); 2056 hashes[hash >> 5] |= 1 << (hash & 0x1f); 2057 ETHER_NEXT_MULTI(step, enm); 2058 sc->sc_opmode |= ATW_NAR_MM; 2059 } 2060 ifp->if_flags &= ~IFF_ALLMULTI; 2061 goto setit; 2062 2063 allmulti: 2064 sc->sc_opmode |= ATW_NAR_MM; 2065 ifp->if_flags |= IFF_ALLMULTI; 2066 hashes[0] = hashes[1] = 0xffffffff; 2067 2068 setit: 2069 ATW_WRITE(sc, ATW_MAR0, hashes[0]); 2070 ATW_WRITE(sc, ATW_MAR1, hashes[1]); 2071 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2072 DELAY(20 * 1000); 2073 ATW_WRITE(sc, ATW_RDR, 0x1); 2074 2075 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname, 2076 ATW_READ(sc, ATW_NAR), sc->sc_opmode)); 2077 } 2078 2079 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match 2080 * a beacon's BSSID and SSID against the preferred BSSID and SSID 2081 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives 2082 * no beacon with the preferred BSSID and SSID in the number of 2083 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF. 2084 */ 2085 void 2086 atw_write_bssid(struct atw_softc *sc) 2087 { 2088 struct ieee80211com *ic = &sc->sc_ic; 2089 u_int8_t *bssid; 2090 2091 bssid = ic->ic_bss->ni_bssid; 2092 2093 ATW_WRITE(sc, ATW_BSSID0, 2094 LSHIFT(bssid[0], ATW_BSSID0_BSSIDB0_MASK) | 2095 LSHIFT(bssid[1], ATW_BSSID0_BSSIDB1_MASK) | 2096 LSHIFT(bssid[2], ATW_BSSID0_BSSIDB2_MASK) | 2097 LSHIFT(bssid[3], ATW_BSSID0_BSSIDB3_MASK)); 2098 2099 ATW_WRITE(sc, ATW_ABDA1, 2100 (ATW_READ(sc, ATW_ABDA1) & 2101 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) | 2102 LSHIFT(bssid[4], ATW_ABDA1_BSSIDB4_MASK) | 2103 LSHIFT(bssid[5], ATW_ABDA1_BSSIDB5_MASK)); 2104 2105 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname, 2106 ether_sprintf(sc->sc_bssid))); 2107 DPRINTF(sc, ("%s\n", ether_sprintf(bssid))); 2108 2109 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid)); 2110 } 2111 2112 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th 2113 * 16-bit word. 2114 */ 2115 void 2116 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen) 2117 { 2118 u_int i; 2119 u_int8_t *ptr; 2120 2121 memcpy(&sc->sc_sram[ofs], buf, buflen); 2122 2123 KASSERT(ofs % 2 == 0 && buflen % 2 == 0); 2124 2125 KASSERT(buflen + ofs <= sc->sc_sramlen); 2126 2127 ptr = &sc->sc_sram[ofs]; 2128 2129 for (i = 0; i < buflen; i += 2) { 2130 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR | 2131 LSHIFT((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK)); 2132 DELAY(atw_writewep_delay); 2133 2134 ATW_WRITE(sc, ATW_WESK, 2135 LSHIFT((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK)); 2136 DELAY(atw_writewep_delay); 2137 } 2138 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */ 2139 2140 if (sc->sc_if.if_flags & IFF_DEBUG) { 2141 int n_octets = 0; 2142 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n", 2143 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl); 2144 for (i = 0; i < buflen; i++) { 2145 printf(" %02x", ptr[i]); 2146 if (++n_octets % 24 == 0) 2147 printf("\n"); 2148 } 2149 if (n_octets % 24 != 0) 2150 printf("\n"); 2151 } 2152 } 2153 2154 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */ 2155 void 2156 atw_write_wep(struct atw_softc *sc) 2157 { 2158 struct ieee80211com *ic = &sc->sc_ic; 2159 #if 0 2160 u_int32_t reg; 2161 int i; 2162 #endif 2163 /* SRAM shared-key record format: key0 flags key1 ... key12 */ 2164 u_int8_t buf[IEEE80211_WEP_NKID] 2165 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */]; 2166 2167 sc->sc_wepctl = 0; 2168 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); 2169 2170 if ((ic->ic_flags & IEEE80211_F_WEPON) == 0) 2171 return; 2172 2173 memset(&buf[0][0], 0, sizeof(buf)); 2174 2175 #if 0 2176 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2177 if (ic->ic_nw_keys[i].k_len > 5) { 2178 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT; 2179 } else if (ic->ic_nw_keys[i].k_len != 0) { 2180 buf[i][1] = ATW_WEP_ENABLED; 2181 } else { 2182 buf[i][1] = 0; 2183 continue; 2184 } 2185 buf[i][0] = ic->ic_nw_keys[i].k_key[0]; 2186 memcpy(&buf[i][2], &ic->ic_nw_keys[i].k_key[1], 2187 ic->ic_nw_keys[i].k_len - 1); 2188 } 2189 2190 reg = ATW_READ(sc, ATW_MACTEST); 2191 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID; 2192 reg &= ~ATW_MACTEST_KEYID_MASK; 2193 reg |= LSHIFT(ic->ic_wep_txkey, ATW_MACTEST_KEYID_MASK); 2194 ATW_WRITE(sc, ATW_MACTEST, reg); 2195 2196 sc->sc_wepctl = ATW_WEPCTL_WEPENABLE; 2197 2198 switch (sc->sc_rev) { 2199 case ATW_REVISION_AB: 2200 case ATW_REVISION_AF: 2201 /* Bypass WEP on Rx. */ 2202 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP; 2203 break; 2204 default: 2205 break; 2206 } 2207 #endif 2208 2209 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0], 2210 sizeof(buf)); 2211 } 2212 2213 void 2214 atw_change_ibss(struct atw_softc *sc) 2215 { 2216 atw_predict_beacon(sc); 2217 atw_write_bssid(sc); 2218 atw_start_beacon(sc, 1); 2219 } 2220 2221 #ifndef IEEE80211_STA_ONLY 2222 void 2223 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2224 struct ieee80211_node *ni, struct ieee80211_rxinfo *rxi, int subtype) 2225 { 2226 struct atw_softc *sc = (struct atw_softc*)ic->ic_softc; 2227 2228 /* The ADM8211A answers probe requests. */ 2229 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ && 2230 sc->sc_rev < ATW_REVISION_BA) 2231 return; 2232 2233 (*sc->sc_recv_mgmt)(ic, m, ni, rxi, subtype); 2234 2235 switch (subtype) { 2236 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2237 case IEEE80211_FC0_SUBTYPE_BEACON: 2238 if (ic->ic_opmode != IEEE80211_M_IBSS || 2239 ic->ic_state != IEEE80211_S_RUN) 2240 break; 2241 if (ieee80211_ibss_merge(ic, ni, atw_get_tsft(sc)) == ENETRESET) 2242 atw_change_ibss(sc); 2243 break; 2244 default: 2245 break; 2246 } 2247 return; 2248 } 2249 #endif 2250 2251 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211. 2252 * In ad hoc mode, the SSID is written to the beacons sent by the 2253 * ADM8211. In both ad hoc and infrastructure mode, beacons received 2254 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF 2255 * indications. 2256 */ 2257 void 2258 atw_write_ssid(struct atw_softc *sc) 2259 { 2260 struct ieee80211com *ic = &sc->sc_ic; 2261 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but 2262 * it only expects the element length, not its ID. 2263 */ 2264 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)]; 2265 2266 memset(buf, 0, sizeof(buf)); 2267 buf[0] = ic->ic_bss->ni_esslen; 2268 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen); 2269 2270 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf, 2271 roundup(1 + ic->ic_bss->ni_esslen, 2)); 2272 } 2273 2274 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211. 2275 * In ad hoc mode, the supported rates are written to beacons sent by the 2276 * ADM8211. 2277 */ 2278 void 2279 atw_write_sup_rates(struct atw_softc *sc) 2280 { 2281 struct ieee80211com *ic = &sc->sc_ic; 2282 /* 2283 * There is not enough space in the ADM8211 SRAM for the 2284 * full IEEE80211_RATE_MAXSIZE 2285 */ 2286 u_int8_t buf[12]; 2287 u_int8_t nrates; 2288 2289 memset(buf, 0, sizeof(buf)); 2290 if (ic->ic_bss->ni_rates.rs_nrates > sizeof(buf) - 1) 2291 nrates = sizeof(buf) - 1; 2292 else 2293 nrates = ic->ic_bss->ni_rates.rs_nrates; 2294 buf[0] = nrates; 2295 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates, nrates); 2296 2297 /* XXX deal with rev BA bug linux driver talks of? */ 2298 2299 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf)); 2300 } 2301 2302 /* Start/stop sending beacons. */ 2303 void 2304 atw_start_beacon(struct atw_softc *sc, int start) 2305 { 2306 struct ieee80211com *ic = &sc->sc_ic; 2307 #ifndef IEEE80211_STA_ONLY 2308 uint16_t chan; 2309 uint32_t bpli; 2310 #endif 2311 uint32_t bcnt, cap0, cap1, capinfo; 2312 size_t len; 2313 2314 if (ATW_IS_ENABLED(sc) == 0) 2315 return; 2316 2317 /* start beacons */ 2318 len = sizeof(struct ieee80211_frame) + 2319 8 /* timestamp */ + 2 /* beacon interval */ + 2320 2 /* capability info */ + 2321 2 + ic->ic_bss->ni_esslen /* SSID element */ + 2322 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ + 2323 3 /* DS parameters */ + 2324 IEEE80211_CRC_LEN; 2325 2326 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK; 2327 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK; 2328 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK; 2329 2330 ATW_WRITE(sc, ATW_BCNT, bcnt); 2331 ATW_WRITE(sc, ATW_CAP1, cap1); 2332 2333 if (!start) 2334 return; 2335 2336 /* TBD use ni_capinfo */ 2337 2338 capinfo = 0; 2339 if (sc->sc_flags & ATWF_SHORT_PREAMBLE) 2340 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE; 2341 if (ic->ic_flags & IEEE80211_F_WEPON) 2342 capinfo |= IEEE80211_CAPINFO_PRIVACY; 2343 2344 #ifndef IEEE80211_STA_ONLY 2345 switch (ic->ic_opmode) { 2346 case IEEE80211_M_IBSS: 2347 len += 4; /* IBSS parameters */ 2348 capinfo |= IEEE80211_CAPINFO_IBSS; 2349 break; 2350 default: 2351 return; 2352 } 2353 2354 /* set listen interval 2355 * XXX do software units agree w/ hardware? 2356 */ 2357 bpli = LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2358 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK); 2359 2360 chan = ieee80211_chan2ieee(ic, ic->ic_bss->ni_chan); 2361 2362 bcnt |= LSHIFT(len, ATW_BCNT_BCNT_MASK); 2363 cap0 |= LSHIFT(chan, ATW_CAP0_CHN_MASK); 2364 cap1 |= LSHIFT(capinfo, ATW_CAP1_CAPI_MASK); 2365 2366 ATW_WRITE(sc, ATW_BCNT, bcnt); 2367 ATW_WRITE(sc, ATW_BPLI, bpli); 2368 ATW_WRITE(sc, ATW_CAP0, cap0); 2369 ATW_WRITE(sc, ATW_CAP1, cap1); 2370 2371 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n", 2372 sc->sc_dev.dv_xname, bcnt)); 2373 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n", 2374 sc->sc_dev.dv_xname, cap1)); 2375 #endif 2376 } 2377 2378 /* Return the 32 lsb of the last TSFT divisible by ival. */ 2379 static __inline uint32_t 2380 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival) 2381 { 2382 /* Following the reference driver's lead, I compute 2383 * 2384 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival) 2385 * 2386 * without using 64-bit arithmetic, using the following 2387 * relationship: 2388 * 2389 * (0x100000000 * H + L) % m 2390 * = ((0x100000000 % m) * H + L) % m 2391 * = (((0xffffffff + 1) % m) * H + L) % m 2392 * = ((0xffffffff % m + 1 % m) * H + L) % m 2393 * = ((0xffffffff % m + 1) * H + L) % m 2394 */ 2395 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival; 2396 } 2397 2398 uint64_t 2399 atw_get_tsft(struct atw_softc *sc) 2400 { 2401 int i; 2402 uint32_t tsfth, tsftl; 2403 for (i = 0; i < 2; i++) { 2404 tsfth = ATW_READ(sc, ATW_TSFTH); 2405 tsftl = ATW_READ(sc, ATW_TSFTL); 2406 if (ATW_READ(sc, ATW_TSFTH) == tsfth) 2407 break; 2408 } 2409 return ((uint64_t)tsfth << 32) | tsftl; 2410 } 2411 2412 /* If we've created an IBSS, write the TSF time in the ADM8211 to 2413 * the ieee80211com. 2414 * 2415 * Predict the next target beacon transmission time (TBTT) and 2416 * write it to the ADM8211. 2417 */ 2418 void 2419 atw_predict_beacon(struct atw_softc *sc) 2420 { 2421 #define TBTTOFS 20 /* TU */ 2422 2423 struct ieee80211com *ic = &sc->sc_ic; 2424 uint64_t tsft; 2425 uint32_t ival, past_even, tbtt, tsfth, tsftl; 2426 union { 2427 uint64_t word; 2428 uint8_t tstamp[8]; 2429 } u; 2430 2431 #ifndef IEEE80211_STA_ONLY 2432 if ((ic->ic_opmode == IEEE80211_M_IBSS) && 2433 (ic->ic_flags & IEEE80211_F_SIBSS)) { 2434 tsft = atw_get_tsft(sc); 2435 u.word = htole64(tsft); 2436 (void)memcpy(&ic->ic_bss->ni_tstamp[0], &u.tstamp[0], 2437 sizeof(ic->ic_bss->ni_tstamp)); 2438 } else 2439 #endif 2440 { 2441 (void)memcpy(&u, &ic->ic_bss->ni_tstamp[0], sizeof(u)); 2442 tsft = letoh64(u.word); 2443 } 2444 2445 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU; 2446 2447 tsftl = tsft & 0xFFFFFFFF; 2448 tsfth = tsft >> 32; 2449 2450 /* We sent/received the last beacon `past' microseconds 2451 * after the interval divided the TSF timer. 2452 */ 2453 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival); 2454 2455 /* Skip ten beacons so that the TBTT cannot pass before 2456 * we've programmed it. Ten is an arbitrary number. 2457 */ 2458 tbtt = past_even + ival * 10; 2459 2460 ATW_WRITE(sc, ATW_TOFS1, 2461 LSHIFT(1, ATW_TOFS1_TSFTOFSR_MASK) | 2462 LSHIFT(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) | 2463 LSHIFT(MASK_AND_RSHIFT(tbtt - TBTTOFS * IEEE80211_DUR_TU, 2464 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK)); 2465 #undef TBTTOFS 2466 } 2467 2468 void 2469 atw_next_scan(void *arg) 2470 { 2471 struct atw_softc *sc = arg; 2472 struct ieee80211com *ic = &sc->sc_ic; 2473 struct ifnet *ifp = &ic->ic_if; 2474 int s; 2475 2476 /* don't call atw_start w/o network interrupts blocked */ 2477 s = splnet(); 2478 if (ic->ic_state == IEEE80211_S_SCAN) 2479 ieee80211_next_scan(ifp); 2480 splx(s); 2481 } 2482 2483 /* Synchronize the hardware state with the software state. */ 2484 int 2485 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 2486 { 2487 struct ifnet *ifp = &ic->ic_if; 2488 struct atw_softc *sc = ifp->if_softc; 2489 enum ieee80211_state ostate = ic->ic_state; 2490 int error; 2491 2492 if (nstate == IEEE80211_S_INIT) { 2493 timeout_del(&sc->sc_scan_to); 2494 sc->sc_cur_chan = IEEE80211_CHAN_ANY; 2495 atw_start_beacon(sc, 0); 2496 return (*sc->sc_newstate)(ic, nstate, arg); 2497 } 2498 2499 if ((error = atw_tune(sc)) != 0) 2500 return error; 2501 2502 switch (nstate) { 2503 case IEEE80211_S_ASSOC: 2504 break; 2505 case IEEE80211_S_INIT: 2506 panic("%s: unexpected state IEEE80211_S_INIT", __func__); 2507 break; 2508 case IEEE80211_S_SCAN: 2509 timeout_add_msec(&sc->sc_scan_to, atw_dwelltime); 2510 break; 2511 case IEEE80211_S_RUN: 2512 if (ic->ic_opmode == IEEE80211_M_STA) 2513 break; 2514 /*FALLTHROUGH*/ 2515 case IEEE80211_S_AUTH: 2516 atw_write_bssid(sc); 2517 atw_write_ssid(sc); 2518 atw_write_sup_rates(sc); 2519 2520 if ( 2521 #ifndef IEEE80211_STA_ONLY 2522 ic->ic_opmode == IEEE80211_M_AHDEMO || 2523 #endif 2524 ic->ic_opmode == IEEE80211_M_MONITOR) 2525 break; 2526 2527 /* set listen interval 2528 * XXX do software units agree w/ hardware? 2529 */ 2530 ATW_WRITE(sc, ATW_BPLI, 2531 LSHIFT(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) | 2532 LSHIFT(ic->ic_lintval / ic->ic_bss->ni_intval, 2533 ATW_BPLI_LI_MASK)); 2534 2535 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", 2536 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_BPLI))); 2537 2538 atw_predict_beacon(sc); 2539 break; 2540 } 2541 2542 if (nstate != IEEE80211_S_SCAN) 2543 timeout_del(&sc->sc_scan_to); 2544 2545 #ifndef IEEE80211_STA_ONLY 2546 if (nstate == IEEE80211_S_RUN && 2547 ic->ic_opmode == IEEE80211_M_IBSS) 2548 atw_start_beacon(sc, 1); 2549 else 2550 #endif 2551 atw_start_beacon(sc, 0); 2552 2553 error = (*sc->sc_newstate)(ic, nstate, arg); 2554 2555 if (ostate == IEEE80211_S_INIT && nstate == IEEE80211_S_SCAN) 2556 atw_write_bssid(sc); 2557 2558 return error; 2559 } 2560 2561 /* 2562 * atw_add_rxbuf: 2563 * 2564 * Add a receive buffer to the indicated descriptor. 2565 */ 2566 int 2567 atw_add_rxbuf(struct atw_softc *sc, int idx) 2568 { 2569 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2570 struct mbuf *m; 2571 int error; 2572 2573 MGETHDR(m, M_DONTWAIT, MT_DATA); 2574 if (m == NULL) 2575 return (ENOBUFS); 2576 2577 MCLGET(m, M_DONTWAIT); 2578 if ((m->m_flags & M_EXT) == 0) { 2579 m_freem(m); 2580 return (ENOBUFS); 2581 } 2582 2583 if (rxs->rxs_mbuf != NULL) 2584 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2585 2586 rxs->rxs_mbuf = m; 2587 2588 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap, 2589 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2590 BUS_DMA_READ|BUS_DMA_NOWAIT); 2591 if (error) { 2592 printf("%s: can't load rx DMA map %d, error = %d\n", 2593 sc->sc_dev.dv_xname, idx, error); 2594 panic("atw_add_rxbuf"); /* XXX */ 2595 } 2596 2597 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 2598 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2599 2600 ATW_INIT_RXDESC(sc, idx); 2601 2602 return (0); 2603 } 2604 2605 /* 2606 * Release any queued transmit buffers. 2607 */ 2608 void 2609 atw_txdrain(struct atw_softc *sc) 2610 { 2611 struct atw_txsoft *txs; 2612 2613 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 2614 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 2615 if (txs->txs_mbuf != NULL) { 2616 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2617 m_freem(txs->txs_mbuf); 2618 txs->txs_mbuf = NULL; 2619 } 2620 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 2621 } 2622 sc->sc_tx_timer = 0; 2623 } 2624 2625 /* 2626 * atw_stop: [ ifnet interface function ] 2627 * 2628 * Stop transmission on the interface. 2629 */ 2630 void 2631 atw_stop(struct ifnet *ifp, int disable) 2632 { 2633 struct atw_softc *sc = ifp->if_softc; 2634 struct ieee80211com *ic = &sc->sc_ic; 2635 2636 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2637 2638 /* 2639 * Mark the interface down and cancel the watchdog timer. 2640 */ 2641 ifp->if_flags &= ~IFF_RUNNING; 2642 ifq_clr_oactive(&ifp->if_snd); 2643 ifp->if_timer = 0; 2644 2645 /* Disable interrupts. */ 2646 ATW_WRITE(sc, ATW_IER, 0); 2647 2648 /* Stop the transmit and receive processes. */ 2649 sc->sc_opmode = 0; 2650 ATW_WRITE(sc, ATW_NAR, 0); 2651 DELAY(20 * 1000); 2652 ATW_WRITE(sc, ATW_TDBD, 0); 2653 ATW_WRITE(sc, ATW_TDBP, 0); 2654 ATW_WRITE(sc, ATW_RDB, 0); 2655 2656 atw_txdrain(sc); 2657 2658 if (disable) { 2659 atw_rxdrain(sc); 2660 atw_disable(sc); 2661 } 2662 2663 if (!disable) 2664 atw_reset(sc); 2665 } 2666 2667 /* 2668 * atw_rxdrain: 2669 * 2670 * Drain the receive queue. 2671 */ 2672 void 2673 atw_rxdrain(struct atw_softc *sc) 2674 { 2675 struct atw_rxsoft *rxs; 2676 int i; 2677 2678 for (i = 0; i < ATW_NRXDESC; i++) { 2679 rxs = &sc->sc_rxsoft[i]; 2680 if (rxs->rxs_mbuf == NULL) 2681 continue; 2682 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2683 m_freem(rxs->rxs_mbuf); 2684 rxs->rxs_mbuf = NULL; 2685 } 2686 } 2687 2688 /* 2689 * atw_detach: 2690 * 2691 * Detach an ADM8211 interface. 2692 */ 2693 int 2694 atw_detach(struct atw_softc *sc) 2695 { 2696 struct ifnet *ifp = &sc->sc_ic.ic_if; 2697 struct atw_rxsoft *rxs; 2698 struct atw_txsoft *txs; 2699 int i; 2700 2701 /* 2702 * Succeed now if there isn't any work to do. 2703 */ 2704 if ((sc->sc_flags & ATWF_ATTACHED) == 0) 2705 return (0); 2706 2707 timeout_del(&sc->sc_scan_to); 2708 2709 ieee80211_ifdetach(ifp); 2710 if_detach(ifp); 2711 2712 for (i = 0; i < ATW_NRXDESC; i++) { 2713 rxs = &sc->sc_rxsoft[i]; 2714 if (rxs->rxs_mbuf != NULL) { 2715 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 2716 m_freem(rxs->rxs_mbuf); 2717 rxs->rxs_mbuf = NULL; 2718 } 2719 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap); 2720 } 2721 for (i = 0; i < ATW_TXQUEUELEN; i++) { 2722 txs = &sc->sc_txsoft[i]; 2723 if (txs->txs_mbuf != NULL) { 2724 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 2725 m_freem(txs->txs_mbuf); 2726 txs->txs_mbuf = NULL; 2727 } 2728 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap); 2729 } 2730 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 2731 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 2732 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 2733 sizeof(struct atw_control_data)); 2734 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg); 2735 2736 if (sc->sc_srom) 2737 free(sc->sc_srom, M_DEVBUF, sc->sc_sromsz); 2738 2739 return (0); 2740 } 2741 2742 int 2743 atw_intr(void *arg) 2744 { 2745 struct atw_softc *sc = arg; 2746 struct ifnet *ifp = &sc->sc_ic.ic_if; 2747 u_int32_t status, rxstatus, txstatus, linkstatus; 2748 int handled = 0, txthresh; 2749 2750 #ifdef DEBUG 2751 if (ATW_IS_ENABLED(sc) == 0) 2752 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname); 2753 #endif 2754 2755 /* 2756 * If the interface isn't running, the interrupt couldn't 2757 * possibly have come from us. 2758 */ 2759 if ((ifp->if_flags & IFF_RUNNING) == 0 || 2760 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 2761 return (0); 2762 2763 for (;;) { 2764 status = ATW_READ(sc, ATW_STSR); 2765 2766 if (status) 2767 ATW_WRITE(sc, ATW_STSR, status); 2768 2769 #ifdef ATW_DEBUG 2770 #define PRINTINTR(flag) do { \ 2771 if ((status & flag) != 0) { \ 2772 printf("%s" #flag, delim); \ 2773 delim = ","; \ 2774 } \ 2775 } while (0) 2776 2777 if (atw_debug > 1 && status) { 2778 const char *delim = "<"; 2779 2780 printf("%s: reg[STSR] = %x", 2781 sc->sc_dev.dv_xname, status); 2782 2783 PRINTINTR(ATW_INTR_FBE); 2784 PRINTINTR(ATW_INTR_LINKOFF); 2785 PRINTINTR(ATW_INTR_LINKON); 2786 PRINTINTR(ATW_INTR_RCI); 2787 PRINTINTR(ATW_INTR_RDU); 2788 PRINTINTR(ATW_INTR_REIS); 2789 PRINTINTR(ATW_INTR_RPS); 2790 PRINTINTR(ATW_INTR_TCI); 2791 PRINTINTR(ATW_INTR_TDU); 2792 PRINTINTR(ATW_INTR_TLT); 2793 PRINTINTR(ATW_INTR_TPS); 2794 PRINTINTR(ATW_INTR_TRT); 2795 PRINTINTR(ATW_INTR_TUF); 2796 PRINTINTR(ATW_INTR_BCNTC); 2797 PRINTINTR(ATW_INTR_ATIME); 2798 PRINTINTR(ATW_INTR_TBTT); 2799 PRINTINTR(ATW_INTR_TSCZ); 2800 PRINTINTR(ATW_INTR_TSFTF); 2801 printf(">\n"); 2802 } 2803 #undef PRINTINTR 2804 #endif /* ATW_DEBUG */ 2805 2806 if ((status & sc->sc_inten) == 0) 2807 break; 2808 2809 handled = 1; 2810 2811 rxstatus = status & sc->sc_rxint_mask; 2812 txstatus = status & sc->sc_txint_mask; 2813 linkstatus = status & sc->sc_linkint_mask; 2814 2815 if (linkstatus) { 2816 atw_linkintr(sc, linkstatus); 2817 } 2818 2819 if (rxstatus) { 2820 /* Grab any new packets. */ 2821 atw_rxintr(sc); 2822 2823 if (rxstatus & ATW_INTR_RDU) { 2824 printf("%s: receive ring overrun\n", 2825 sc->sc_dev.dv_xname); 2826 /* Get the receive process going again. */ 2827 ATW_WRITE(sc, ATW_RDR, 0x1); 2828 break; 2829 } 2830 } 2831 2832 if (txstatus) { 2833 /* Sweep up transmit descriptors. */ 2834 atw_txintr(sc); 2835 2836 if (txstatus & ATW_INTR_TLT) 2837 DPRINTF(sc, ("%s: tx lifetime exceeded\n", 2838 sc->sc_dev.dv_xname)); 2839 2840 if (txstatus & ATW_INTR_TRT) 2841 DPRINTF(sc, ("%s: tx retry limit exceeded\n", 2842 sc->sc_dev.dv_xname)); 2843 2844 /* If Tx under-run, increase our transmit threshold 2845 * if another is available. 2846 */ 2847 txthresh = sc->sc_txthresh + 1; 2848 if ((txstatus & ATW_INTR_TUF) && 2849 sc->sc_txth[txthresh].txth_name != NULL) { 2850 /* Idle the transmit process. */ 2851 atw_idle(sc, ATW_NAR_ST); 2852 2853 sc->sc_txthresh = txthresh; 2854 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF); 2855 sc->sc_opmode |= 2856 sc->sc_txth[txthresh].txth_opmode; 2857 printf("%s: transmit underrun; new " 2858 "threshold: %s\n", sc->sc_dev.dv_xname, 2859 sc->sc_txth[txthresh].txth_name); 2860 2861 /* Set the new threshold and restart 2862 * the transmit process. 2863 */ 2864 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode); 2865 DELAY(20 * 1000); 2866 ATW_WRITE(sc, ATW_RDR, 0x1); 2867 /* XXX Log every Nth underrun from 2868 * XXX now on? 2869 */ 2870 } 2871 } 2872 2873 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) { 2874 if (status & ATW_INTR_TPS) 2875 printf("%s: transmit process stopped\n", 2876 sc->sc_dev.dv_xname); 2877 if (status & ATW_INTR_RPS) 2878 printf("%s: receive process stopped\n", 2879 sc->sc_dev.dv_xname); 2880 (void)atw_init(ifp); 2881 break; 2882 } 2883 2884 if (status & ATW_INTR_FBE) { 2885 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname); 2886 (void)atw_init(ifp); 2887 break; 2888 } 2889 2890 /* 2891 * Not handled: 2892 * 2893 * Transmit buffer unavailable -- normal 2894 * condition, nothing to do, really. 2895 * 2896 * Early receive interrupt -- not available on 2897 * all chips, we just use RI. We also only 2898 * use single-segment receive DMA, so this 2899 * is mostly useless. 2900 * 2901 * TBD others 2902 */ 2903 } 2904 2905 /* Try to get more packets going. */ 2906 atw_start(ifp); 2907 2908 return (handled); 2909 } 2910 2911 /* 2912 * atw_idle: 2913 * 2914 * Cause the transmit and/or receive processes to go idle. 2915 * 2916 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx 2917 * process in STSR if I clear SR or ST after the process has already 2918 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0 2919 * do not seem to be too reliable. Perhaps I have the sense of the 2920 * Rx bits switched with the Tx bits? 2921 */ 2922 void 2923 atw_idle(struct atw_softc *sc, u_int32_t bits) 2924 { 2925 u_int32_t ackmask = 0, opmode, stsr, test0; 2926 int i, s; 2927 2928 s = splnet(); 2929 2930 opmode = sc->sc_opmode & ~bits; 2931 2932 if (bits & ATW_NAR_SR) 2933 ackmask |= ATW_INTR_RPS; 2934 2935 if (bits & ATW_NAR_ST) { 2936 ackmask |= ATW_INTR_TPS; 2937 /* set ATW_NAR_HF to flush TX FIFO. */ 2938 opmode |= ATW_NAR_HF; 2939 } 2940 2941 ATW_WRITE(sc, ATW_NAR, opmode); 2942 DELAY(20 * 1000); 2943 2944 for (i = 0; i < 10; i++) { 2945 stsr = ATW_READ(sc, ATW_STSR); 2946 if ((stsr & ackmask) == ackmask) 2947 break; 2948 DELAY(1000); 2949 } 2950 2951 ATW_WRITE(sc, ATW_STSR, stsr & ackmask); 2952 2953 if ((stsr & ackmask) == ackmask) 2954 goto out; 2955 2956 test0 = ATW_READ(sc, ATW_TEST0); 2957 2958 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 && 2959 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) { 2960 DPRINTF2(sc, ("%s: transmit process not idle [%s]\n", 2961 sc->sc_dev.dv_xname, 2962 atw_tx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_TS_MASK)])); 2963 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2964 sc->sc_dev.dv_xname, bits, test0, stsr)); 2965 } 2966 2967 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 && 2968 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) { 2969 DPRINTF2(sc, ("%s: receive process not idle [%s]\n", 2970 sc->sc_dev.dv_xname, 2971 atw_rx_state[MASK_AND_RSHIFT(test0, ATW_TEST0_RS_MASK)])); 2972 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n", 2973 sc->sc_dev.dv_xname, bits, test0, stsr)); 2974 } 2975 out: 2976 if ((bits & ATW_NAR_ST) != 0) 2977 atw_txdrain(sc); 2978 splx(s); 2979 return; 2980 } 2981 2982 /* 2983 * atw_linkintr: 2984 * 2985 * Helper; handle link-status interrupts. 2986 */ 2987 void 2988 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus) 2989 { 2990 struct ieee80211com *ic = &sc->sc_ic; 2991 2992 if (ic->ic_state != IEEE80211_S_RUN) 2993 return; 2994 2995 if (linkstatus & ATW_INTR_LINKON) { 2996 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname)); 2997 sc->sc_rescan_timer = 0; 2998 } else if (linkstatus & ATW_INTR_LINKOFF) { 2999 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname)); 3000 if (ic->ic_opmode != IEEE80211_M_STA) 3001 return; 3002 sc->sc_rescan_timer = 3; 3003 ic->ic_if.if_timer = 1; 3004 } 3005 } 3006 3007 #if 0 3008 static __inline int 3009 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame *wh) 3010 { 3011 if ((sc->sc_ic.ic_flags & IEEE80211_F_WEPON) == 0) 3012 return 0; 3013 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0) 3014 return 0; 3015 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0; 3016 } 3017 #endif 3018 3019 /* 3020 * atw_rxintr: 3021 * 3022 * Helper; handle receive interrupts. 3023 */ 3024 void 3025 atw_rxintr(struct atw_softc *sc) 3026 { 3027 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 3028 static int rate_tbl[] = {2, 4, 11, 22, 44}; 3029 struct ieee80211com *ic = &sc->sc_ic; 3030 struct ieee80211_rxinfo rxi; 3031 struct ieee80211_node *ni; 3032 struct ieee80211_frame *wh; 3033 struct ifnet *ifp = &ic->ic_if; 3034 struct atw_rxsoft *rxs; 3035 struct mbuf *m; 3036 u_int32_t rxstat; 3037 int i, len, rate, rate0; 3038 u_int32_t rssi, rssi0; 3039 3040 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) { 3041 rxs = &sc->sc_rxsoft[i]; 3042 3043 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3044 3045 rxstat = letoh32(sc->sc_rxdescs[i].ar_stat); 3046 rssi0 = letoh32(sc->sc_rxdescs[i].ar_rssi); 3047 rate0 = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_RXDR_MASK); 3048 3049 if (rxstat & ATW_RXSTAT_OWN) 3050 break; /* We have processed all receive buffers. */ 3051 3052 DPRINTF3(sc, 3053 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n", 3054 sc->sc_dev.dv_xname, 3055 rxstat, rssi0, 3056 letoh32(sc->sc_rxdescs[i].ar_buf1), 3057 letoh32(sc->sc_rxdescs[i].ar_buf2))); 3058 3059 /* 3060 * Make sure the packet fits in one buffer. This should 3061 * always be the case. 3062 */ 3063 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) != 3064 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) { 3065 printf("%s: incoming packet spilled, resetting\n", 3066 sc->sc_dev.dv_xname); 3067 (void)atw_init(ifp); 3068 return; 3069 } 3070 3071 /* 3072 * If an error occurred, update stats, clear the status 3073 * word, and leave the packet buffer in place. It will 3074 * simply be reused the next time the ring comes around. 3075 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long 3076 * error. 3077 */ 3078 3079 if ((rxstat & ATW_RXSTAT_ES) != 0 && 3080 ((sc->sc_ic.ic_if.if_capabilities & IFCAP_VLAN_MTU) == 0 || 3081 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE | 3082 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E | 3083 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E | 3084 ATW_RXSTAT_ICVE)) != 0)) { 3085 #define PRINTERR(bit, str) \ 3086 if (rxstat & (bit)) \ 3087 printf("%s: receive error: %s\n", \ 3088 sc->sc_dev.dv_xname, str) 3089 ifp->if_ierrors++; 3090 PRINTERR(ATW_RXSTAT_DE, "descriptor error"); 3091 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error"); 3092 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error"); 3093 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error"); 3094 PRINTERR(ATW_RXSTAT_RXTOE, "time-out"); 3095 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error"); 3096 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error"); 3097 #undef PRINTERR 3098 ATW_INIT_RXDESC(sc, i); 3099 continue; 3100 } 3101 3102 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3103 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 3104 3105 /* 3106 * No errors; receive the packet. Note the ADM8211 3107 * includes the CRC in promiscuous mode. 3108 */ 3109 len = MASK_AND_RSHIFT(rxstat, ATW_RXSTAT_FL_MASK); 3110 3111 /* 3112 * Allocate a new mbuf cluster. If that fails, we are 3113 * out of memory, and must drop the packet and recycle 3114 * the buffer that's already attached to this descriptor. 3115 */ 3116 m = rxs->rxs_mbuf; 3117 if (atw_add_rxbuf(sc, i) != 0) { 3118 ifp->if_ierrors++; 3119 ATW_INIT_RXDESC(sc, i); 3120 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0, 3121 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 3122 continue; 3123 } 3124 3125 if (sc->sc_opmode & ATW_NAR_PR) 3126 len -= IEEE80211_CRC_LEN; 3127 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len); 3128 3129 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0])) 3130 rate = 0; 3131 else 3132 rate = rate_tbl[rate0]; 3133 3134 /* The RSSI comes straight from a register in the 3135 * baseband processor. I know that for the RF3000, 3136 * the RSSI register also contains the antenna-selection 3137 * bits. Mask those off. 3138 * 3139 * TBD Treat other basebands. 3140 */ 3141 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD) 3142 rssi = rssi0 & RF3000_RSSI_MASK; 3143 else 3144 rssi = rssi0; 3145 3146 #if NBPFILTER > 0 3147 /* Pass this up to any BPF listeners. */ 3148 if (sc->sc_radiobpf != NULL) { 3149 struct mbuf mb; 3150 3151 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap; 3152 3153 tap->ar_rate = rate; 3154 tap->ar_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3155 tap->ar_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3156 3157 /* TBD verify units are dB */ 3158 tap->ar_antsignal = (int)rssi; 3159 /* TBD tap->ar_flags */ 3160 3161 mb.m_data = (caddr_t)tap; 3162 mb.m_len = tap->ar_ihdr.it_len; 3163 mb.m_next = m; 3164 mb.m_nextpkt = NULL; 3165 mb.m_type = 0; 3166 mb.m_flags = 0; 3167 bpf_mtap(sc->sc_radiobpf, &mb, BPF_DIRECTION_IN); 3168 } 3169 #endif /* NBPFILTER > 0 */ 3170 3171 wh = mtod(m, struct ieee80211_frame *); 3172 ni = ieee80211_find_rxnode(ic, wh); 3173 memset(&rxi, 0, sizeof(rxi)); 3174 #if 0 3175 if (atw_hw_decrypted(sc, wh)) { 3176 wh->i_fc[1] &= ~IEEE80211_FC1_WEP; 3177 rxi.rxi_flags |= IEEE80211_RXI_HWDEC; 3178 } 3179 #endif 3180 rxi.rxi_rssi = (int)rssi; 3181 ieee80211_inputm(ifp, m, ni, &rxi, &ml); 3182 /* 3183 * The frame may have caused the node to be marked for 3184 * reclamation (e.g. in response to a DEAUTH message) 3185 * so use release_node here instead of unref_node. 3186 */ 3187 ieee80211_release_node(ic, ni); 3188 } 3189 if_input(ifp, &ml); 3190 3191 /* Update the receive pointer. */ 3192 sc->sc_rxptr = i; 3193 } 3194 3195 /* 3196 * atw_txintr: 3197 * 3198 * Helper; handle transmit interrupts. 3199 */ 3200 void 3201 atw_txintr(struct atw_softc *sc) 3202 { 3203 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \ 3204 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR) 3205 #define TXSTAT_FMT "\20\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \ 3206 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT" 3207 struct ifnet *ifp = &sc->sc_ic.ic_if; 3208 struct atw_txsoft *txs; 3209 u_int32_t txstat; 3210 3211 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n", 3212 sc->sc_dev.dv_xname, sc->sc_flags)); 3213 3214 ifq_clr_oactive(&ifp->if_snd); 3215 3216 /* 3217 * Go through our Tx list and free mbufs for those 3218 * frames that have been transmitted. 3219 */ 3220 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 3221 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1, 3222 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3223 3224 #ifdef ATW_DEBUG 3225 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3226 int i; 3227 printf(" txsoft %p transmit chain:\n", txs); 3228 ATW_CDTXSYNC(sc, txs->txs_firstdesc, 3229 txs->txs_ndescs - 1, 3230 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3231 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) { 3232 printf(" descriptor %d:\n", i); 3233 printf(" at_status: 0x%08x\n", 3234 letoh32(sc->sc_txdescs[i].at_stat)); 3235 printf(" at_flags: 0x%08x\n", 3236 letoh32(sc->sc_txdescs[i].at_flags)); 3237 printf(" at_buf1: 0x%08x\n", 3238 letoh32(sc->sc_txdescs[i].at_buf1)); 3239 printf(" at_buf2: 0x%08x\n", 3240 letoh32(sc->sc_txdescs[i].at_buf2)); 3241 if (i == txs->txs_lastdesc) 3242 break; 3243 } 3244 } 3245 #endif 3246 3247 txstat = letoh32(sc->sc_txdescs[txs->txs_lastdesc].at_stat); 3248 if (txstat & ATW_TXSTAT_OWN) 3249 break; 3250 3251 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 3252 3253 sc->sc_txfree += txs->txs_ndescs; 3254 3255 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap, 3256 0, txs->txs_dmamap->dm_mapsize, 3257 BUS_DMASYNC_POSTWRITE); 3258 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap); 3259 m_freem(txs->txs_mbuf); 3260 txs->txs_mbuf = NULL; 3261 3262 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 3263 3264 if ((ifp->if_flags & IFF_DEBUG) != 0 && 3265 (txstat & TXSTAT_ERRMASK) != 0) { 3266 printf("%s: txstat %b %d\n", sc->sc_dev.dv_xname, 3267 txstat & TXSTAT_ERRMASK, TXSTAT_FMT, 3268 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK)); 3269 } 3270 3271 /* 3272 * Check for errors and collisions. 3273 */ 3274 if (txstat & ATW_TXSTAT_TUF) 3275 sc->sc_stats.ts_tx_tuf++; 3276 if (txstat & ATW_TXSTAT_TLT) 3277 sc->sc_stats.ts_tx_tlt++; 3278 if (txstat & ATW_TXSTAT_TRT) 3279 sc->sc_stats.ts_tx_trt++; 3280 if (txstat & ATW_TXSTAT_TRO) 3281 sc->sc_stats.ts_tx_tro++; 3282 if (txstat & ATW_TXSTAT_SOFBR) { 3283 sc->sc_stats.ts_tx_sofbr++; 3284 } 3285 3286 if ((txstat & ATW_TXSTAT_ES) == 0) 3287 ifp->if_collisions += 3288 MASK_AND_RSHIFT(txstat, ATW_TXSTAT_ARC_MASK); 3289 else 3290 ifp->if_oerrors++; 3291 } 3292 3293 /* 3294 * If there are no more pending transmissions, cancel the watchdog 3295 * timer. 3296 */ 3297 if (txs == NULL) 3298 sc->sc_tx_timer = 0; 3299 #undef TXSTAT_ERRMASK 3300 #undef TXSTAT_FMT 3301 } 3302 3303 /* 3304 * atw_watchdog: [ifnet interface function] 3305 * 3306 * Watchdog timer handler. 3307 */ 3308 void 3309 atw_watchdog(struct ifnet *ifp) 3310 { 3311 struct atw_softc *sc = ifp->if_softc; 3312 struct ieee80211com *ic = &sc->sc_ic; 3313 uint32_t test1, rra, rwa; 3314 3315 ifp->if_timer = 0; 3316 if (ATW_IS_ENABLED(sc) == 0) 3317 return; 3318 3319 if (sc->sc_rescan_timer) { 3320 if (--sc->sc_rescan_timer == 0) 3321 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3322 } 3323 if (sc->sc_tx_timer) { 3324 if (--sc->sc_tx_timer == 0 && 3325 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) { 3326 printf("%s: transmit timeout\n", ifp->if_xname); 3327 ifp->if_oerrors++; 3328 (void)atw_init(ifp); 3329 atw_start(ifp); 3330 } 3331 } 3332 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0) 3333 ifp->if_timer = 1; 3334 3335 /* 3336 * ADM8211B seems to stall every so often, check for this. 3337 * These bits are what the Linux driver checks, they don't 3338 * seem to be documented by ADMTek/Infineon? 3339 */ 3340 if (sc->sc_rev == ATW_REVISION_BA) { 3341 test1 = ATW_READ(sc, ATW_TEST1); 3342 rra = (test1 >> 12) & 0x1ff; 3343 rwa = (test1 >> 2) & 0x1ff; 3344 3345 if ((rra != rwa) && !(test1 & 0x2)) { 3346 atw_init(ifp); 3347 atw_start(ifp); 3348 } 3349 } 3350 3351 ieee80211_watchdog(ifp); 3352 } 3353 3354 /* 3355 * Arguments in: 3356 * 3357 * paylen: payload length (no FCS, no WEP header) 3358 * 3359 * hdrlen: header length 3360 * 3361 * rate: MSDU speed, units 500kb/s 3362 * 3363 * flags: IEEE80211_F_SHPREAMBLE (use short preamble), 3364 * IEEE80211_F_SHSLOT (use short slot length) 3365 * 3366 * Arguments out: 3367 * 3368 * d: 802.11 Duration field for RTS, 3369 * 802.11 Duration field for data frame, 3370 * PLCP Length for data frame, 3371 * residual octets at end of data slot 3372 */ 3373 int 3374 atw_compute_duration1(int len, int use_ack, uint32_t flags, int rate, 3375 struct atw_duration *d) 3376 { 3377 int pre, ctsrate; 3378 int ack, bitlen, data_dur, remainder; 3379 3380 /* RTS reserves medium for SIFS | CTS | SIFS | (DATA) | SIFS | ACK 3381 * DATA reserves medium for SIFS | ACK 3382 * 3383 * XXXMYC: no ACK on multicast/broadcast or control packets 3384 */ 3385 3386 bitlen = len * 8; 3387 3388 pre = IEEE80211_DUR_DS_SIFS; 3389 if ((flags & IEEE80211_F_SHPREAMBLE) != 0) 3390 pre += IEEE80211_DUR_DS_SHORT_PREAMBLE + 3391 IEEE80211_DUR_DS_FAST_PLCPHDR; 3392 else 3393 pre += IEEE80211_DUR_DS_LONG_PREAMBLE + 3394 IEEE80211_DUR_DS_SLOW_PLCPHDR; 3395 3396 d->d_residue = 0; 3397 data_dur = (bitlen * 2) / rate; 3398 remainder = (bitlen * 2) % rate; 3399 if (remainder != 0) { 3400 d->d_residue = (rate - remainder) / 16; 3401 data_dur++; 3402 } 3403 3404 switch (rate) { 3405 case 2: /* 1 Mb/s */ 3406 case 4: /* 2 Mb/s */ 3407 /* 1 - 2 Mb/s WLAN: send ACK/CTS at 1 Mb/s */ 3408 ctsrate = 2; 3409 break; 3410 case 11: /* 5.5 Mb/s */ 3411 case 22: /* 11 Mb/s */ 3412 case 44: /* 22 Mb/s */ 3413 /* 5.5 - 11 Mb/s WLAN: send ACK/CTS at 2 Mb/s */ 3414 ctsrate = 4; 3415 break; 3416 default: 3417 /* TBD */ 3418 return -1; 3419 } 3420 3421 d->d_plcp_len = data_dur; 3422 3423 ack = (use_ack) ? pre + (IEEE80211_DUR_DS_SLOW_ACK * 2) / ctsrate : 0; 3424 3425 d->d_rts_dur = 3426 pre + (IEEE80211_DUR_DS_SLOW_CTS * 2) / ctsrate + 3427 pre + data_dur + 3428 ack; 3429 3430 d->d_data_dur = ack; 3431 3432 return 0; 3433 } 3434 3435 /* 3436 * Arguments in: 3437 * 3438 * wh: 802.11 header 3439 * 3440 * len: packet length 3441 * 3442 * rate: MSDU speed, units 500kb/s 3443 * 3444 * fraglen: fragment length, set to maximum (or higher) for no 3445 * fragmentation 3446 * 3447 * flags: IEEE80211_F_WEPON (hardware adds WEP), 3448 * IEEE80211_F_SHPREAMBLE (use short preamble), 3449 * IEEE80211_F_SHSLOT (use short slot length) 3450 * 3451 * Arguments out: 3452 * 3453 * d0: 802.11 Duration fields (RTS/Data), PLCP Length, Service fields 3454 * of first/only fragment 3455 * 3456 * dn: 802.11 Duration fields (RTS/Data), PLCP Length, Service fields 3457 * of first/only fragment 3458 */ 3459 int 3460 atw_compute_duration(struct ieee80211_frame *wh, int len, uint32_t flags, 3461 int fraglen, int rate, struct atw_duration *d0, struct atw_duration *dn, 3462 int *npktp, int debug) 3463 { 3464 int ack, rc; 3465 int firstlen, hdrlen, lastlen, lastlen0, npkt, overlen, paylen; 3466 3467 if (ieee80211_has_addr4(wh)) 3468 hdrlen = sizeof(struct ieee80211_frame_addr4); 3469 else 3470 hdrlen = sizeof(struct ieee80211_frame); 3471 3472 paylen = len - hdrlen; 3473 3474 if ((flags & IEEE80211_F_WEPON) != 0) 3475 overlen = IEEE80211_WEP_TOTLEN + IEEE80211_CRC_LEN; 3476 else 3477 overlen = IEEE80211_CRC_LEN; 3478 3479 npkt = paylen / fraglen; 3480 lastlen0 = paylen % fraglen; 3481 3482 if (npkt == 0) /* no fragments */ 3483 lastlen = paylen + overlen; 3484 else if (lastlen0 != 0) { /* a short "tail" fragment */ 3485 lastlen = lastlen0 + overlen; 3486 npkt++; 3487 } else /* full-length "tail" fragment */ 3488 lastlen = fraglen + overlen; 3489 3490 if (npktp != NULL) 3491 *npktp = npkt; 3492 3493 if (npkt > 1) 3494 firstlen = fraglen + overlen; 3495 else 3496 firstlen = paylen + overlen; 3497 3498 if (debug) { 3499 printf("%s: npkt %d firstlen %d lastlen0 %d lastlen %d " 3500 "fraglen %d overlen %d len %d rate %d flags %08x\n", 3501 __func__, npkt, firstlen, lastlen0, lastlen, fraglen, 3502 overlen, len, rate, flags); 3503 } 3504 3505 ack = !IEEE80211_IS_MULTICAST(wh->i_addr1) && 3506 (wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL; 3507 3508 rc = atw_compute_duration1(firstlen + hdrlen, ack, flags, rate, d0); 3509 if (rc == -1) 3510 return rc; 3511 3512 if (npkt <= 1) { 3513 *dn = *d0; 3514 return 0; 3515 } 3516 return atw_compute_duration1(lastlen + hdrlen, ack, flags, rate, dn); 3517 } 3518 3519 #ifdef ATW_DEBUG 3520 void 3521 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0) 3522 { 3523 struct atw_softc *sc = ifp->if_softc; 3524 struct mbuf *m; 3525 int i, noctets = 0; 3526 3527 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname, 3528 m0->m_pkthdr.len); 3529 3530 for (m = m0; m; m = m->m_next) { 3531 if (m->m_len == 0) 3532 continue; 3533 for (i = 0; i < m->m_len; i++) { 3534 printf(" %02x", ((u_int8_t*)m->m_data)[i]); 3535 if (++noctets % 24 == 0) 3536 printf("\n"); 3537 } 3538 } 3539 printf("%s%s: %d bytes emitted\n", 3540 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets); 3541 } 3542 #endif /* ATW_DEBUG */ 3543 3544 /* 3545 * atw_start: [ifnet interface function] 3546 * 3547 * Start packet transmission on the interface. 3548 */ 3549 void 3550 atw_start(struct ifnet *ifp) 3551 { 3552 struct atw_softc *sc = ifp->if_softc; 3553 struct ieee80211com *ic = &sc->sc_ic; 3554 struct ieee80211_node *ni; 3555 struct ieee80211_frame *wh; 3556 struct ieee80211_key *k; 3557 struct atw_frame *hh; 3558 struct mbuf *m0, *m; 3559 struct atw_txsoft *txs, *last_txs; 3560 struct atw_txdesc *txd; 3561 int do_encrypt, npkt, rate; 3562 bus_dmamap_t dmamap; 3563 int ctl, error, firsttx, nexttx, lasttx = -1, first, ofree, seg; 3564 3565 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n", 3566 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags)); 3567 3568 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 3569 return; 3570 3571 /* 3572 * Remember the previous number of free descriptors and 3573 * the first descriptor we'll use. 3574 */ 3575 ofree = sc->sc_txfree; 3576 firsttx = sc->sc_txnext; 3577 3578 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n", 3579 sc->sc_dev.dv_xname, ofree, firsttx)); 3580 3581 /* 3582 * Loop through the send queue, setting up transmit descriptors 3583 * until we drain the queue, or use up all available transmit 3584 * descriptors. 3585 */ 3586 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 3587 sc->sc_txfree != 0) { 3588 3589 /* 3590 * Grab a packet off the management queue, if it 3591 * is not empty. Otherwise, from the data queue. 3592 */ 3593 m0 = mq_dequeue(&ic->ic_mgtq); 3594 if (m0 != NULL) { 3595 ni = m0->m_pkthdr.ph_cookie; 3596 } else { 3597 /* send no data packets until we are associated */ 3598 if (ic->ic_state != IEEE80211_S_RUN) 3599 break; 3600 m0 = ifq_dequeue(&ifp->if_snd); 3601 if (m0 == NULL) 3602 break; 3603 #if NBPFILTER > 0 3604 if (ifp->if_bpf != NULL) 3605 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT); 3606 #endif /* NBPFILTER > 0 */ 3607 if ((m0 = ieee80211_encap(ifp, m0, &ni)) == NULL) { 3608 ifp->if_oerrors++; 3609 break; 3610 } 3611 3612 if (ic->ic_flags & IEEE80211_F_WEPON) { 3613 wh = mtod(m0, struct ieee80211_frame *); 3614 k = ieee80211_get_txkey(ic, wh, ni); 3615 m0 = ieee80211_encrypt(ic, m0, k); 3616 if (m0 == NULL) { 3617 ifp->if_oerrors++; 3618 break; 3619 } 3620 } 3621 } 3622 3623 wh = mtod(m0, struct ieee80211_frame *); 3624 3625 /* XXX do real rate control */ 3626 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 3627 IEEE80211_FC0_TYPE_MGT) 3628 rate = 2; 3629 else 3630 rate = MAX(2, ieee80211_get_rate(ic)); 3631 3632 if (atw_compute_duration(wh, m0->m_pkthdr.len, 3633 ic->ic_flags & ~IEEE80211_F_WEPON, ic->ic_fragthreshold, 3634 rate, &txs->txs_d0, &txs->txs_dn, &npkt, 3635 (sc->sc_if.if_flags & (IFF_DEBUG|IFF_LINK2)) == 3636 (IFF_DEBUG|IFF_LINK2)) == -1) { 3637 DPRINTF2(sc, ("%s: fail compute duration\n", __func__)); 3638 m_freem(m0); 3639 break; 3640 } 3641 3642 /* 3643 * XXX Misleading if fragmentation is enabled. Better 3644 * to fragment in software? 3645 */ 3646 *(uint16_t *)wh->i_dur = htole16(txs->txs_d0.d_rts_dur); 3647 3648 #if NBPFILTER > 0 3649 /* 3650 * Pass the packet to any BPF listeners. 3651 */ 3652 if (ic->ic_rawbpf != NULL) 3653 bpf_mtap(ic->ic_rawbpf, m0, BPF_DIRECTION_OUT); 3654 3655 if (sc->sc_radiobpf != NULL) { 3656 struct mbuf mb; 3657 struct atw_tx_radiotap_header *tap = &sc->sc_txtap; 3658 3659 tap->at_rate = rate; 3660 tap->at_chan_freq = ic->ic_bss->ni_chan->ic_freq; 3661 tap->at_chan_flags = ic->ic_bss->ni_chan->ic_flags; 3662 3663 /* TBD tap->at_flags */ 3664 3665 mb.m_data = (caddr_t)tap; 3666 mb.m_len = tap->at_ihdr.it_len; 3667 mb.m_next = m0; 3668 mb.m_nextpkt = NULL; 3669 mb.m_type = 0; 3670 mb.m_flags = 0; 3671 bpf_mtap(sc->sc_radiobpf, &mb, BPF_DIRECTION_OUT); 3672 } 3673 #endif /* NBPFILTER > 0 */ 3674 3675 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT); 3676 3677 if (ni != NULL) 3678 ieee80211_release_node(ic, ni); 3679 3680 if (m0 == NULL) { 3681 ifp->if_oerrors++; 3682 break; 3683 } 3684 3685 /* just to make sure. */ 3686 m0 = m_pullup(m0, sizeof(struct atw_frame)); 3687 3688 if (m0 == NULL) { 3689 ifp->if_oerrors++; 3690 break; 3691 } 3692 3693 hh = mtod(m0, struct atw_frame *); 3694 wh = &hh->atw_ihdr; 3695 3696 do_encrypt = ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0) ? 1 : 0; 3697 3698 /* Copy everything we need from the 802.11 header: 3699 * Frame Control; address 1, address 3, or addresses 3700 * 3 and 4. NIC fills in BSSID, SA. 3701 */ 3702 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) { 3703 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS) 3704 panic("%s: illegal WDS frame", 3705 sc->sc_dev.dv_xname); 3706 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN); 3707 } else 3708 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN); 3709 3710 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc; 3711 3712 /* initialize remaining Tx parameters */ 3713 memset(&hh->u, 0, sizeof(hh->u)); 3714 3715 hh->atw_rate = rate * 5; 3716 /* XXX this could be incorrect if M_FCS. _encap should 3717 * probably strip FCS just in case it sticks around in 3718 * bridged packets. 3719 */ 3720 hh->atw_service = IEEE80211_PLCP_SERVICE; /* XXX guess */ 3721 hh->atw_paylen = htole16(m0->m_pkthdr.len - 3722 sizeof(struct atw_frame)); 3723 3724 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3725 hh->atw_rtylmt = 3; 3726 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1); 3727 #if 0 3728 if (do_encrypt) { 3729 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP); 3730 hh->atw_keyid = ic->ic_wep_txkey; 3731 } 3732 #endif 3733 3734 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len); 3735 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len); 3736 if (txs->txs_d0.d_residue) 3737 hh->atw_head_plcplen |= htole16(0x8000); 3738 if (txs->txs_dn.d_residue) 3739 hh->atw_tail_plcplen |= htole16(0x8000); 3740 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur); 3741 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur); 3742 3743 /* never fragment multicast frames */ 3744 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) { 3745 hh->atw_fragthr = htole16(ATW_FRAGTHR_FRAGTHR_MASK); 3746 } else if (sc->sc_flags & ATWF_RTSCTS) { 3747 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS); 3748 } 3749 3750 #ifdef ATW_DEBUG 3751 hh->atw_fragnum = 0; 3752 3753 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3754 printf("%s: dst = %s, rate = 0x%02x, " 3755 "service = 0x%02x, paylen = 0x%04x\n", 3756 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst), 3757 hh->atw_rate, hh->atw_service, hh->atw_paylen); 3758 3759 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, " 3760 "dur1 = 0x%04x, dur2 = 0x%04x, " 3761 "dur3 = 0x%04x, rts_dur = 0x%04x\n", 3762 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1], 3763 hh->atw_tail_plcplen, hh->atw_head_plcplen, 3764 hh->atw_tail_dur, hh->atw_head_dur); 3765 3766 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, " 3767 "fragnum = 0x%02x, rtylmt = 0x%04x\n", 3768 sc->sc_dev.dv_xname, hh->atw_hdrctl, 3769 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt); 3770 3771 printf("%s: keyid = %d\n", 3772 sc->sc_dev.dv_xname, hh->atw_keyid); 3773 3774 atw_dump_pkt(ifp, m0); 3775 } 3776 #endif /* ATW_DEBUG */ 3777 3778 dmamap = txs->txs_dmamap; 3779 3780 /* 3781 * Load the DMA map. Copy and try (once) again if the packet 3782 * didn't fit in the allotted number of segments. 3783 */ 3784 for (first = 1; 3785 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 3786 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first; 3787 first = 0) { 3788 MGETHDR(m, M_DONTWAIT, MT_DATA); 3789 if (m == NULL) { 3790 printf("%s: unable to allocate Tx mbuf\n", 3791 sc->sc_dev.dv_xname); 3792 break; 3793 } 3794 if (m0->m_pkthdr.len > MHLEN) { 3795 MCLGET(m, M_DONTWAIT); 3796 if ((m->m_flags & M_EXT) == 0) { 3797 printf("%s: unable to allocate Tx " 3798 "cluster\n", sc->sc_dev.dv_xname); 3799 m_freem(m); 3800 break; 3801 } 3802 } 3803 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 3804 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 3805 m_freem(m0); 3806 m0 = m; 3807 m = NULL; 3808 } 3809 if (error != 0) { 3810 printf("%s: unable to load Tx buffer, " 3811 "error = %d\n", sc->sc_dev.dv_xname, error); 3812 m_freem(m0); 3813 break; 3814 } 3815 3816 /* 3817 * Ensure we have enough descriptors free to describe 3818 * the packet. 3819 */ 3820 if (dmamap->dm_nsegs > sc->sc_txfree) { 3821 /* 3822 * Not enough free descriptors to transmit 3823 * this packet. Unload the DMA map and 3824 * drop the packet. Notify the upper layer 3825 * that there are no more slots left. 3826 * 3827 * XXX We could allocate an mbuf and copy, but 3828 * XXX it is worth it? 3829 */ 3830 ifq_set_oactive(&ifp->if_snd); 3831 bus_dmamap_unload(sc->sc_dmat, dmamap); 3832 m_freem(m0); 3833 break; 3834 } 3835 3836 /* 3837 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 3838 */ 3839 3840 /* Sync the DMA map. */ 3841 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 3842 BUS_DMASYNC_PREWRITE); 3843 3844 /* XXX arbitrary retry limit; 8 because I have seen it in 3845 * use already and maybe 0 means "no tries" ! 3846 */ 3847 ctl = htole32(LSHIFT(8, ATW_TXCTL_TL_MASK)); 3848 3849 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n", 3850 sc->sc_dev.dv_xname, rate * 5)); 3851 ctl |= htole32(LSHIFT(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK)); 3852 3853 /* 3854 * Initialize the transmit descriptors. 3855 */ 3856 for (nexttx = sc->sc_txnext, seg = 0; 3857 seg < dmamap->dm_nsegs; 3858 seg++, nexttx = ATW_NEXTTX(nexttx)) { 3859 /* 3860 * If this is the first descriptor we're 3861 * enqueueing, don't set the OWN bit just 3862 * yet. That could cause a race condition. 3863 * We'll do it below. 3864 */ 3865 txd = &sc->sc_txdescs[nexttx]; 3866 txd->at_ctl = ctl | 3867 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN)); 3868 3869 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr); 3870 txd->at_flags = 3871 htole32(LSHIFT(dmamap->dm_segs[seg].ds_len, 3872 ATW_TXFLAG_TBS1_MASK)) | 3873 ((nexttx == (ATW_NTXDESC - 1)) 3874 ? htole32(ATW_TXFLAG_TER) : 0); 3875 lasttx = nexttx; 3876 } 3877 3878 if (lasttx == -1) 3879 panic("%s: bad lastx", ifp->if_xname); 3880 /* Set `first segment' and `last segment' appropriately. */ 3881 sc->sc_txdescs[sc->sc_txnext].at_flags |= 3882 htole32(ATW_TXFLAG_FS); 3883 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS); 3884 3885 #ifdef ATW_DEBUG 3886 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) { 3887 printf(" txsoft %p transmit chain:\n", txs); 3888 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) { 3889 printf(" descriptor %d:\n", seg); 3890 printf(" at_ctl: 0x%08x\n", 3891 letoh32(sc->sc_txdescs[seg].at_ctl)); 3892 printf(" at_flags: 0x%08x\n", 3893 letoh32(sc->sc_txdescs[seg].at_flags)); 3894 printf(" at_buf1: 0x%08x\n", 3895 letoh32(sc->sc_txdescs[seg].at_buf1)); 3896 printf(" at_buf2: 0x%08x\n", 3897 letoh32(sc->sc_txdescs[seg].at_buf2)); 3898 if (seg == lasttx) 3899 break; 3900 } 3901 } 3902 #endif 3903 3904 /* Sync the descriptors we're using. */ 3905 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 3906 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3907 3908 /* 3909 * Store a pointer to the packet so we can free it later, 3910 * and remember what txdirty will be once the packet is 3911 * done. 3912 */ 3913 txs->txs_mbuf = m0; 3914 txs->txs_firstdesc = sc->sc_txnext; 3915 txs->txs_lastdesc = lasttx; 3916 txs->txs_ndescs = dmamap->dm_nsegs; 3917 3918 /* Advance the tx pointer. */ 3919 sc->sc_txfree -= dmamap->dm_nsegs; 3920 sc->sc_txnext = nexttx; 3921 3922 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 3923 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 3924 3925 last_txs = txs; 3926 } 3927 3928 if (txs == NULL || sc->sc_txfree == 0) { 3929 /* No more slots left; notify upper layer. */ 3930 ifq_set_oactive(&ifp->if_snd); 3931 } 3932 3933 if (sc->sc_txfree != ofree) { 3934 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 3935 sc->sc_dev.dv_xname, lasttx, firsttx)); 3936 /* 3937 * Cause a transmit interrupt to happen on the 3938 * last packet we enqueued. 3939 */ 3940 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC); 3941 ATW_CDTXSYNC(sc, lasttx, 1, 3942 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3943 3944 /* 3945 * The entire packet chain is set up. Give the 3946 * first descriptor to the chip now. 3947 */ 3948 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN); 3949 ATW_CDTXSYNC(sc, firsttx, 1, 3950 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3951 3952 /* Wake up the transmitter. */ 3953 ATW_WRITE(sc, ATW_TDR, 0x1); 3954 3955 /* Set a watchdog timer in case the chip flakes out. */ 3956 sc->sc_tx_timer = 5; 3957 ifp->if_timer = 1; 3958 } 3959 } 3960 3961 int 3962 atw_activate(struct device *self, int act) 3963 { 3964 struct atw_softc *sc = (struct atw_softc *)self; 3965 struct ifnet *ifp = &sc->sc_ic.ic_if; 3966 3967 switch (act) { 3968 case DVACT_SUSPEND: 3969 if (ifp->if_flags & IFF_RUNNING) 3970 atw_stop(ifp, 1); 3971 if (sc->sc_power != NULL) 3972 (*sc->sc_power)(sc, act); 3973 break; 3974 case DVACT_WAKEUP: 3975 atw_wakeup(sc); 3976 break; 3977 } 3978 return 0; 3979 } 3980 3981 void 3982 atw_wakeup(struct atw_softc *sc) 3983 { 3984 struct ifnet *ifp = &sc->sc_ic.ic_if; 3985 3986 if (sc->sc_power != NULL) 3987 (*sc->sc_power)(sc, DVACT_RESUME); 3988 if (ifp->if_flags & IFF_UP) 3989 atw_init(ifp); 3990 } 3991 3992 /* 3993 * atw_ioctl: [ifnet interface function] 3994 * 3995 * Handle control requests from the operator. 3996 */ 3997 int 3998 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3999 { 4000 struct atw_softc *sc = ifp->if_softc; 4001 struct ifreq *ifr = (struct ifreq *)data; 4002 int s, error = 0; 4003 4004 /* XXX monkey see, monkey do. comes from wi_ioctl. */ 4005 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 4006 return ENXIO; 4007 4008 s = splnet(); 4009 4010 switch (cmd) { 4011 case SIOCSIFADDR: 4012 ifp->if_flags |= IFF_UP; 4013 /* FALLTHROUGH */ 4014 4015 case SIOCSIFFLAGS: 4016 if (ifp->if_flags & IFF_UP) { 4017 if (ATW_IS_ENABLED(sc)) { 4018 /* 4019 * To avoid rescanning another access point, 4020 * do not call atw_init() here. Instead, 4021 * only reflect media settings. 4022 */ 4023 atw_filter_setup(sc); 4024 } else 4025 error = atw_init(ifp); 4026 } else if (ATW_IS_ENABLED(sc)) 4027 atw_stop(ifp, 1); 4028 break; 4029 4030 case SIOCADDMULTI: 4031 case SIOCDELMULTI: 4032 error = (cmd == SIOCADDMULTI) ? 4033 ether_addmulti(ifr, &sc->sc_ic.ic_ac) : 4034 ether_delmulti(ifr, &sc->sc_ic.ic_ac); 4035 4036 if (error == ENETRESET) { 4037 if (ifp->if_flags & IFF_RUNNING) 4038 atw_filter_setup(sc); /* do not rescan */ 4039 error = 0; 4040 } 4041 break; 4042 4043 default: 4044 error = ieee80211_ioctl(ifp, cmd, data); 4045 if (error == ENETRESET) { 4046 if (ATW_IS_ENABLED(sc)) 4047 error = atw_init(ifp); 4048 else 4049 error = 0; 4050 } 4051 break; 4052 } 4053 4054 /* Try to get more packets going. */ 4055 if (ATW_IS_ENABLED(sc)) 4056 atw_start(ifp); 4057 4058 splx(s); 4059 return (error); 4060 } 4061 4062 int 4063 atw_media_change(struct ifnet *ifp) 4064 { 4065 int error; 4066 4067 error = ieee80211_media_change(ifp); 4068 if (error == ENETRESET) { 4069 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == 4070 (IFF_RUNNING|IFF_UP)) 4071 atw_init(ifp); /* XXX lose error */ 4072 error = 0; 4073 } 4074 return error; 4075 } 4076 4077 void 4078 atw_media_status(struct ifnet *ifp, struct ifmediareq *imr) 4079 { 4080 struct atw_softc *sc = ifp->if_softc; 4081 4082 if (ATW_IS_ENABLED(sc) == 0) { 4083 imr->ifm_active = IFM_IEEE80211 | IFM_NONE; 4084 imr->ifm_status = 0; 4085 return; 4086 } 4087 ieee80211_media_status(ifp, imr); 4088 } 4089