1 /* $OpenBSD: rtwn.c,v 1.59 2024/09/20 02:00:46 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2016 Nathanial Sloss <nathanialsloss@yahoo.com.au> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for Realtek 802.11b/g/n chipsets. 23 */ 24 25 #include "bpfilter.h" 26 27 #include <sys/param.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/task.h> 34 #include <sys/timeout.h> 35 #include <sys/conf.h> 36 #include <sys/device.h> 37 #include <sys/endian.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #if NBPFILTER > 0 43 #include <net/bpf.h> 44 #endif 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_media.h> 48 49 #include <netinet/in.h> 50 #include <netinet/if_ether.h> 51 52 #include <net80211/ieee80211_var.h> 53 #include <net80211/ieee80211_radiotap.h> 54 55 #include <dev/ic/r92creg.h> 56 #include <dev/ic/rtwnvar.h> 57 58 #define RTWN_RIDX_CCK1 0 59 #define RTWN_RIDX_CCK2 1 60 #define RTWN_RIDX_CCK11 3 61 #define RTWN_RIDX_OFDM6 4 62 #define RTWN_RIDX_OFDM54 11 63 #define RTWN_RIDX_MCS0 12 64 #define RTWN_RIDX_MCS8 (RTWN_RIDX_MCS0 + 8) 65 #define RTWN_RIDX_MCS15 27 66 #define RTWN_RIDX_MAX 27 67 68 #define RTWN_POWER_CCK1 0 69 #define RTWN_POWER_CCK2 1 70 #define RTWN_POWER_CCK55 2 71 #define RTWN_POWER_CCK11 3 72 #define RTWN_POWER_OFDM6 4 73 #define RTWN_POWER_OFDM9 5 74 #define RTWN_POWER_OFDM12 6 75 #define RTWN_POWER_OFDM18 7 76 #define RTWN_POWER_OFDM24 8 77 #define RTWN_POWER_OFDM36 9 78 #define RTWN_POWER_OFDM48 10 79 #define RTWN_POWER_OFDM54 11 80 #define RTWN_POWER_MCS(mcs) (12 + (mcs)) 81 #define RTWN_POWER_COUNT 28 82 83 84 #ifdef RTWN_DEBUG 85 #define DPRINTF(x) do { if (rtwn_debug) printf x; } while (0) 86 #define DPRINTFN(n, x) do { if (rtwn_debug >= (n)) printf x; } while (0) 87 int rtwn_debug = 0; 88 #else 89 #define DPRINTF(x) 90 #define DPRINTFN(n, x) 91 #endif 92 93 /* Registers to save and restore during IQ calibration. */ 94 struct rtwn_iq_cal_regs { 95 uint32_t adda[16]; 96 uint8_t txpause; 97 uint8_t bcn_ctrl; 98 uint8_t bcn_ctrl1; 99 uint32_t gpio_muxcfg; 100 uint32_t ofdm0_trxpathena; 101 uint32_t ofdm0_trmuxpar; 102 uint32_t fpga0_rfifacesw0; 103 uint32_t fpga0_rfifacesw1; 104 uint32_t fpga0_rfifaceoe0; 105 uint32_t fpga0_rfifaceoe1; 106 uint32_t config_ant_a; 107 uint32_t config_ant_b; 108 uint32_t cck0_afesetting; 109 }; 110 111 void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 112 void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 113 void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 114 uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 115 uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 116 uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 117 int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 118 void rtwn_rf_write(struct rtwn_softc *, int, uint16_t, uint32_t); 119 uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 120 void rtwn_cam_write(struct rtwn_softc *, uint32_t, uint32_t); 121 uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 122 void rtwn_efuse_read(struct rtwn_softc *, uint8_t *, size_t); 123 void rtwn_efuse_switch_power(struct rtwn_softc *); 124 int rtwn_read_chipid(struct rtwn_softc *); 125 void rtwn_read_rom(struct rtwn_softc *); 126 void rtwn_r92c_read_rom(struct rtwn_softc *); 127 void rtwn_r92e_read_rom(struct rtwn_softc *); 128 void rtwn_r88e_read_rom(struct rtwn_softc *); 129 void rtwn_r88f_read_rom(struct rtwn_softc *); 130 void rtwn_r23a_read_rom(struct rtwn_softc *); 131 int rtwn_media_change(struct ifnet *); 132 int rtwn_ra_init(struct rtwn_softc *); 133 int rtwn_r92c_ra_init(struct rtwn_softc *, u_int8_t, u_int32_t, 134 int, uint32_t, int); 135 int rtwn_r88e_ra_init(struct rtwn_softc *, u_int8_t, u_int32_t, 136 int, uint32_t, int); 137 void rtwn_tsf_sync_enable(struct rtwn_softc *); 138 void rtwn_set_led(struct rtwn_softc *, int, int); 139 void rtwn_set_nettype(struct rtwn_softc *, enum ieee80211_opmode); 140 void rtwn_update_short_preamble(struct ieee80211com *); 141 void rtwn_r92c_update_short_preamble(struct rtwn_softc *); 142 void rtwn_r88e_update_short_preamble(struct rtwn_softc *); 143 int8_t rtwn_r88e_get_rssi(struct rtwn_softc *, int, void *); 144 int8_t rtwn_r88f_get_rssi(struct rtwn_softc *, int, void *); 145 void rtwn_watchdog(struct ifnet *); 146 void rtwn_fw_reset(struct rtwn_softc *); 147 void rtwn_r92c_fw_reset(struct rtwn_softc *); 148 void rtwn_r88e_fw_reset(struct rtwn_softc *); 149 int rtwn_load_firmware(struct rtwn_softc *); 150 void rtwn_rf_init(struct rtwn_softc *); 151 void rtwn_cam_init(struct rtwn_softc *); 152 void rtwn_pa_bias_init(struct rtwn_softc *); 153 void rtwn_rxfilter_init(struct rtwn_softc *); 154 void rtwn_edca_init(struct rtwn_softc *); 155 void rtwn_rate_fallback_init(struct rtwn_softc *); 156 void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t *); 157 void rtwn_get_txpower(struct rtwn_softc *sc, int, 158 struct ieee80211_channel *, struct ieee80211_channel *, 159 uint16_t *); 160 void rtwn_r92c_get_txpower(struct rtwn_softc *, int, 161 struct ieee80211_channel *, struct ieee80211_channel *, 162 uint16_t *); 163 void rtwn_r92e_get_txpower(struct rtwn_softc *, int, 164 struct ieee80211_channel *, 165 struct ieee80211_channel *, uint16_t *); 166 void rtwn_r88e_get_txpower(struct rtwn_softc *, int, 167 struct ieee80211_channel *, 168 struct ieee80211_channel *, uint16_t *); 169 void rtwn_set_txpower(struct rtwn_softc *, 170 struct ieee80211_channel *, struct ieee80211_channel *); 171 void rtwn_set_chan(struct rtwn_softc *, 172 struct ieee80211_channel *, struct ieee80211_channel *); 173 int rtwn_chan2group(int); 174 int rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2], 175 uint16_t[2]); 176 void rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2], 177 uint16_t rx[2][2], struct rtwn_iq_cal_regs *); 178 int rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2], 179 uint16_t[2][2], uint16_t[2][2], int); 180 void rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2], 181 uint16_t[2], int); 182 void rtwn_iq_calib(struct rtwn_softc *); 183 void rtwn_lc_calib(struct rtwn_softc *); 184 void rtwn_temp_calib(struct rtwn_softc *); 185 void rtwn_enable_intr(struct rtwn_softc *); 186 void rtwn_disable_intr(struct rtwn_softc *); 187 int rtwn_init(struct ifnet *); 188 void rtwn_init_task(void *); 189 void rtwn_stop(struct ifnet *); 190 191 /* Aliases. */ 192 #define rtwn_bb_write rtwn_write_4 193 #define rtwn_bb_read rtwn_read_4 194 195 /* 196 * Macro to convert 4-bit signed integer to 8-bit signed integer. 197 */ 198 #define RTWN_SIGN4TO8(val) (((val) & 0x08) ? (val) | 0xf0 : (val)) 199 200 int 201 rtwn_attach(struct device *pdev, struct rtwn_softc *sc) 202 { 203 struct ieee80211com *ic = &sc->sc_ic; 204 struct ifnet *ifp = &ic->ic_if; 205 int i, error; 206 207 sc->sc_pdev = pdev; 208 209 task_set(&sc->init_task, rtwn_init_task, sc); 210 211 error = rtwn_read_chipid(sc); 212 if (error != 0) { 213 printf("%s: unsupported chip\n", sc->sc_pdev->dv_xname); 214 return (ENXIO); 215 } 216 217 /* Determine number of Tx/Rx chains. */ 218 if (sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_92E)) { 219 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 220 sc->nrxchains = 2; 221 } else { 222 sc->ntxchains = 1; 223 sc->nrxchains = 1; 224 } 225 226 rtwn_read_rom(sc); 227 228 if (sc->chip & RTWN_CHIP_PCI) { 229 printf("%s: MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 230 sc->sc_pdev->dv_xname, 231 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : 232 (sc->chip & RTWN_CHIP_88E) ? "8188EE" : 233 (sc->chip & RTWN_CHIP_92E) ? "8192EE" : 234 (sc->chip & RTWN_CHIP_23A) ? "8723AE" : 235 (sc->chip & RTWN_CHIP_23B) ? "8723BE" : "8188CE", 236 sc->ntxchains, sc->nrxchains, 237 ether_sprintf(ic->ic_myaddr)); 238 } else if (sc->chip & RTWN_CHIP_USB) { 239 printf("%s: MAC/BB RTL%s, RF 6052 %dT%dR, address %s\n", 240 sc->sc_pdev->dv_xname, 241 (sc->chip & RTWN_CHIP_92C) ? "8192CU" : 242 (sc->chip & RTWN_CHIP_92E) ? "8192EU" : 243 (sc->chip & RTWN_CHIP_88E) ? "8188EU" : 244 (sc->chip & RTWN_CHIP_88F) ? "8188FTV" : 245 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 246 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? 247 "8188CE-VAU" : "8188CUS", 248 sc->ntxchains, sc->nrxchains, 249 ether_sprintf(ic->ic_myaddr)); 250 } else { 251 printf("%s: unsupported chip\n", sc->sc_pdev->dv_xname); 252 return (ENXIO); 253 } 254 255 ic->ic_phytype = IEEE80211_T_OFDM; /* Not only, but not used. */ 256 ic->ic_opmode = IEEE80211_M_STA; /* Default to BSS mode. */ 257 ic->ic_state = IEEE80211_S_INIT; 258 259 /* Set device capabilities. */ 260 ic->ic_caps = 261 IEEE80211_C_MONITOR | /* Monitor mode supported. */ 262 IEEE80211_C_SHPREAMBLE | /* Short preamble supported. */ 263 IEEE80211_C_SHSLOT | /* Short slot time supported. */ 264 IEEE80211_C_WEP | /* WEP. */ 265 IEEE80211_C_RSN; /* WPA/RSN. */ 266 267 /* Set HT capabilities. */ 268 ic->ic_htcaps = 269 IEEE80211_HTCAP_CBW20_40 | 270 IEEE80211_HTCAP_DSSSCCK40; 271 /* Set supported HT rates. */ 272 for (i = 0; i < sc->nrxchains; i++) 273 ic->ic_sup_mcs[i] = 0xff; 274 275 /* Set supported .11b and .11g rates. */ 276 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b; 277 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g; 278 279 /* Set supported .11b and .11g channels (1 through 14). */ 280 for (i = 1; i <= 14; i++) { 281 ic->ic_channels[i].ic_freq = 282 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 283 ic->ic_channels[i].ic_flags = 284 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 285 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 286 } 287 288 #ifdef notyet 289 /* 290 * The number of STAs that we can support is limited by the number 291 * of CAM entries used for hardware crypto. 292 */ 293 ic->ic_max_nnodes = R92C_CAM_ENTRY_COUNT - 4; 294 if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE) 295 ic->ic_max_nnodes = IEEE80211_CACHE_SIZE; 296 #endif 297 298 ifp->if_softc = sc; 299 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 300 ifp->if_ioctl = rtwn_ioctl; 301 ifp->if_start = rtwn_start; 302 ifp->if_watchdog = rtwn_watchdog; 303 memcpy(ifp->if_xname, sc->sc_pdev->dv_xname, IFNAMSIZ); 304 305 if_attach(ifp); 306 ieee80211_ifattach(ifp); 307 ic->ic_updateslot = rtwn_updateslot; 308 ic->ic_updateedca = rtwn_updateedca; 309 #ifdef notyet 310 ic->ic_set_key = rtwn_set_key; 311 ic->ic_delete_key = rtwn_delete_key; 312 #endif 313 /* Override state transition machine. */ 314 sc->sc_newstate = ic->ic_newstate; 315 ic->ic_newstate = rtwn_newstate; 316 ieee80211_media_init(ifp, rtwn_media_change, ieee80211_media_status); 317 318 return (0); 319 } 320 321 int 322 rtwn_detach(struct rtwn_softc *sc, int flags) 323 { 324 struct ifnet *ifp = &sc->sc_ic.ic_if; 325 int s; 326 327 s = splnet(); 328 329 task_del(systq, &sc->init_task); 330 331 if (ifp->if_softc != NULL) { 332 ieee80211_ifdetach(ifp); 333 if_detach(ifp); 334 } 335 336 splx(s); 337 338 return (0); 339 } 340 341 int 342 rtwn_activate(struct rtwn_softc *sc, int act) 343 { 344 struct ifnet *ifp = &sc->sc_ic.ic_if; 345 346 switch (act) { 347 case DVACT_QUIESCE: /* rtwn_stop() may sleep */ 348 if (ifp->if_flags & IFF_RUNNING) 349 rtwn_stop(ifp); 350 break; 351 case DVACT_WAKEUP: 352 rtwn_init_task(sc); 353 break; 354 } 355 return (0); 356 } 357 358 void 359 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 360 { 361 sc->sc_ops.write_1(sc->sc_ops.cookie, addr, val); 362 } 363 364 void 365 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 366 { 367 sc->sc_ops.write_2(sc->sc_ops.cookie, addr, val); 368 } 369 370 void 371 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 372 { 373 sc->sc_ops.write_4(sc->sc_ops.cookie, addr, val); 374 } 375 376 uint8_t 377 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 378 { 379 return sc->sc_ops.read_1(sc->sc_ops.cookie, addr); 380 } 381 382 uint16_t 383 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 384 { 385 return sc->sc_ops.read_2(sc->sc_ops.cookie, addr); 386 } 387 388 uint32_t 389 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 390 { 391 return sc->sc_ops.read_4(sc->sc_ops.cookie, addr); 392 } 393 394 int 395 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 396 { 397 struct r92c_fw_cmd cmd; 398 int ntries; 399 400 /* Wait for current FW box to be empty. */ 401 for (ntries = 0; ntries < 100; ntries++) { 402 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 403 break; 404 DELAY(10); 405 } 406 if (ntries == 100) { 407 printf("%s: could not send firmware command %d\n", 408 sc->sc_pdev->dv_xname, id); 409 return (ETIMEDOUT); 410 } 411 memset(&cmd, 0, sizeof(cmd)); 412 cmd.id = id; 413 if (len > 3) 414 cmd.id |= R92C_CMD_FLAG_EXT; 415 KASSERT(len <= sizeof(cmd.msg)); 416 memcpy(cmd.msg, buf, len); 417 418 /* Write the first word last since that will trigger the FW. */ 419 if (sc->chip & RTWN_CHIP_92E) 420 rtwn_write_2(sc, R88E_HMEBOX_EXT(sc->fwcur), 421 *((uint8_t *)&cmd + 4)); 422 else 423 rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), 424 *((uint8_t *)&cmd + 4)); 425 rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0)); 426 427 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 428 429 if (sc->chip & RTWN_CHIP_PCI) { 430 /* Give firmware some time for processing. */ 431 DELAY(2000); 432 } 433 434 return (0); 435 } 436 437 void 438 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint16_t addr, uint32_t val) 439 { 440 uint32_t param_addr; 441 442 if (sc->chip & RTWN_CHIP_92E) { 443 rtwn_write_4(sc, R92C_FPGA0_POWER_SAVE, 444 rtwn_read_4(sc, R92C_FPGA0_POWER_SAVE) & ~0x20000); 445 } 446 447 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) 448 param_addr = SM(R88E_LSSI_PARAM_ADDR, addr); 449 else 450 param_addr = SM(R92C_LSSI_PARAM_ADDR, addr); 451 452 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 453 param_addr | SM(R92C_LSSI_PARAM_DATA, val)); 454 455 DELAY(1); 456 457 if (sc->chip & RTWN_CHIP_92E) { 458 rtwn_write_4(sc, R92C_FPGA0_POWER_SAVE, 459 rtwn_read_4(sc, R92C_FPGA0_POWER_SAVE) | 0x20000); 460 } 461 } 462 463 uint32_t 464 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 465 { 466 uint32_t reg[R92C_MAX_CHAINS], val; 467 468 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 469 if (chain != 0) 470 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 471 472 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 473 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 474 DELAY(1000); 475 476 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 477 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 478 R92C_HSSI_PARAM2_READ_EDGE); 479 DELAY(1000); 480 481 if (!(sc->chip & RTWN_CHIP_88E)) { 482 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 483 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 484 DELAY(1000); 485 } 486 487 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 488 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 489 else 490 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 491 return (MS(val, R92C_LSSI_READBACK_DATA)); 492 } 493 494 void 495 rtwn_cam_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 496 { 497 rtwn_write_4(sc, R92C_CAMWRITE, data); 498 rtwn_write_4(sc, R92C_CAMCMD, 499 R92C_CAMCMD_POLLING | R92C_CAMCMD_WRITE | 500 SM(R92C_CAMCMD_ADDR, addr)); 501 } 502 503 uint8_t 504 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 505 { 506 uint32_t reg; 507 int ntries; 508 509 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 510 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 511 reg &= ~R92C_EFUSE_CTRL_VALID; 512 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 513 /* Wait for read operation to complete. */ 514 for (ntries = 0; ntries < 100; ntries++) { 515 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 516 if (reg & R92C_EFUSE_CTRL_VALID) 517 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 518 DELAY(5); 519 } 520 printf("%s: could not read efuse byte at address 0x%x\n", 521 sc->sc_pdev->dv_xname, addr); 522 return (0xff); 523 } 524 525 void 526 rtwn_efuse_read(struct rtwn_softc *sc, uint8_t *rom, size_t size) 527 { 528 uint8_t off, msk, tmp; 529 uint16_t addr = 0; 530 uint32_t reg; 531 int i, len; 532 533 if (!(sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C))) 534 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 535 536 rtwn_efuse_switch_power(sc); 537 538 /* Switch bank to 0 for wifi/bt later use. */ 539 if (sc->chip & RTWN_CHIP_88F) { 540 reg = rtwn_read_4(sc, R92C_EFUSE_TEST); 541 reg = RW(reg, R92C_EFUSE_TEST_SEL, 0); 542 rtwn_write_4(sc, R92C_EFUSE_TEST, reg); 543 } 544 545 memset(rom, 0xff, size); 546 len = (sc->chip & RTWN_CHIP_88E) ? 256 : 512; 547 while (addr < len) { 548 reg = rtwn_efuse_read_1(sc, addr); 549 if (reg == 0xff) 550 break; 551 addr++; 552 553 /* Check for extended header. */ 554 if ((sc->sc_flags & RTWN_FLAG_EXT_HDR) && 555 (reg & 0x1f) == 0x0f) { 556 tmp = (reg & 0xe0) >> 5; 557 reg = rtwn_efuse_read_1(sc, addr); 558 addr++; 559 if ((reg & 0x0f) != 0x0f) 560 off = ((reg & 0xf0) >> 1) | tmp; 561 else 562 continue; 563 } else 564 off = reg >> 4; 565 msk = reg & 0xf; 566 for (i = 0; i < 4; i++) { 567 if (msk & (1 << i)) 568 continue; 569 rom[off * 8 + i * 2 + 0] = rtwn_efuse_read_1(sc, addr); 570 addr++; 571 rom[off * 8 + i * 2 + 1] = rtwn_efuse_read_1(sc, addr); 572 addr++; 573 } 574 } 575 #ifdef RTWN_DEBUG 576 if (rtwn_debug >= 2) { 577 /* Dump ROM content. */ 578 printf("\n"); 579 for (i = 0; i < size; i++) 580 printf("%02x:", rom[i]); 581 printf("\n"); 582 } 583 #endif 584 if (!(sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C))) 585 rtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 586 } 587 588 void 589 rtwn_efuse_switch_power(struct rtwn_softc *sc) 590 { 591 uint16_t reg; 592 593 if (!(sc->chip & (RTWN_CHIP_88F | RTWN_CHIP_92E))) { 594 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 595 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 596 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 597 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 598 } 599 } 600 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 601 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 602 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 603 reg | R92C_SYS_FUNC_EN_ELDR); 604 } 605 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 606 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 607 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 608 rtwn_write_2(sc, R92C_SYS_CLKR, 609 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 610 } 611 } 612 613 int 614 rtwn_read_chipid(struct rtwn_softc *sc) 615 { 616 uint32_t reg; 617 618 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) { 619 sc->sc_flags |= RTWN_FLAG_EXT_HDR; 620 return (0); 621 } 622 623 reg = rtwn_read_4(sc, R92C_SYS_CFG); 624 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 625 /* Unsupported test chip. */ 626 return (EIO); 627 628 if ((sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) != 0) { 629 if (reg & R92C_SYS_CFG_TYPE_92C) { 630 sc->chip &= ~RTWN_CHIP_88C; 631 /* Check if it is a castrated 8192C. */ 632 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 633 R92C_HPON_FSM_CHIP_BONDING_ID) == 634 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 635 sc->chip |= RTWN_CHIP_92C_1T2R; 636 } else 637 sc->chip &= ~RTWN_CHIP_92C; 638 639 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 640 sc->chip |= RTWN_CHIP_UMC; 641 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 642 sc->chip |= RTWN_CHIP_UMC_A_CUT; 643 } 644 645 return (0); 646 } else if (sc->chip & RTWN_CHIP_23A) { 647 sc->sc_flags |= RTWN_FLAG_EXT_HDR; 648 649 if ((reg & 0xf000) == 0) 650 sc->chip |= RTWN_CHIP_UMC_A_CUT; 651 return (0); 652 } 653 654 return (ENXIO); /* unsupported chip */ 655 } 656 657 void 658 rtwn_read_rom(struct rtwn_softc *sc) 659 { 660 if (sc->chip & RTWN_CHIP_88E) 661 rtwn_r88e_read_rom(sc); 662 else if (sc->chip & RTWN_CHIP_88F) 663 rtwn_r88f_read_rom(sc); 664 else if (sc->chip & RTWN_CHIP_92E) 665 rtwn_r92e_read_rom(sc); 666 else if (sc->chip & RTWN_CHIP_23A) 667 rtwn_r23a_read_rom(sc); 668 else 669 rtwn_r92c_read_rom(sc); 670 } 671 672 void 673 rtwn_r92c_read_rom(struct rtwn_softc *sc) 674 { 675 struct ieee80211com *ic = &sc->sc_ic; 676 struct r92c_rom *rom = &sc->sc_r92c_rom; 677 678 /* Read full ROM image. */ 679 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r92c_rom, 680 sizeof(sc->sc_r92c_rom)); 681 682 /* XXX Weird but this is what the vendor driver does. */ 683 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 684 DPRINTF(("PA setting=0x%x\n", sc->pa_setting)); 685 686 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 687 DPRINTF(("board type=%d\n", sc->board_type)); 688 689 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 690 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 691 692 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 693 } 694 695 void 696 rtwn_r92e_read_rom(struct rtwn_softc *sc) 697 { 698 struct ieee80211com *ic = &sc->sc_ic; 699 struct r92e_rom *rom = &sc->sc_r92e_rom; 700 701 /* Read full ROM image. */ 702 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r92e_rom, 703 sizeof(sc->sc_r92e_rom)); 704 705 sc->crystal_cap = rom->xtal_k; 706 DPRINTF(("crystal cap=0x%x\n", sc->crystal_cap)); 707 708 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 709 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 710 711 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 712 } 713 714 void 715 rtwn_r88e_read_rom(struct rtwn_softc *sc) 716 { 717 struct ieee80211com *ic = &sc->sc_ic; 718 struct r88e_rom *rom = &sc->sc_r88e_rom; 719 720 /* Read full ROM image. */ 721 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r88e_rom, 722 sizeof(sc->sc_r88e_rom)); 723 724 sc->crystal_cap = (sc->chip & RTWN_CHIP_PCI) ? 0x20 : rom->xtal; 725 DPRINTF(("Crystal cap=0x%x\n", sc->crystal_cap)); 726 727 sc->regulatory = MS(rom->rf_board_opt, R92C_ROM_RF1_REGULATORY); 728 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 729 730 if (sc->chip & RTWN_CHIP_PCI) 731 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->r88ee_rom.macaddr); 732 else 733 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->r88eu_rom.macaddr); 734 } 735 736 void 737 rtwn_r88f_read_rom(struct rtwn_softc *sc) 738 { 739 struct ieee80211com *ic = &sc->sc_ic; 740 struct r88f_rom *rom = &sc->sc_r88f_rom; 741 742 /* Read full ROM image. */ 743 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r88f_rom, 744 sizeof(sc->sc_r88f_rom)); 745 746 sc->crystal_cap = rom->xtal; 747 748 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 749 } 750 751 void 752 rtwn_r23a_read_rom(struct rtwn_softc *sc) 753 { 754 struct ieee80211com *ic = &sc->sc_ic; 755 struct r23a_rom *rom = &sc->sc_r23a_rom; 756 757 /* Read full ROM image. */ 758 rtwn_efuse_read(sc, (uint8_t *)&sc->sc_r23a_rom, 759 sizeof(sc->sc_r23a_rom)); 760 761 IEEE80211_ADDR_COPY(ic->ic_myaddr, rom->macaddr); 762 } 763 764 int 765 rtwn_media_change(struct ifnet *ifp) 766 { 767 int error; 768 769 error = ieee80211_media_change(ifp); 770 if (error != ENETRESET) 771 return (error); 772 773 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 774 (IFF_UP | IFF_RUNNING)) { 775 rtwn_stop(ifp); 776 error = rtwn_init(ifp); 777 } 778 return (error); 779 } 780 781 /* 782 * Initialize rate adaptation. 783 */ 784 int 785 rtwn_ra_init(struct rtwn_softc *sc) 786 { 787 static const uint8_t map[] = 788 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 789 struct ieee80211com *ic = &sc->sc_ic; 790 struct ieee80211_node *ni = ic->ic_bss; 791 struct ieee80211_rateset *rs = &ni->ni_rates; 792 uint32_t rates, basicrates; 793 uint8_t mode; 794 int maxrate, maxbasicrate, i, j; 795 int error = 0; 796 797 /* Get normal and basic rates mask. */ 798 rates = basicrates = 0; 799 maxrate = maxbasicrate = 0; 800 for (i = 0; i < rs->rs_nrates; i++) { 801 /* Convert 802.11 rate to HW rate index. */ 802 for (j = 0; j < nitems(map); j++) 803 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 804 break; 805 if (j == nitems(map)) /* Unknown rate, skip. */ 806 continue; 807 rates |= 1 << j; 808 if (j > maxrate) 809 maxrate = j; 810 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 811 basicrates |= 1 << j; 812 if (j > maxbasicrate) 813 maxbasicrate = j; 814 } 815 } 816 if (ic->ic_curmode == IEEE80211_MODE_11B) 817 mode = R92C_RAID_11B; 818 else 819 mode = R92C_RAID_11BG; 820 DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 821 mode, rates, basicrates)); 822 823 if (sc->chip & RTWN_CHIP_PCI) { 824 /* Configure Automatic Rate Fallback Register. */ 825 if (ic->ic_curmode == IEEE80211_MODE_11B) { 826 if (rates & 0x0c) 827 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x05); 828 else 829 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x07); 830 } else 831 rtwn_write_4(sc, R92C_ARFR(0), rates & 0x07f5); 832 } 833 834 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) { 835 error = rtwn_r88e_ra_init(sc, mode, rates, maxrate, 836 basicrates, maxbasicrate); 837 /* We use AMRR with this chip. Start with the lowest rate. */ 838 ni->ni_txrate = 0; 839 } else { 840 if (sc->chip & RTWN_CHIP_PCI) { 841 ni->ni_txrate = 0; /* AMRR will raise. */ 842 /* Set initial MRR rates. */ 843 rtwn_write_1(sc, 844 R92C_INIDATA_RATE_SEL(R92C_MACID_BC), maxbasicrate); 845 rtwn_write_1(sc, 846 R92C_INIDATA_RATE_SEL(R92C_MACID_BSS), 0); 847 } else { 848 error = rtwn_r92c_ra_init(sc, mode, rates, maxrate, 849 basicrates, maxbasicrate); 850 /* No AMRR support. Indicate highest supported rate. */ 851 ni->ni_txrate = rs->rs_nrates - 1; 852 } 853 } 854 return (error); 855 } 856 857 /* 858 * Initialize rate adaptation in firmware. 859 */ 860 int 861 rtwn_r92c_ra_init(struct rtwn_softc *sc, u_int8_t mode, u_int32_t rates, 862 int maxrate, uint32_t basicrates, int maxbasicrate) 863 { 864 struct r92c_fw_cmd_macid_cfg cmd; 865 int error; 866 867 /* Set rates mask for group addressed frames. */ 868 cmd.macid = R92C_MACID_BC | R92C_MACID_VALID; 869 cmd.mask = htole32(mode << 28 | basicrates); 870 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 871 if (error != 0) { 872 printf("%s: could not add broadcast station\n", 873 sc->sc_pdev->dv_xname); 874 return (error); 875 } 876 /* Set initial MRR rate. */ 877 DPRINTF(("maxbasicrate=%d\n", maxbasicrate)); 878 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BC), 879 maxbasicrate); 880 881 /* Set rates mask for unicast frames. */ 882 cmd.macid = R92C_MACID_BSS | R92C_MACID_VALID; 883 cmd.mask = htole32(mode << 28 | rates); 884 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 885 if (error != 0) { 886 printf("%s: could not add BSS station\n", 887 sc->sc_pdev->dv_xname); 888 return (error); 889 } 890 /* Set initial MRR rate. */ 891 DPRINTF(("maxrate=%d\n", maxrate)); 892 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(R92C_MACID_BSS), 893 maxrate); 894 895 return (0); 896 } 897 898 int 899 rtwn_r88e_ra_init(struct rtwn_softc *sc, u_int8_t mode, u_int32_t rates, 900 int maxrate, uint32_t basicrates, int maxbasicrate) 901 { 902 u_int32_t reg; 903 904 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, maxbasicrate); 905 906 reg = rtwn_read_4(sc, R92C_RRSR); 907 reg = RW(reg, R92C_RRSR_RATE_BITMAP, rates); 908 rtwn_write_4(sc, R92C_RRSR, reg); 909 910 /* 911 * Workaround for performance problems with firmware rate adaptation: 912 * If the AP only supports 11b rates, disable mixed B/G mode. 913 */ 914 if (mode != R92C_RAID_11B && maxrate <= 3 /* 11M */) 915 sc->sc_flags |= RTWN_FLAG_FORCE_RAID_11B; 916 917 return (0); 918 } 919 920 void 921 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 922 { 923 struct ieee80211_node *ni = sc->sc_ic.ic_bss; 924 uint64_t tsf; 925 926 /* Enable TSF synchronization. */ 927 rtwn_write_1(sc, R92C_BCN_CTRL, 928 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 929 930 rtwn_write_1(sc, R92C_BCN_CTRL, 931 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 932 933 /* Set initial TSF. */ 934 memcpy(&tsf, ni->ni_tstamp, sizeof(tsf)); 935 tsf = letoh64(tsf); 936 tsf = tsf - (tsf % (ni->ni_intval * IEEE80211_DUR_TU)); 937 tsf -= IEEE80211_DUR_TU; 938 rtwn_write_4(sc, R92C_TSFTR + 0, tsf); 939 rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 940 941 rtwn_write_1(sc, R92C_BCN_CTRL, 942 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 943 } 944 945 void 946 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 947 { 948 uint8_t reg; 949 950 if (led != RTWN_LED_LINK) 951 return; /* not supported */ 952 953 if (sc->chip & RTWN_CHIP_PCI) { 954 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 955 if (!on) 956 reg |= R92C_LEDCFG2_DIS; 957 else 958 reg |= R92C_LEDCFG2_EN; 959 rtwn_write_1(sc, R92C_LEDCFG2, reg); 960 } else if (sc->chip & RTWN_CHIP_USB) { 961 if (sc->chip & RTWN_CHIP_92E) { 962 rtwn_write_1(sc, 0x64, rtwn_read_1(sc, 0x64) & 0xfe); 963 reg = rtwn_read_1(sc, R92C_LEDCFG1) & R92E_LEDSON; 964 rtwn_write_1(sc, R92C_LEDCFG1, reg | 965 (R92C_LEDCFG0_DIS << 1)); 966 if (on) { 967 reg = rtwn_read_1(sc, R92C_LEDCFG1) & 968 R92E_LEDSON; 969 rtwn_write_1(sc, R92C_LEDCFG1, reg); 970 } 971 } else if (sc->chip & RTWN_CHIP_88E) { 972 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 973 rtwn_write_1(sc, R92C_LEDCFG2, reg | R92C_LEDCFG2_EN); 974 if (!on) { 975 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 976 rtwn_write_1(sc, R92C_LEDCFG2, 977 reg | R92C_LEDCFG0_DIS); 978 rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 979 rtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 980 0xfe); 981 } 982 } else { 983 reg = rtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 984 if (!on) 985 reg |= R92C_LEDCFG0_DIS; 986 rtwn_write_1(sc, R92C_LEDCFG0, reg); 987 } 988 } 989 sc->ledlink = on; /* Save LED state. */ 990 } 991 992 void 993 rtwn_set_nettype(struct rtwn_softc *sc, enum ieee80211_opmode opmode) 994 { 995 uint8_t msr; 996 997 msr = rtwn_read_1(sc, R92C_MSR) & ~R92C_MSR_NETTYPE_MASK; 998 999 switch (opmode) { 1000 case IEEE80211_M_MONITOR: 1001 msr |= R92C_MSR_NETTYPE_NOLINK; 1002 break; 1003 case IEEE80211_M_STA: 1004 msr |= R92C_MSR_NETTYPE_INFRA; 1005 break; 1006 default: 1007 break; 1008 } 1009 1010 rtwn_write_1(sc, R92C_MSR, msr); 1011 } 1012 1013 void 1014 rtwn_calib(struct rtwn_softc *sc) 1015 { 1016 1017 if (sc->avg_pwdb != -1) { 1018 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1019 1020 /* Indicate Rx signal strength to FW for rate adaptation. */ 1021 if (sc->chip & RTWN_CHIP_92E) { 1022 struct r92e_fw_cmd_rssi cmd; 1023 1024 memset(&cmd, 0, sizeof(cmd)); 1025 cmd.macid = 0; /* BSS. */ 1026 cmd.pwdb = sc->avg_pwdb; 1027 rtwn_fw_cmd(sc, R92E_CMD_RSSI_REPORT, &cmd, 1028 sizeof(cmd)); 1029 } else { 1030 struct r92c_fw_cmd_rssi cmd; 1031 1032 memset(&cmd, 0, sizeof(cmd)); 1033 cmd.macid = 0; /* BSS. */ 1034 cmd.pwdb = sc->avg_pwdb; 1035 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, 1036 sizeof(cmd)); 1037 } 1038 } 1039 1040 /* Do temperature compensation. */ 1041 rtwn_temp_calib(sc); 1042 1043 sc->sc_ops.next_calib(sc->sc_ops.cookie); 1044 } 1045 1046 void 1047 rtwn_next_scan(struct rtwn_softc *sc) 1048 { 1049 struct ieee80211com *ic = &sc->sc_ic; 1050 int s; 1051 1052 s = splnet(); 1053 if (ic->ic_state == IEEE80211_S_SCAN) 1054 ieee80211_next_scan(&ic->ic_if); 1055 splx(s); 1056 } 1057 1058 int 1059 rtwn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 1060 { 1061 struct rtwn_softc *sc = ic->ic_softc; 1062 struct ieee80211_node *ni; 1063 enum ieee80211_state ostate; 1064 uint32_t reg; 1065 int s, error; 1066 1067 s = splnet(); 1068 ostate = ic->ic_state; 1069 1070 if (nstate != ostate) 1071 DPRINTF(("newstate %s -> %s\n", 1072 ieee80211_state_name[ostate], 1073 ieee80211_state_name[nstate])); 1074 1075 if (ostate == IEEE80211_S_RUN) { 1076 /* Stop calibration. */ 1077 sc->sc_ops.cancel_calib(sc->sc_ops.cookie); 1078 1079 /* Turn link LED off. */ 1080 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1081 1082 /* Set media status to 'No Link'. */ 1083 rtwn_set_nettype(sc, IEEE80211_M_MONITOR); 1084 1085 /* Stop Rx of data frames. */ 1086 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1087 1088 /* Rest TSF. */ 1089 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1090 1091 /* Disable TSF synchronization. */ 1092 rtwn_write_1(sc, R92C_BCN_CTRL, 1093 rtwn_read_1(sc, R92C_BCN_CTRL) | 1094 R92C_BCN_CTRL_DIS_TSF_UDT0); 1095 1096 /* Reset EDCA parameters. */ 1097 rtwn_edca_init(sc); 1098 1099 rtwn_updateslot(ic); 1100 rtwn_update_short_preamble(ic); 1101 1102 /* Disable 11b-only AP workaround (see rtwn_r88e_ra_init). */ 1103 sc->sc_flags &= ~RTWN_FLAG_FORCE_RAID_11B; 1104 } 1105 switch (nstate) { 1106 case IEEE80211_S_INIT: 1107 /* Turn link LED off. */ 1108 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1109 break; 1110 case IEEE80211_S_SCAN: 1111 if (ostate != IEEE80211_S_SCAN) { 1112 /* Allow Rx from any BSSID. */ 1113 rtwn_write_4(sc, R92C_RCR, 1114 rtwn_read_4(sc, R92C_RCR) & 1115 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1116 1117 /* Set gain for scanning. */ 1118 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1119 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1120 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1121 1122 if (!(sc->chip & RTWN_CHIP_88E)) { 1123 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1124 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1125 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1126 } 1127 } 1128 1129 /* Make link LED blink during scan. */ 1130 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1131 1132 /* Pause AC Tx queues. */ 1133 rtwn_write_1(sc, R92C_TXPAUSE, 1134 rtwn_read_1(sc, R92C_TXPAUSE) | R92C_TXPAUSE_AC_VO | 1135 R92C_TXPAUSE_AC_VI | R92C_TXPAUSE_AC_BE | 1136 R92C_TXPAUSE_AC_BK); 1137 1138 rtwn_set_chan(sc, ic->ic_bss->ni_chan, NULL); 1139 sc->sc_ops.next_scan(sc->sc_ops.cookie); 1140 break; 1141 1142 case IEEE80211_S_AUTH: 1143 /* Set initial gain under link. */ 1144 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1145 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1146 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1147 1148 if (!(sc->chip & RTWN_CHIP_88E)) { 1149 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1150 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1151 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1152 } 1153 1154 rtwn_set_chan(sc, ic->ic_bss->ni_chan, NULL); 1155 break; 1156 case IEEE80211_S_ASSOC: 1157 break; 1158 case IEEE80211_S_RUN: 1159 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1160 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 1161 1162 /* Enable Rx of data frames. */ 1163 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1164 1165 /* Enable Rx of control frames. */ 1166 rtwn_write_2(sc, R92C_RXFLTMAP1, 0xffff); 1167 1168 rtwn_write_4(sc, R92C_RCR, 1169 rtwn_read_4(sc, R92C_RCR) | 1170 R92C_RCR_AAP | R92C_RCR_ADF | R92C_RCR_ACF | 1171 R92C_RCR_AMF); 1172 1173 /* Turn link LED on. */ 1174 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1175 break; 1176 } 1177 ni = ic->ic_bss; 1178 1179 /* Set media status to 'Associated'. */ 1180 rtwn_set_nettype(sc, IEEE80211_M_STA); 1181 1182 /* Set BSSID. */ 1183 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1184 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1185 1186 if (ic->ic_curmode == IEEE80211_MODE_11B) 1187 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1188 else /* 802.11b/g */ 1189 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1190 1191 rtwn_updateslot(ic); 1192 rtwn_update_short_preamble(ic); 1193 1194 /* Enable Rx of data frames. */ 1195 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1196 1197 /* Flush all AC queues. */ 1198 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 1199 1200 /* Set beacon interval. */ 1201 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1202 1203 /* Allow Rx from our BSSID only. */ 1204 rtwn_write_4(sc, R92C_RCR, 1205 rtwn_read_4(sc, R92C_RCR) | 1206 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1207 1208 /* Enable TSF synchronization. */ 1209 rtwn_tsf_sync_enable(sc); 1210 1211 /* Initialize rate adaptation. */ 1212 rtwn_ra_init(sc); 1213 1214 /* Turn link LED on. */ 1215 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1216 1217 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1218 /* Reset temperature calibration state machine. */ 1219 sc->thcal_state = 0; 1220 sc->thcal_lctemp = 0; 1221 /* Start periodic calibration. */ 1222 sc->sc_ops.next_calib(sc->sc_ops.cookie); 1223 break; 1224 } 1225 1226 error = sc->sc_newstate(ic, nstate, arg); 1227 splx(s); 1228 1229 return (error); 1230 } 1231 1232 void 1233 rtwn_update_short_preamble(struct ieee80211com *ic) 1234 { 1235 struct rtwn_softc *sc = ic->ic_softc; 1236 1237 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 1238 rtwn_r88e_update_short_preamble(sc); 1239 else 1240 rtwn_r92c_update_short_preamble(sc); 1241 } 1242 1243 void 1244 rtwn_r92c_update_short_preamble(struct rtwn_softc *sc) 1245 { 1246 uint32_t reg; 1247 1248 reg = rtwn_read_4(sc, R92C_RRSR); 1249 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1250 reg |= R92C_RRSR_SHORT; 1251 else 1252 reg &= ~R92C_RRSR_SHORT; 1253 rtwn_write_4(sc, R92C_RRSR, reg); 1254 } 1255 1256 void 1257 rtwn_r88e_update_short_preamble(struct rtwn_softc *sc) 1258 { 1259 uint32_t reg; 1260 1261 reg = rtwn_read_4(sc, R92C_WMAC_TRXPTCL_CTL); 1262 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE) 1263 reg |= R92C_WMAC_TRXPTCL_CTL_SHORT; 1264 else 1265 reg &= ~R92C_WMAC_TRXPTCL_CTL_SHORT; 1266 rtwn_write_4(sc, R92C_WMAC_TRXPTCL_CTL, reg); 1267 } 1268 1269 void 1270 rtwn_updateslot(struct ieee80211com *ic) 1271 { 1272 struct rtwn_softc *sc = ic->ic_softc; 1273 int s; 1274 1275 s = splnet(); 1276 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1277 rtwn_write_1(sc, R92C_SLOT, IEEE80211_DUR_DS_SHSLOT); 1278 else 1279 rtwn_write_1(sc, R92C_SLOT, IEEE80211_DUR_DS_SLOT); 1280 splx(s); 1281 } 1282 1283 void 1284 rtwn_updateedca(struct ieee80211com *ic) 1285 { 1286 struct rtwn_softc *sc = ic->ic_softc; 1287 const uint16_t aci2reg[EDCA_NUM_AC] = { 1288 R92C_EDCA_BE_PARAM, 1289 R92C_EDCA_BK_PARAM, 1290 R92C_EDCA_VI_PARAM, 1291 R92C_EDCA_VO_PARAM 1292 }; 1293 struct ieee80211_edca_ac_params *ac; 1294 int s, aci, aifs, slottime; 1295 uint8_t acm = 0; 1296 1297 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1298 slottime = IEEE80211_DUR_DS_SHSLOT; 1299 else 1300 slottime = IEEE80211_DUR_DS_SLOT; 1301 s = splnet(); 1302 for (aci = 0; aci < EDCA_NUM_AC; aci++) { 1303 ac = &ic->ic_edca_ac[aci]; 1304 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1305 aifs = ac->ac_aifsn * slottime + IEEE80211_DUR_DS_SIFS; 1306 rtwn_write_4(sc, aci2reg[aci], 1307 SM(R92C_EDCA_PARAM_TXOP, ac->ac_txoplimit) | 1308 SM(R92C_EDCA_PARAM_ECWMIN, ac->ac_ecwmin) | 1309 SM(R92C_EDCA_PARAM_ECWMAX, ac->ac_ecwmax) | 1310 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1311 1312 /* Is admission control mandatory for this queue? */ 1313 if (ac->ac_acm) { 1314 switch (aci) { 1315 case EDCA_AC_BE: 1316 acm |= R92C_ACMHW_BEQEN; 1317 break; 1318 case EDCA_AC_VI: 1319 acm |= R92C_ACMHW_VIQEN; 1320 break; 1321 case EDCA_AC_VO: 1322 acm |= R92C_ACMHW_VOQEN; 1323 break; 1324 default: 1325 break; 1326 } 1327 } 1328 } 1329 splx(s); 1330 1331 /* Enable hardware admission control. */ 1332 rtwn_write_1(sc, R92C_ACMHWCTRL, R92C_ACMHW_HWEN | acm); 1333 } 1334 1335 int 1336 rtwn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1337 struct ieee80211_key *k) 1338 { 1339 struct rtwn_softc *sc = ic->ic_softc; 1340 static const uint8_t etherzeroaddr[6] = { 0 }; 1341 const uint8_t *macaddr; 1342 uint8_t keybuf[16], algo; 1343 int i, entry; 1344 1345 /* Defer setting of WEP keys until interface is brought up. */ 1346 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 1347 (IFF_UP | IFF_RUNNING)) 1348 return (0); 1349 1350 /* Map net80211 cipher to HW crypto algorithm. */ 1351 switch (k->k_cipher) { 1352 case IEEE80211_CIPHER_WEP40: 1353 algo = R92C_CAM_ALGO_WEP40; 1354 break; 1355 case IEEE80211_CIPHER_WEP104: 1356 algo = R92C_CAM_ALGO_WEP104; 1357 break; 1358 case IEEE80211_CIPHER_TKIP: 1359 algo = R92C_CAM_ALGO_TKIP; 1360 break; 1361 case IEEE80211_CIPHER_CCMP: 1362 algo = R92C_CAM_ALGO_AES; 1363 break; 1364 default: 1365 /* Fallback to software crypto for other ciphers. */ 1366 return (ieee80211_set_key(ic, ni, k)); 1367 } 1368 if (k->k_flags & IEEE80211_KEY_GROUP) { 1369 macaddr = etherzeroaddr; 1370 entry = k->k_id; 1371 } else { 1372 macaddr = ic->ic_bss->ni_macaddr; 1373 entry = 4; 1374 } 1375 /* Write key. */ 1376 memset(keybuf, 0, sizeof(keybuf)); 1377 memcpy(keybuf, k->k_key, MIN(k->k_len, sizeof(keybuf))); 1378 for (i = 0; i < 4; i++) { 1379 rtwn_cam_write(sc, R92C_CAM_KEY(entry, i), 1380 LE_READ_4(&keybuf[i * 4])); 1381 } 1382 /* Write CTL0 last since that will validate the CAM entry. */ 1383 rtwn_cam_write(sc, R92C_CAM_CTL1(entry), 1384 LE_READ_4(&macaddr[2])); 1385 rtwn_cam_write(sc, R92C_CAM_CTL0(entry), 1386 SM(R92C_CAM_ALGO, algo) | 1387 SM(R92C_CAM_KEYID, k->k_id) | 1388 SM(R92C_CAM_MACLO, LE_READ_2(&macaddr[0])) | 1389 R92C_CAM_VALID); 1390 1391 return (0); 1392 } 1393 1394 void 1395 rtwn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 1396 struct ieee80211_key *k) 1397 { 1398 struct rtwn_softc *sc = ic->ic_softc; 1399 int i, entry; 1400 1401 if (!(ic->ic_if.if_flags & IFF_RUNNING) || 1402 ic->ic_state != IEEE80211_S_RUN) 1403 return; /* Nothing to do. */ 1404 1405 if (k->k_flags & IEEE80211_KEY_GROUP) 1406 entry = k->k_id; 1407 else 1408 entry = 4; 1409 rtwn_cam_write(sc, R92C_CAM_CTL0(entry), 0); 1410 rtwn_cam_write(sc, R92C_CAM_CTL1(entry), 0); 1411 /* Clear key. */ 1412 for (i = 0; i < 4; i++) 1413 rtwn_cam_write(sc, R92C_CAM_KEY(entry, i), 0); 1414 } 1415 1416 void 1417 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1418 { 1419 int pwdb; 1420 1421 /* Convert antenna signal to percentage. */ 1422 if (rssi <= -100 || rssi >= 20) 1423 pwdb = 0; 1424 else if (rssi >= 0) 1425 pwdb = 100; 1426 else 1427 pwdb = 100 + rssi; 1428 if (sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C)) { 1429 if (rate <= 3) { 1430 /* CCK gain is smaller than OFDM/MCS gain. */ 1431 pwdb += 6; 1432 if (pwdb > 100) 1433 pwdb = 100; 1434 if (pwdb <= 14) 1435 pwdb -= 4; 1436 else if (pwdb <= 26) 1437 pwdb -= 8; 1438 else if (pwdb <= 34) 1439 pwdb -= 6; 1440 else if (pwdb <= 42) 1441 pwdb -= 2; 1442 } 1443 } 1444 if (sc->avg_pwdb == -1) /* Init. */ 1445 sc->avg_pwdb = pwdb; 1446 else if (sc->avg_pwdb < pwdb) 1447 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1448 else 1449 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1450 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1451 } 1452 1453 int8_t 1454 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1455 { 1456 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1457 struct r92c_rx_phystat *phy; 1458 struct r92c_rx_cck *cck; 1459 uint8_t rpt; 1460 int8_t rssi; 1461 1462 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 1463 return rtwn_r88e_get_rssi(sc, rate, physt); 1464 else if (sc->chip & RTWN_CHIP_88E) 1465 return rtwn_r88f_get_rssi(sc, rate, physt); 1466 1467 if (rate <= 3) { 1468 cck = (struct r92c_rx_cck *)physt; 1469 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1470 rpt = (cck->agc_rpt >> 5) & 0x3; 1471 rssi = (cck->agc_rpt & 0x1f) << 1; 1472 } else { 1473 rpt = (cck->agc_rpt >> 6) & 0x3; 1474 rssi = cck->agc_rpt & 0x3e; 1475 } 1476 rssi = cckoff[rpt] - rssi; 1477 } else { /* OFDM/HT. */ 1478 phy = (struct r92c_rx_phystat *)physt; 1479 rssi = ((letoh32(phy->phydw1) >> 1) & 0x7f) - 110; 1480 } 1481 return (rssi); 1482 } 1483 1484 int8_t 1485 rtwn_r88e_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1486 { 1487 static const int8_t cckoff[] = { 20, 14, 10, -4, -16, -22, -38, -40 }; 1488 struct r88e_rx_phystat *phy; 1489 uint8_t rpt; 1490 int8_t rssi; 1491 1492 phy = (struct r88e_rx_phystat *)physt; 1493 1494 if (rate <= 3) { 1495 rpt = (phy->agc_rpt >> 5) & 0x7; 1496 rssi = (phy->agc_rpt & 0x1f) << 1; 1497 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1498 if (rpt == 2) 1499 rssi -= 6; 1500 } 1501 rssi = (phy->agc_rpt & 0x1f) > 27 ? -94 : cckoff[rpt] - rssi; 1502 } else { /* OFDM/HT. */ 1503 rssi = ((le32toh(phy->sq_rpt) >> 1) & 0x7f) - 110; 1504 } 1505 return (rssi); 1506 } 1507 1508 int8_t 1509 rtwn_r88f_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1510 { 1511 struct r88e_rx_phystat *phy; 1512 uint8_t lna_idx, vga_idx; 1513 int8_t rssi; 1514 1515 phy = (struct r88e_rx_phystat *)physt; 1516 lna_idx = (phy->agc_rpt & 0xe0) >> 5; 1517 vga_idx = (phy->agc_rpt & 0x1f); 1518 rssi = -(2 * vga_idx); 1519 1520 if (rate <= 3) { 1521 switch (lna_idx) { 1522 case 7: 1523 if (vga_idx > 27) 1524 rssi = -100; 1525 else 1526 rssi += -46; 1527 break; 1528 case 5: 1529 rssi += -32; 1530 break; 1531 case 3: 1532 rssi += -20; 1533 break; 1534 case 1: 1535 rssi += -6; 1536 break; 1537 default: 1538 rssi = 0; 1539 break; 1540 } 1541 } else { /* OFDM/HT. */ 1542 rssi = ((le32toh(phy->sq_rpt) >> 1) & 0x7f) - 110; 1543 } 1544 return (rssi); 1545 } 1546 1547 void 1548 rtwn_start(struct ifnet *ifp) 1549 { 1550 struct rtwn_softc *sc = ifp->if_softc; 1551 struct ieee80211com *ic = &sc->sc_ic; 1552 struct ieee80211_node *ni; 1553 struct mbuf *m; 1554 1555 if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) 1556 return; 1557 1558 for (;;) { 1559 if (sc->sc_ops.is_oactive(sc->sc_ops.cookie)) { 1560 ifq_set_oactive(&ifp->if_snd); 1561 break; 1562 } 1563 /* Send pending management frames first. */ 1564 m = mq_dequeue(&ic->ic_mgtq); 1565 if (m != NULL) { 1566 ni = m->m_pkthdr.ph_cookie; 1567 goto sendit; 1568 } 1569 if (ic->ic_state != IEEE80211_S_RUN) 1570 break; 1571 1572 /* Encapsulate and send data frames. */ 1573 m = ifq_dequeue(&ifp->if_snd); 1574 if (m == NULL) 1575 break; 1576 #if NBPFILTER > 0 1577 if (ifp->if_bpf != NULL) 1578 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); 1579 #endif 1580 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) 1581 continue; 1582 sendit: 1583 #if NBPFILTER > 0 1584 if (ic->ic_rawbpf != NULL) 1585 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT); 1586 #endif 1587 if (sc->sc_ops.tx(sc->sc_ops.cookie, m, ni) != 0) { 1588 ieee80211_release_node(ic, ni); 1589 ifp->if_oerrors++; 1590 continue; 1591 } 1592 1593 sc->sc_tx_timer = 5; 1594 ifp->if_timer = 1; 1595 } 1596 } 1597 1598 void 1599 rtwn_watchdog(struct ifnet *ifp) 1600 { 1601 struct rtwn_softc *sc = ifp->if_softc; 1602 1603 ifp->if_timer = 0; 1604 1605 if (sc->sc_tx_timer > 0) { 1606 if (--sc->sc_tx_timer == 0) { 1607 printf("%s: device timeout\n", sc->sc_pdev->dv_xname); 1608 task_add(systq, &sc->init_task); 1609 ifp->if_oerrors++; 1610 return; 1611 } 1612 ifp->if_timer = 1; 1613 } 1614 ieee80211_watchdog(ifp); 1615 } 1616 1617 int 1618 rtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1619 { 1620 struct rtwn_softc *sc = ifp->if_softc; 1621 struct ieee80211com *ic = &sc->sc_ic; 1622 int s, error = 0; 1623 1624 s = splnet(); 1625 /* 1626 * Prevent processes from entering this function while another 1627 * process is tsleep'ing in it. 1628 */ 1629 while ((sc->sc_flags & RTWN_FLAG_BUSY) && error == 0) 1630 error = tsleep_nsec(&sc->sc_flags, PCATCH, "rtwnioc", INFSLP); 1631 if (error != 0) { 1632 splx(s); 1633 return error; 1634 } 1635 sc->sc_flags |= RTWN_FLAG_BUSY; 1636 1637 switch (cmd) { 1638 case SIOCSIFADDR: 1639 ifp->if_flags |= IFF_UP; 1640 /* FALLTHROUGH */ 1641 case SIOCSIFFLAGS: 1642 if (ifp->if_flags & IFF_UP) { 1643 if (!(ifp->if_flags & IFF_RUNNING)) 1644 rtwn_init(ifp); 1645 } else { 1646 if (ifp->if_flags & IFF_RUNNING) 1647 rtwn_stop(ifp); 1648 } 1649 break; 1650 case SIOCS80211CHANNEL: 1651 error = ieee80211_ioctl(ifp, cmd, data); 1652 if (error == ENETRESET && 1653 ic->ic_opmode == IEEE80211_M_MONITOR) { 1654 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1655 (IFF_UP | IFF_RUNNING)) 1656 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 1657 error = 0; 1658 } 1659 break; 1660 default: 1661 error = ieee80211_ioctl(ifp, cmd, data); 1662 } 1663 1664 if (error == ENETRESET) { 1665 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == 1666 (IFF_UP | IFF_RUNNING)) { 1667 rtwn_stop(ifp); 1668 rtwn_init(ifp); 1669 } 1670 error = 0; 1671 } 1672 sc->sc_flags &= ~RTWN_FLAG_BUSY; 1673 wakeup(&sc->sc_flags); 1674 splx(s); 1675 1676 return (error); 1677 } 1678 1679 void 1680 rtwn_fw_reset(struct rtwn_softc *sc) 1681 { 1682 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) 1683 rtwn_r88e_fw_reset(sc); 1684 else 1685 rtwn_r92c_fw_reset(sc); 1686 } 1687 1688 void 1689 rtwn_r92c_fw_reset(struct rtwn_softc *sc) 1690 { 1691 uint16_t reg; 1692 int ntries; 1693 1694 /* Tell 8051 to reset itself. */ 1695 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 1696 1697 /* Wait until 8051 resets by itself. */ 1698 for (ntries = 0; ntries < 100; ntries++) { 1699 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1700 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 1701 goto sleep; 1702 DELAY(50); 1703 } 1704 /* Force 8051 reset. */ 1705 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 1706 sleep: 1707 if (sc->chip & RTWN_CHIP_PCI) { 1708 /* 1709 * We must sleep for one second to let the firmware settle. 1710 * Accessing registers too early will hang the whole system. 1711 */ 1712 tsleep_nsec(®, 0, "rtwnrst", SEC_TO_NSEC(1)); 1713 } 1714 } 1715 1716 void 1717 rtwn_r88e_fw_reset(struct rtwn_softc *sc) 1718 { 1719 /* Reset MCU IO wrapper. */ 1720 if (!(sc->chip & RTWN_CHIP_88F)) { 1721 rtwn_write_1(sc, R92C_RSV_CTRL, 1722 rtwn_read_1(sc, R92C_RSV_CTRL) & ~R92C_RSV_CTRL_WLOCK_00); 1723 } 1724 if (sc->chip & RTWN_CHIP_88E) { 1725 rtwn_write_2(sc, R92C_RSV_CTRL, 1726 rtwn_read_2(sc, R92C_RSV_CTRL) & ~R88E_RSV_CTRL_MCU_RST); 1727 } else { 1728 rtwn_write_2(sc, R92C_RSV_CTRL, 1729 rtwn_read_2(sc, R92C_RSV_CTRL) & ~R88E_RSV_CTRL_MIO_EN); 1730 } 1731 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1732 rtwn_read_2(sc, R92C_SYS_FUNC_EN) & ~R92C_SYS_FUNC_EN_CPUEN); 1733 1734 /* Enable MCU IO wrapper. */ 1735 if (!(sc->chip & RTWN_CHIP_88F)) { 1736 rtwn_write_1(sc, R92C_RSV_CTRL, 1737 rtwn_read_1(sc, R92C_RSV_CTRL) & ~R92C_RSV_CTRL_WLOCK_00); 1738 } 1739 if (sc->chip & RTWN_CHIP_88E) { 1740 rtwn_write_2(sc, R92C_RSV_CTRL, 1741 rtwn_read_2(sc, R92C_RSV_CTRL) | R88E_RSV_CTRL_MCU_RST); 1742 } else { 1743 rtwn_write_2(sc, R92C_RSV_CTRL, 1744 rtwn_read_2(sc, R92C_RSV_CTRL) | R88E_RSV_CTRL_MIO_EN); 1745 } 1746 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1747 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | R92C_SYS_FUNC_EN_CPUEN); 1748 } 1749 1750 int 1751 rtwn_load_firmware(struct rtwn_softc *sc) 1752 { 1753 const struct r92c_fw_hdr *hdr; 1754 u_char *fw, *ptr; 1755 size_t len0, len; 1756 uint32_t reg; 1757 int mlen, ntries, page, error; 1758 1759 /* Read firmware image from the filesystem. */ 1760 error = sc->sc_ops.load_firmware(sc->sc_ops.cookie, &fw, &len0); 1761 if (error) 1762 return (error); 1763 len = len0; 1764 if (len < sizeof(*hdr)) { 1765 printf("%s: firmware too short\n", sc->sc_pdev->dv_xname); 1766 error = EINVAL; 1767 goto fail; 1768 } 1769 ptr = fw; 1770 hdr = (const struct r92c_fw_hdr *)ptr; 1771 /* Check if there is a valid FW header and skip it. */ 1772 if ((letoh16(hdr->signature) >> 4) == 0x230 || 1773 (letoh16(hdr->signature) >> 4) == 0x88c || 1774 (letoh16(hdr->signature) >> 4) == 0x88e || 1775 (letoh16(hdr->signature) >> 4) == 0x88f || 1776 (letoh16(hdr->signature) >> 4) == 0x92c || 1777 (letoh16(hdr->signature) >> 4) == 0x92e) { 1778 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 1779 letoh16(hdr->version), letoh16(hdr->subversion), 1780 hdr->month, hdr->date, hdr->hour, hdr->minute)); 1781 ptr += sizeof(*hdr); 1782 len -= sizeof(*hdr); 1783 } 1784 1785 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 1786 rtwn_write_1(sc, R92C_MCUFWDL, 0); 1787 rtwn_fw_reset(sc); 1788 } 1789 1790 if ((sc->chip & RTWN_CHIP_PCI) || (sc->chip & RTWN_CHIP_88F)) { 1791 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1792 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | R92C_SYS_FUNC_EN_CPUEN); 1793 } 1794 1795 /* Enable FW download. */ 1796 rtwn_write_1(sc, R92C_MCUFWDL, 1797 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 1798 rtwn_write_4(sc, R92C_MCUFWDL, 1799 rtwn_read_4(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_ROM_DLEN); 1800 1801 /* Reset the FWDL checksum. */ 1802 rtwn_write_1(sc, R92C_MCUFWDL, 1803 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 1804 1805 DELAY(50); 1806 for (page = 0; len > 0; page++) { 1807 mlen = MIN(len, R92C_FW_PAGE_SIZE); 1808 error = sc->sc_ops.fw_loadpage(sc->sc_ops.cookie, page, ptr, 1809 mlen); 1810 if (error != 0) { 1811 printf("%s: could not load firmware page %d\n", 1812 sc->sc_pdev->dv_xname, page); 1813 goto fail; 1814 } 1815 ptr += mlen; 1816 len -= mlen; 1817 } 1818 1819 /* Wait for checksum report. */ 1820 for (ntries = 0; ntries < 1000; ntries++) { 1821 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 1822 break; 1823 DELAY(5); 1824 } 1825 if (ntries == 1000) { 1826 printf("%s: timeout waiting for checksum report\n", 1827 sc->sc_pdev->dv_xname); 1828 error = ETIMEDOUT; 1829 goto fail; 1830 } 1831 1832 /* Disable FW download. */ 1833 rtwn_write_1(sc, R92C_MCUFWDL, 1834 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 1835 1836 /* Reserved for fw extension. */ 1837 if (!(sc->chip & (RTWN_CHIP_88F | RTWN_CHIP_92E))) 1838 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 1839 1840 reg = rtwn_read_4(sc, R92C_MCUFWDL); 1841 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 1842 rtwn_write_4(sc, R92C_MCUFWDL, reg); 1843 if (sc->chip & (RTWN_CHIP_92C | RTWN_CHIP_88C | RTWN_CHIP_23A)) { 1844 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 1845 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1846 reg & ~R92C_SYS_FUNC_EN_CPUEN); 1847 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 1848 reg | R92C_SYS_FUNC_EN_CPUEN); 1849 } else 1850 rtwn_fw_reset(sc); 1851 /* Wait for firmware readiness. */ 1852 for (ntries = 0; ntries < 1000; ntries++) { 1853 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 1854 break; 1855 DELAY(10); 1856 } 1857 if (ntries == 1000) { 1858 printf("%s: timeout waiting for firmware readiness\n", 1859 sc->sc_pdev->dv_xname); 1860 error = ETIMEDOUT; 1861 goto fail; 1862 } 1863 fail: 1864 free(fw, M_DEVBUF, len0); 1865 /* Init H2C command. */ 1866 if (sc->chip & RTWN_CHIP_88F) 1867 rtwn_write_1(sc, R92C_HMETFR, 0xf); 1868 return (error); 1869 } 1870 1871 void 1872 rtwn_rf_init(struct rtwn_softc *sc) 1873 { 1874 const struct r92c_rf_prog *prog; 1875 uint32_t reg, type; 1876 int i, j, idx, off; 1877 1878 /* Select RF programming based on board type. */ 1879 if (sc->chip & RTWN_CHIP_88E) 1880 prog = rtl8188eu_rf_prog; 1881 else if (sc->chip & RTWN_CHIP_88F) 1882 prog = rtl8188ftv_rf_prog; 1883 else if (sc->chip & RTWN_CHIP_92E) 1884 prog = rtl8192e_rf_prog; 1885 else if (!(sc->chip & RTWN_CHIP_92C)) { 1886 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 1887 prog = rtl8188ce_rf_prog; 1888 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 1889 prog = rtl8188ru_rf_prog; 1890 else 1891 prog = rtl8188cu_rf_prog; 1892 } else 1893 prog = rtl8192ce_rf_prog; 1894 1895 for (i = 0; i < sc->nrxchains; i++) { 1896 /* Save RF_ENV control type. */ 1897 idx = i / 2; 1898 off = (i % 2) * 16; 1899 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 1900 type = (reg >> off) & 0x10; 1901 1902 /* Set RF_ENV enable. */ 1903 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 1904 reg |= 0x100000; 1905 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 1906 DELAY(50); 1907 /* Set RF_ENV output high. */ 1908 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 1909 reg |= 0x10; 1910 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 1911 DELAY(50); 1912 /* Set address and data lengths of RF registers. */ 1913 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 1914 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 1915 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 1916 DELAY(50); 1917 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 1918 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 1919 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 1920 DELAY(50); 1921 1922 /* Write RF initialization values for this chain. */ 1923 for (j = 0; j < prog[i].count; j++) { 1924 switch (prog[i].regs[j]) { 1925 case 0xfe: 1926 case 0xffe: 1927 DELAY(50000); 1928 continue; 1929 case 0xfd: 1930 DELAY(5000); 1931 continue; 1932 case 0xfc: 1933 DELAY(1000); 1934 continue; 1935 case 0xfb: 1936 DELAY(50); 1937 continue; 1938 case 0xfa: 1939 DELAY(5); 1940 continue; 1941 case 0xf9: 1942 DELAY(1); 1943 continue; 1944 } 1945 rtwn_rf_write(sc, i, prog[i].regs[j], 1946 prog[i].vals[j]); 1947 DELAY(5); 1948 } 1949 1950 /* Restore RF_ENV control type. */ 1951 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 1952 reg &= ~(0x10 << off) | (type << off); 1953 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 1954 1955 /* Cache RF register CHNLBW. */ 1956 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 1957 } 1958 1959 /* magic value for HP 8188EEs */ 1960 if (sc->chip == (RTWN_CHIP_88E | RTWN_CHIP_PCI)) { 1961 struct r88e_rom *rom = &sc->sc_r88e_rom; 1962 if (rom->r88ee_rom.svid == 0x103c && 1963 rom->r88ee_rom.smid == 0x197d) 1964 rtwn_rf_write(sc, 0, 0x52, 0x7e4bd); 1965 } 1966 1967 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 1968 RTWN_CHIP_UMC_A_CUT) { 1969 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 1970 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 1971 } else if (sc->chip & RTWN_CHIP_23A) { 1972 rtwn_rf_write(sc, 0, 0x0C, 0x894ae); 1973 rtwn_rf_write(sc, 0, 0x0A, 0x1af31); 1974 rtwn_rf_write(sc, 0, R92C_RF_IPA, 0x8f425); 1975 rtwn_rf_write(sc, 0, R92C_RF_SYN_G(1), 0x4f200); 1976 rtwn_rf_write(sc, 0, R92C_RF_RCK1, 0x44053); 1977 rtwn_rf_write(sc, 0, R92C_RF_RCK2, 0x80201); 1978 } 1979 } 1980 1981 void 1982 rtwn_cam_init(struct rtwn_softc *sc) 1983 { 1984 /* Invalidate all CAM entries. */ 1985 rtwn_write_4(sc, R92C_CAMCMD, 1986 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 1987 } 1988 1989 void 1990 rtwn_pa_bias_init(struct rtwn_softc *sc) 1991 { 1992 uint8_t reg; 1993 int i; 1994 1995 for (i = 0; i < sc->nrxchains; i++) { 1996 if (sc->pa_setting & (1 << i)) 1997 continue; 1998 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 1999 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2000 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2001 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2002 } 2003 if (!(sc->pa_setting & 0x10)) { 2004 reg = rtwn_read_1(sc, 0x16); 2005 reg = (reg & ~0xf0) | 0x90; 2006 rtwn_write_1(sc, 0x16, reg); 2007 } 2008 } 2009 2010 void 2011 rtwn_rxfilter_init(struct rtwn_softc *sc) 2012 { 2013 /* Initialize Rx filter. */ 2014 rtwn_write_4(sc, R92C_RCR, 2015 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2016 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2017 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2018 /* Accept all multicast frames. */ 2019 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2020 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2021 /* Accept all management frames. */ 2022 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2023 /* Reject all control frames. */ 2024 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2025 /* Accept all data frames. */ 2026 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2027 } 2028 2029 void 2030 rtwn_edca_init(struct rtwn_softc *sc) 2031 { 2032 struct ieee80211com *ic = &sc->sc_ic; 2033 int mode, aci; 2034 2035 /* Set SIFS; 0x10 = 16 usec (SIFS 11g), 0x0a = 10 usec (SIFS 11b) */ 2036 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2037 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2038 rtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2039 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2040 if (!(sc->chip & RTWN_CHIP_88F)) { 2041 rtwn_write_2(sc, R92C_RESP_SIFS_CCK, 0x100a); 2042 rtwn_write_2(sc, R92C_RESP_SIFS_OFDM, 0x100a); 2043 } else { 2044 rtwn_write_2(sc, R92C_RESP_SIFS_CCK, 0x0808); 2045 rtwn_write_2(sc, R92C_RESP_SIFS_OFDM, 0x0a0a); 2046 } 2047 2048 if (ic->ic_curmode == IEEE80211_MODE_AUTO) 2049 mode = IEEE80211_MODE_11G; /* XXX */ 2050 else 2051 mode = ic->ic_curmode; 2052 for (aci = 0; aci < EDCA_NUM_AC; aci++) 2053 memcpy(&ic->ic_edca_ac[aci], &ieee80211_edca_table[mode][aci], 2054 sizeof(struct ieee80211_edca_ac_params)); 2055 rtwn_updateedca(ic); 2056 2057 if (sc->chip & RTWN_CHIP_PCI) { 2058 /* linux magic */ 2059 rtwn_write_4(sc, R92C_FAST_EDCA_CTRL, 0x086666); 2060 } 2061 2062 rtwn_write_4(sc, R92C_EDCA_RANDOM_GEN, arc4random()); 2063 } 2064 2065 void 2066 rtwn_rate_fallback_init(struct rtwn_softc *sc) 2067 { 2068 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2069 if (sc->chip & RTWN_CHIP_PCI) { 2070 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 2071 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 2072 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 2073 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 2074 } else if (sc->chip & RTWN_CHIP_USB) { 2075 rtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 2076 rtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 2077 rtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 2078 rtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 2079 } 2080 } 2081 } 2082 2083 void 2084 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2085 uint16_t power[RTWN_POWER_COUNT]) 2086 { 2087 uint32_t reg; 2088 2089 /* Write per-CCK rate Tx power. */ 2090 if (chain == 0) { 2091 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2092 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_POWER_CCK1]); 2093 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2094 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2095 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_POWER_CCK2]); 2096 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_POWER_CCK55]); 2097 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_POWER_CCK11]); 2098 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2099 } else { 2100 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2101 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_POWER_CCK1]); 2102 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_POWER_CCK2]); 2103 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_POWER_CCK55]); 2104 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2105 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2106 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_POWER_CCK11]); 2107 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2108 } 2109 /* Write per-OFDM rate Tx power. */ 2110 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2111 SM(R92C_TXAGC_RATE06, power[RTWN_POWER_OFDM6]) | 2112 SM(R92C_TXAGC_RATE09, power[RTWN_POWER_OFDM9]) | 2113 SM(R92C_TXAGC_RATE12, power[RTWN_POWER_OFDM12]) | 2114 SM(R92C_TXAGC_RATE18, power[RTWN_POWER_OFDM18])); 2115 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2116 SM(R92C_TXAGC_RATE24, power[RTWN_POWER_OFDM24]) | 2117 SM(R92C_TXAGC_RATE36, power[RTWN_POWER_OFDM36]) | 2118 SM(R92C_TXAGC_RATE48, power[RTWN_POWER_OFDM48]) | 2119 SM(R92C_TXAGC_RATE54, power[RTWN_POWER_OFDM54])); 2120 /* Write per-MCS Tx power. */ 2121 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2122 SM(R92C_TXAGC_MCS00, power[RTWN_POWER_MCS( 0)]) | 2123 SM(R92C_TXAGC_MCS01, power[RTWN_POWER_MCS( 1)]) | 2124 SM(R92C_TXAGC_MCS02, power[RTWN_POWER_MCS( 2)]) | 2125 SM(R92C_TXAGC_MCS03, power[RTWN_POWER_MCS( 3)])); 2126 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2127 SM(R92C_TXAGC_MCS04, power[RTWN_POWER_MCS( 4)]) | 2128 SM(R92C_TXAGC_MCS05, power[RTWN_POWER_MCS( 5)]) | 2129 SM(R92C_TXAGC_MCS06, power[RTWN_POWER_MCS( 6)]) | 2130 SM(R92C_TXAGC_MCS07, power[RTWN_POWER_MCS( 7)])); 2131 if (sc->ntxchains > 1) { 2132 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2133 SM(R92C_TXAGC_MCS08, power[RTWN_POWER_MCS( 8)]) | 2134 SM(R92C_TXAGC_MCS09, power[RTWN_POWER_MCS( 9)]) | 2135 SM(R92C_TXAGC_MCS10, power[RTWN_POWER_MCS(10)]) | 2136 SM(R92C_TXAGC_MCS11, power[RTWN_POWER_MCS(11)])); 2137 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2138 SM(R92C_TXAGC_MCS12, power[RTWN_POWER_MCS(12)]) | 2139 SM(R92C_TXAGC_MCS13, power[RTWN_POWER_MCS(13)]) | 2140 SM(R92C_TXAGC_MCS14, power[RTWN_POWER_MCS(14)]) | 2141 SM(R92C_TXAGC_MCS15, power[RTWN_POWER_MCS(15)])); 2142 } 2143 } 2144 2145 void 2146 rtwn_get_txpower(struct rtwn_softc *sc, int chain, struct ieee80211_channel *c, 2147 struct ieee80211_channel *extc, uint16_t power[RTWN_POWER_COUNT]) 2148 { 2149 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F)) 2150 rtwn_r88e_get_txpower(sc, chain, c, extc, power); 2151 else if (sc->chip & RTWN_CHIP_92E) 2152 rtwn_r92e_get_txpower(sc, chain, c, extc, power); 2153 else 2154 rtwn_r92c_get_txpower(sc, chain, c, extc, power); 2155 } 2156 2157 void 2158 rtwn_r92c_get_txpower(struct rtwn_softc *sc, int chain, 2159 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2160 uint16_t power[RTWN_POWER_COUNT]) 2161 { 2162 struct ieee80211com *ic = &sc->sc_ic; 2163 struct r92c_rom *rom = &sc->sc_r92c_rom; 2164 uint16_t cckpow, ofdmpow, htpow, diff, max; 2165 const struct r92c_txpwr *base; 2166 int ridx, chan, group; 2167 2168 /* Determine channel group. */ 2169 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2170 if (chan <= 3) 2171 group = 0; 2172 else if (chan <= 9) 2173 group = 1; 2174 else 2175 group = 2; 2176 2177 /* Get original Tx power based on board type and RF chain. */ 2178 if (!(sc->chip & RTWN_CHIP_92C)) { 2179 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2180 base = &rtl8188ru_txagc[chain]; 2181 else 2182 base = &rtl8192cu_txagc[chain]; 2183 } else 2184 base = &rtl8192cu_txagc[chain]; 2185 2186 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2187 if (sc->regulatory == 0) { 2188 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) 2189 power[ridx] = base->pwr[0][ridx]; 2190 } 2191 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_MAX; ridx++) { 2192 if (sc->regulatory == 3) { 2193 power[ridx] = base->pwr[0][ridx]; 2194 /* Apply vendor limits. */ 2195 if (extc != NULL) 2196 max = rom->ht40_max_pwr[group]; 2197 else 2198 max = rom->ht20_max_pwr[group]; 2199 max = (max >> (chain * 4)) & 0xf; 2200 if (power[ridx] > max) 2201 power[ridx] = max; 2202 } else if (sc->regulatory == 1) { 2203 if (extc == NULL) 2204 power[ridx] = base->pwr[group][ridx]; 2205 } else if (sc->regulatory != 2) 2206 power[ridx] = base->pwr[0][ridx]; 2207 } 2208 2209 /* Compute per-CCK rate Tx power. */ 2210 cckpow = rom->cck_tx_pwr[chain][group]; 2211 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2212 power[ridx] += cckpow; 2213 if (power[ridx] > R92C_MAX_TX_PWR) 2214 power[ridx] = R92C_MAX_TX_PWR; 2215 } 2216 2217 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2218 if (sc->ntxchains > 1) { 2219 /* Apply reduction for 2 spatial streams. */ 2220 diff = rom->ht40_2s_tx_pwr_diff[group]; 2221 diff = (diff >> (chain * 4)) & 0xf; 2222 htpow = (htpow > diff) ? htpow - diff : 0; 2223 } 2224 2225 /* Compute per-OFDM rate Tx power. */ 2226 diff = rom->ofdm_tx_pwr_diff[group]; 2227 diff = (diff >> (chain * 4)) & 0xf; 2228 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2229 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2230 power[ridx] += ofdmpow; 2231 if (power[ridx] > R92C_MAX_TX_PWR) 2232 power[ridx] = R92C_MAX_TX_PWR; 2233 } 2234 2235 /* Compute per-MCS Tx power. */ 2236 if (extc == NULL) { 2237 diff = rom->ht20_tx_pwr_diff[group]; 2238 diff = (diff >> (chain * 4)) & 0xf; 2239 htpow += diff; /* HT40->HT20 correction. */ 2240 } 2241 for (ridx = RTWN_RIDX_MCS0; ridx <= RTWN_RIDX_MCS15; ridx++) { 2242 power[ridx] += htpow; 2243 if (power[ridx] > R92C_MAX_TX_PWR) 2244 power[ridx] = R92C_MAX_TX_PWR; 2245 } 2246 #ifdef RTWN_DEBUG 2247 if (rtwn_debug >= 4) { 2248 /* Dump per-rate Tx power values. */ 2249 printf("Tx power for chain %d:\n", chain); 2250 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_MAX; ridx++) 2251 printf("Rate %d = %u\n", ridx, power[ridx]); 2252 } 2253 #endif 2254 } 2255 2256 void 2257 rtwn_r92e_get_txpower(struct rtwn_softc *sc, int chain, 2258 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2259 uint16_t power[RTWN_POWER_COUNT]) 2260 { 2261 struct ieee80211com *ic = &sc->sc_ic; 2262 struct r92e_rom *rom = &sc->sc_r92e_rom; 2263 struct r92e_tx_pwr *txpwr; 2264 uint8_t cckpow, htpow, htpow2s = 0, ofdmpow; 2265 int8_t diff; 2266 int ridx, chan, group; 2267 2268 /* Determine channel group. */ 2269 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2270 group = rtwn_chan2group(chan); 2271 2272 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2273 2274 if (chain == 0) 2275 txpwr = &rom->txpwr_a; 2276 else 2277 txpwr = &rom->txpwr_b; 2278 2279 /* Compute per-CCK rate Tx power. */ 2280 cckpow = txpwr->cck_tx_pwr[group]; 2281 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2282 power[ridx] = cckpow; 2283 if (power[ridx] > R92C_MAX_TX_PWR) 2284 power[ridx] = R92C_MAX_TX_PWR; 2285 } 2286 2287 htpow = txpwr->ht40_tx_pwr[group]; 2288 2289 /* Compute per-OFDM rate Tx power. */ 2290 diff = RTWN_SIGN4TO8(MS(txpwr->ht20_ofdm_tx_pwr_diff, 2291 R92E_ROM_TXPWR_OFDM_DIFF)); 2292 ofdmpow = htpow + diff; 2293 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2294 power[ridx] = ofdmpow; 2295 if (power[ridx] > R92C_MAX_TX_PWR) 2296 power[ridx] = R92C_MAX_TX_PWR; 2297 } 2298 2299 /* Compute per-MCS Tx power. */ 2300 if (extc == NULL) { 2301 diff = RTWN_SIGN4TO8(MS(txpwr->ht20_ofdm_tx_pwr_diff, 2302 R92E_ROM_TXPWR_HT20_DIFF)); 2303 htpow += diff; 2304 if (sc->ntxchains > 1) { 2305 diff = RTWN_SIGN4TO8(MS( 2306 txpwr->pwr_diff[0].ht40_ht20_tx_pwr_diff, 2307 R92E_ROM_TXPWR_HT20_2S_DIFF)); 2308 htpow2s = htpow + diff; 2309 } 2310 } 2311 2312 for (ridx = RTWN_RIDX_MCS0; ridx <= RTWN_RIDX_MCS15; ridx++) { 2313 power[ridx] = (ridx < RTWN_RIDX_MCS8) ? htpow : htpow2s; 2314 if (power[ridx] > R92C_MAX_TX_PWR) 2315 power[ridx] = R92C_MAX_TX_PWR; 2316 } 2317 } 2318 2319 void 2320 rtwn_r88e_get_txpower(struct rtwn_softc *sc, int chain, 2321 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2322 uint16_t power[RTWN_POWER_COUNT]) 2323 { 2324 struct ieee80211com *ic = &sc->sc_ic; 2325 struct r88e_rom *rom = &sc->sc_r88e_rom; 2326 uint8_t cckpow, htpow, ofdmpow; 2327 int8_t diff; 2328 int ridx, chan, group; 2329 2330 /* Determine channel group. */ 2331 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2332 if (sc->chip & RTWN_CHIP_88F) 2333 group = rtwn_chan2group(chan); 2334 else { 2335 if (chan <= 2) 2336 group = 0; 2337 else if (chan <= 5) 2338 group = 1; 2339 else if (chan <= 8) 2340 group = 2; 2341 else if (chan <= 11) 2342 group = 3; 2343 else if (chan <= 13) 2344 group = 4; 2345 else 2346 group = 5; 2347 } 2348 2349 memset(power, 0, RTWN_POWER_COUNT * sizeof(power[0])); 2350 2351 /* Compute per-CCK rate Tx power. */ 2352 cckpow = rom->txpwr.cck_tx_pwr[group]; 2353 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) { 2354 if (sc->chip & RTWN_CHIP_88F) 2355 power[ridx] = cckpow; 2356 else 2357 power[ridx] = (ridx == RTWN_RIDX_CCK2) ? 2358 cckpow - 9 : cckpow; 2359 if (power[ridx] > R92C_MAX_TX_PWR) 2360 power[ridx] = R92C_MAX_TX_PWR; 2361 } 2362 2363 if (sc->chip & RTWN_CHIP_88F) 2364 htpow = rom->txpwr.ht40_tx_pwr[group]; 2365 else 2366 htpow = (group == 5) ? rom->txpwr.ht40_tx_pwr[group - 1] : 2367 rom->txpwr.ht40_tx_pwr[group]; 2368 2369 /* Compute per-OFDM rate Tx power. */ 2370 diff = RTWN_SIGN4TO8(MS(rom->txpwr.ht20_ofdm_tx_pwr_diff, 2371 R88E_ROM_TXPWR_OFDM_DIFF)); 2372 ofdmpow = htpow + diff; 2373 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) { 2374 power[ridx] = ofdmpow; 2375 if (power[ridx] > R92C_MAX_TX_PWR) 2376 power[ridx] = R92C_MAX_TX_PWR; 2377 } 2378 2379 /* Compute per-MCS Tx power. */ 2380 if (extc == NULL) { 2381 diff = RTWN_SIGN4TO8(MS(rom->txpwr.ht20_ofdm_tx_pwr_diff, 2382 R88E_ROM_TXPWR_HT20_DIFF)); 2383 htpow += diff; 2384 } 2385 for (ridx = RTWN_RIDX_MCS0; ridx < RTWN_RIDX_MCS8; ridx++) { 2386 power[ridx] = htpow; 2387 if (power[ridx] > R92C_MAX_TX_PWR) 2388 power[ridx] = R92C_MAX_TX_PWR; 2389 } 2390 } 2391 2392 void 2393 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 2394 struct ieee80211_channel *extc) 2395 { 2396 uint16_t power[RTWN_POWER_COUNT]; 2397 int i; 2398 2399 for (i = 0; i < sc->ntxchains; i++) { 2400 /* Compute per-rate Tx power values. */ 2401 rtwn_get_txpower(sc, i, c, extc, power); 2402 /* Write per-rate Tx power values to hardware. */ 2403 rtwn_write_txpower(sc, i, power); 2404 } 2405 } 2406 2407 void 2408 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 2409 struct ieee80211_channel *extc) 2410 { 2411 struct ieee80211com *ic = &sc->sc_ic; 2412 u_int chan; 2413 uint32_t reg; 2414 int i; 2415 2416 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2417 2418 /* Set Tx power for this new channel. */ 2419 rtwn_set_txpower(sc, c, extc); 2420 2421 if (extc != NULL) { 2422 /* Is secondary channel below or above primary? */ 2423 int prichlo = c->ic_freq < extc->ic_freq; 2424 2425 if (sc->chip & RTWN_CHIP_92E) { 2426 reg = rtwn_read_2(sc, R92C_WMAC_TRXPTCL_CTL); 2427 reg &= ~R92C_WMAC_TRXPTCL_CTL_BW_MASK; 2428 reg |= R92C_WMAC_TRXPTCL_CTL_BW_40; 2429 rtwn_write_2(sc, R92C_WMAC_TRXPTCL_CTL, reg); 2430 rtwn_write_1(sc, R92E_DATA_SC, 0); 2431 } else { 2432 rtwn_write_1(sc, R92C_BWOPMODE, 2433 rtwn_read_1(sc, R92C_BWOPMODE) & 2434 ~R92C_BWOPMODE_20MHZ); 2435 } 2436 2437 reg = rtwn_read_1(sc, R92C_RRSR + 2); 2438 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2439 rtwn_write_1(sc, R92C_RRSR + 2, reg); 2440 2441 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2442 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2443 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2444 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2445 2446 /* Set CCK side band. */ 2447 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2448 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2449 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2450 2451 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 2452 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2453 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2454 2455 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E))) { 2456 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2457 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2458 ~R92C_FPGA0_ANAPARAM2_CBW20); 2459 } 2460 2461 reg = rtwn_bb_read(sc, 0x818); 2462 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2463 rtwn_bb_write(sc, 0x818, reg); 2464 2465 /* Select 40MHz bandwidth. */ 2466 for (i = 0; i < sc->nrxchains; i++) { 2467 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2468 (sc->rf_chnlbw[i] & ~0xfff) | chan); 2469 } 2470 } else { 2471 if (sc->chip & RTWN_CHIP_92E) { 2472 reg = rtwn_read_2(sc, R92C_WMAC_TRXPTCL_CTL); 2473 reg &= ~R92C_WMAC_TRXPTCL_CTL_BW_MASK; 2474 rtwn_write_2(sc, R92C_WMAC_TRXPTCL_CTL, reg); 2475 rtwn_write_1(sc, R92E_DATA_SC, 0); 2476 } else if (!(sc->chip & RTWN_CHIP_88F)) { 2477 rtwn_write_1(sc, R92C_BWOPMODE, 2478 rtwn_read_1(sc, R92C_BWOPMODE) | 2479 R92C_BWOPMODE_20MHZ); 2480 } 2481 2482 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2483 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2484 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2485 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2486 2487 if (!(sc->chip & 2488 (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) { 2489 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2490 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2491 R92C_FPGA0_ANAPARAM2_CBW20); 2492 } else if (sc->chip & (RTWN_CHIP_88F | RTWN_CHIP_92E)) { 2493 if (sc->chip & RTWN_CHIP_88F) { 2494 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2495 reg = (reg & ~0x00000700) | 0x7 << 8; 2496 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2497 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 2498 reg = (reg & ~0x00007000) | 0x5 << 12; 2499 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 2500 } 2501 2502 reg = rtwn_bb_read(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT); 2503 reg &= ~0xc0000000; 2504 rtwn_bb_write(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT, reg); 2505 2506 if (sc->chip & RTWN_CHIP_88F) { 2507 /* Small bandwidth */ 2508 reg = rtwn_bb_read(sc, 2509 R92C_OFDM0_TX_PSDO_NOISE_WEIGHT); 2510 reg |= 0x30000000; 2511 rtwn_bb_write(sc, 2512 R92C_OFDM0_TX_PSDO_NOISE_WEIGHT, reg); 2513 /* ADC buffer clk */ 2514 rtwn_bb_write(sc, R92C_OFDM0_RXAFE, 2515 rtwn_bb_read(sc, R92C_OFDM0_RXAFE) | 2516 0x30000000); 2517 /* OFDM Rx DFIR */ 2518 rtwn_bb_write(sc, R88F_RX_DFIR, 2519 rtwn_bb_read(sc, R88F_RX_DFIR) & 2520 ~0x00080000); 2521 reg = rtwn_bb_read(sc, R88F_RX_DFIR); 2522 reg = (reg & ~0x00f00000) | 0x3 << 15; 2523 rtwn_bb_write(sc, R88F_RX_DFIR, reg); 2524 } 2525 } 2526 2527 /* Select 20MHz bandwidth. */ 2528 for (i = 0; i < sc->nrxchains; i++) { 2529 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2530 (sc->rf_chnlbw[i] & ~0xfff) | chan | 2531 ((sc->chip & 2532 (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) ? 2533 R88E_RF_CHNLBW_BW20 : R92C_RF_CHNLBW_BW20)); 2534 2535 if (sc->chip & RTWN_CHIP_88F) { 2536 rtwn_rf_write(sc, i, 0x87, 0x65); 2537 rtwn_rf_write(sc, i, 0x1c, 0); 2538 rtwn_rf_write(sc, i, 0xdf, 0x0140); 2539 rtwn_rf_write(sc, i, 0x1b, 0x1c6c); 2540 } 2541 } 2542 } 2543 2544 if (sc->chip == (RTWN_CHIP_88E | RTWN_CHIP_PCI)) 2545 DELAY(25000); 2546 } 2547 2548 int 2549 rtwn_chan2group(int chan) 2550 { 2551 int group; 2552 2553 if (chan <= 2) 2554 group = 0; 2555 else if (chan <= 5) 2556 group = 1; 2557 else if (chan <= 8) 2558 group = 2; 2559 else if (chan <= 11) 2560 group = 3; 2561 else 2562 group = 4; 2563 2564 return (group); 2565 } 2566 2567 int 2568 rtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 2569 uint16_t rx[2]) 2570 { 2571 uint32_t status; 2572 int offset = chain * 0x20; 2573 uint32_t iqk_tone_92c[] = { 2574 0x10008c1f, 0x10008c1f, 0x82140102, 0x28160202, 0x10008c22 2575 }; 2576 uint32_t iqk_tone_92e[] = { 2577 0x18008c1c, 0x38008c1c, 0x82140303, 0x68160000, 0x38008c1c 2578 }; 2579 uint32_t *iqk_tone; 2580 2581 if (sc->chip & RTWN_CHIP_92E) 2582 iqk_tone = iqk_tone_92e; 2583 else 2584 iqk_tone = iqk_tone_92c; 2585 2586 if (chain == 0) { /* IQ calibration for chain 0. */ 2587 /* IQ calibration settings for chain 0. */ 2588 rtwn_bb_write(sc, R92C_TX_IQK_TONE_A, iqk_tone[0]); 2589 rtwn_bb_write(sc, R92C_RX_IQK_TONE_B, iqk_tone[1]); 2590 rtwn_bb_write(sc, R92C_TX_IQK_PI_A, iqk_tone[2]); 2591 2592 if (sc->ntxchains > 1) { 2593 rtwn_bb_write(sc, R92C_RX_IQK_PI_A, iqk_tone[3]); 2594 /* IQ calibration settings for chain 1. */ 2595 rtwn_bb_write(sc, R92C_TX_IQK_TONE_B, iqk_tone[4]); 2596 rtwn_bb_write(sc, R92C_RX_IQK_TONE_B, iqk_tone[4]); 2597 rtwn_bb_write(sc, R92C_TX_IQK_PI_B, 0x82140102); 2598 rtwn_bb_write(sc, R92C_RX_IQK_PI_B, 0x28160202); 2599 } else 2600 rtwn_bb_write(sc, R92C_RX_IQK_PI_A, 0x28160502); 2601 2602 /* LO calibration settings. */ 2603 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_92E)) 2604 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x00462911); 2605 else 2606 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1); 2607 /* We're doing LO and IQ calibration in one shot. */ 2608 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000); 2609 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000); 2610 2611 } else { /* IQ calibration for chain 1. */ 2612 /* We're doing LO and IQ calibration in one shot. */ 2613 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0x00000002); 2614 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0x00000000); 2615 } 2616 2617 /* Give LO and IQ calibrations the time to complete. */ 2618 DELAY(1000); 2619 2620 /* Read IQ calibration status. */ 2621 status = rtwn_bb_read(sc, 0xeac); 2622 2623 if (status & (1 << (28 + chain * 3))) 2624 return (0); /* Tx failed. */ 2625 /* Read Tx IQ calibration results. */ 2626 tx[0] = (rtwn_bb_read(sc, R92C_TX_POWER_BEFORE_IQK_A + offset) >> 16) 2627 & 0x3ff; 2628 tx[1] = (rtwn_bb_read(sc, R92C_TX_POWER_AFTER_IQK_A + offset) >> 16) 2629 & 0x3ff; 2630 if (tx[0] == 0x142 || tx[1] == 0x042) 2631 return (0); /* Tx failed. */ 2632 2633 if (status & (1 << (27 + chain * 3))) 2634 return (1); /* Rx failed. */ 2635 /* Read Rx IQ calibration results. */ 2636 rx[0] = (rtwn_bb_read(sc, R92C_RX_POWER_BEFORE_IQK_A_2 + offset) >> 16) 2637 & 0x3ff; 2638 rx[1] = (rtwn_bb_read(sc, R92C_RX_POWER_AFTER_IQK_A_2 + offset) >> 16) 2639 & 0x3ff; 2640 if (rx[0] == 0x132 || rx[1] == 0x036) 2641 return (1); /* Rx failed. */ 2642 2643 return (3); /* Both Tx and Rx succeeded. */ 2644 } 2645 2646 void 2647 rtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 2648 uint16_t rx[2][2], struct rtwn_iq_cal_regs *iq_cal_regs) 2649 { 2650 static const uint16_t reg_adda[16] = { 2651 0x85c, 0xe6c, 0xe70, 0xe74, 2652 0xe78, 0xe7c, 0xe80, 0xe84, 2653 0xe88, 0xe8c, 0xed0, 0xed4, 2654 0xed8, 0xedc, 0xee0, 0xeec 2655 }; 2656 static const uint32_t adda_92c[] = { 2657 0x0b1b25a0, 0x0bdb25a0, 0x04db25a4, 0x0b1b25a4 2658 }; 2659 static const uint32_t adda_92e[] = { 2660 0x0fc01616, 0x0fc01616, 0x0fc01616, 0x0fc01616 2661 }; 2662 const uint32_t *adda_vals; 2663 2664 int i, chain; 2665 uint32_t hssi_param1, reg; 2666 uint8_t xa_agc, xb_agc; 2667 2668 xa_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)) & 0xff; 2669 xb_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)) & 0xff; 2670 2671 if (sc->chip & RTWN_CHIP_92E) 2672 adda_vals = adda_92e; 2673 else 2674 adda_vals = adda_92c; 2675 2676 if (n == 0) { 2677 for (i = 0; i < nitems(reg_adda); i++) 2678 iq_cal_regs->adda[i] = rtwn_bb_read(sc, reg_adda[i]); 2679 2680 iq_cal_regs->txpause = rtwn_read_1(sc, R92C_TXPAUSE); 2681 iq_cal_regs->bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL); 2682 iq_cal_regs->bcn_ctrl1 = rtwn_read_1(sc, R92C_BCN_CTRL1); 2683 iq_cal_regs->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 2684 } 2685 2686 if (sc->ntxchains == 1) { 2687 rtwn_bb_write(sc, reg_adda[0], adda_vals[0]); 2688 for (i = 1; i < nitems(reg_adda); i++) 2689 rtwn_bb_write(sc, reg_adda[i], adda_vals[1]); 2690 } else { 2691 for (i = 0; i < nitems(reg_adda); i++) 2692 rtwn_bb_write(sc, reg_adda[i], adda_vals[2]); 2693 } 2694 2695 if (n == 0) { 2696 iq_cal_regs->ofdm0_trxpathena = 2697 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2698 iq_cal_regs->ofdm0_trmuxpar = 2699 rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 2700 iq_cal_regs->fpga0_rfifacesw0 = 2701 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)); 2702 iq_cal_regs->fpga0_rfifacesw1 = 2703 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 2704 iq_cal_regs->fpga0_rfifaceoe0 = 2705 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0)); 2706 iq_cal_regs->fpga0_rfifaceoe1 = 2707 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1)); 2708 iq_cal_regs->config_ant_a = 2709 rtwn_bb_read(sc, R92C_CONFIG_ANT_A); 2710 iq_cal_regs->config_ant_b = 2711 rtwn_bb_read(sc, R92C_CONFIG_ANT_B); 2712 iq_cal_regs->cck0_afesetting = 2713 rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2714 } 2715 2716 if (sc->chip & RTWN_CHIP_92E) { 2717 rtwn_write_4(sc, R92C_CCK0_AFESETTING, rtwn_read_4(sc, 2718 R92C_CCK0_AFESETTING) | 0x0f000000); 2719 } else { 2720 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 2721 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2722 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2723 hssi_param1 | R92C_HSSI_PARAM1_PI); 2724 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2725 hssi_param1 | R92C_HSSI_PARAM1_PI); 2726 } 2727 } 2728 2729 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 2730 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 2731 2732 if (sc->chip & RTWN_CHIP_92E) { 2733 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22208200); 2734 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), 2735 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)) | (1 << 10) | 2736 (1 << 26)); 2737 2738 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), rtwn_bb_read(sc, 2739 R92C_FPGA0_RFIFACEOE(0)) | (1 << 10)); 2740 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), rtwn_bb_read(sc, 2741 R92C_FPGA0_RFIFACEOE(1)) | (1 << 10)); 2742 } else { 2743 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 2744 2745 if (sc->ntxchains > 1) { 2746 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2747 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 2748 } 2749 2750 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TXPAUSE_AC_VO | 2751 R92C_TXPAUSE_AC_VI | R92C_TXPAUSE_AC_BE | 2752 R92C_TXPAUSE_AC_BK | R92C_TXPAUSE_MGNT | 2753 R92C_TXPAUSE_HIGH); 2754 } 2755 rtwn_write_1(sc, R92C_BCN_CTRL, 2756 iq_cal_regs->bcn_ctrl & ~(R92C_BCN_CTRL_EN_BCN)); 2757 rtwn_write_1(sc, R92C_BCN_CTRL1, 2758 iq_cal_regs->bcn_ctrl1 & ~(R92C_BCN_CTRL_EN_BCN)); 2759 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2760 iq_cal_regs->gpio_muxcfg & ~(R92C_GPIO_MUXCFG_ENBT)); 2761 2762 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 0x00080000); 2763 if (sc->ntxchains > 1) 2764 rtwn_bb_write(sc, R92C_CONFIG_ANT_B, 0x00080000); 2765 2766 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 2767 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); 2768 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800); 2769 2770 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 0x00080000); 2771 2772 for (chain = 0; chain < sc->ntxchains; chain++) { 2773 if (chain > 0) { 2774 /* Put chain 0 on standby. */ 2775 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00); 2776 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2777 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); 2778 2779 /* Enable chain 1. */ 2780 for (i = 0; i < nitems(reg_adda); i++) 2781 rtwn_bb_write(sc, reg_adda[i], adda_vals[3]); 2782 } 2783 2784 /* Run IQ calibration twice. */ 2785 for (i = 0; i < 2; i++) { 2786 int ret; 2787 2788 ret = rtwn_iq_calib_chain(sc, chain, 2789 tx[chain], rx[chain]); 2790 if (ret == 0) { 2791 DPRINTF(("%s: chain %d: Tx failed.\n", 2792 __func__, chain)); 2793 tx[chain][0] = 0xff; 2794 tx[chain][1] = 0xff; 2795 rx[chain][0] = 0xff; 2796 rx[chain][1] = 0xff; 2797 } else if (ret == 1) { 2798 DPRINTF(("%s: chain %d: Rx failed.\n", 2799 __func__, chain)); 2800 rx[chain][0] = 0xff; 2801 rx[chain][1] = 0xff; 2802 } else if (ret == 3) { 2803 DPRINTF(("%s: chain %d: Both Tx and Rx " 2804 "succeeded.\n", __func__, chain)); 2805 } 2806 } 2807 2808 DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, " 2809 "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain, 2810 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1])); 2811 } 2812 2813 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x00); 2814 2815 if (!(sc->chip & RTWN_CHIP_92E)) { 2816 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 2817 if (sc->ntxchains > 1) 2818 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 2819 } 2820 2821 if (n != 0) { 2822 if (!(sc->chip & RTWN_CHIP_92E)) { 2823 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2824 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2825 hssi_param1); 2826 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2827 hssi_param1); 2828 } 2829 } 2830 2831 for (i = 0; i < nitems(reg_adda); i++) 2832 rtwn_bb_write(sc, reg_adda[i], iq_cal_regs->adda[i]); 2833 2834 rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs->txpause); 2835 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs->bcn_ctrl); 2836 rtwn_write_1(sc, R92C_BCN_CTRL1, iq_cal_regs->bcn_ctrl1); 2837 rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs->gpio_muxcfg); 2838 2839 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 2840 iq_cal_regs->ofdm0_trxpathena); 2841 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), 2842 iq_cal_regs->fpga0_rfifacesw0); 2843 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 2844 iq_cal_regs->fpga0_rfifacesw1); 2845 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), 2846 iq_cal_regs->fpga0_rfifaceoe0); 2847 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), 2848 iq_cal_regs->fpga0_rfifaceoe1); 2849 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 2850 iq_cal_regs->ofdm0_trmuxpar); 2851 rtwn_bb_write(sc, R92C_CONFIG_ANT_A, 2852 iq_cal_regs->config_ant_a); 2853 rtwn_bb_write(sc, R92C_CONFIG_ANT_B, 2854 iq_cal_regs->config_ant_b); 2855 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, 2856 iq_cal_regs->cck0_afesetting); 2857 2858 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 2859 reg &= ~0xff; 2860 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | 0x50); 2861 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg | xa_agc); 2862 2863 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 2864 reg &= ~0xff; 2865 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | 0x50); 2866 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg | xb_agc); 2867 2868 rtwn_bb_write(sc, R92C_TX_IQK_TONE_A, 0x01008c00); 2869 rtwn_bb_write(sc, R92C_RX_IQK_TONE_A, 0x01008c00); 2870 } 2871 } 2872 2873 #define RTWN_IQ_CAL_MAX_TOLERANCE 5 2874 int 2875 rtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2], 2876 uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains) 2877 { 2878 int chain, i, tx_ok[2], rx_ok[2]; 2879 2880 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 2881 for (chain = 0; chain < ntxchains; chain++) { 2882 for (i = 0; i < 2; i++) { 2883 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 2884 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 2885 continue; 2886 2887 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 2888 RTWN_IQ_CAL_MAX_TOLERANCE); 2889 2890 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 2891 RTWN_IQ_CAL_MAX_TOLERANCE); 2892 } 2893 } 2894 2895 if (ntxchains > 1) 2896 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 2897 else 2898 return (tx_ok[0] && rx_ok[0]); 2899 } 2900 #undef RTWN_IQ_CAL_MAX_TOLERANCE 2901 2902 void 2903 rtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 2904 uint16_t rx[2], int chain) 2905 { 2906 uint32_t reg, val, x; 2907 long y, tx_c; 2908 2909 if (tx[0] == 0xff || tx[1] == 0xff) 2910 return; 2911 2912 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 2913 val = ((reg >> 22) & 0x3ff); 2914 x = tx[0]; 2915 if (x & 0x00000200) 2916 x |= 0xfffffc00; 2917 reg &= ~0x3ff; 2918 reg |= (((x * val) >> 8) & 0x3ff); 2919 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 2920 2921 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 2922 if (((x * val) >> 7) & 0x01) 2923 reg |= 0x80000000; 2924 else 2925 reg &= ~0x80000000; 2926 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 2927 2928 y = tx[1]; 2929 if (y & 0x00000200) 2930 y |= 0xfffffc00; 2931 tx_c = (y * val) >> 8; 2932 reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain)); 2933 reg &= ~0xf0000000; 2934 reg |= ((tx_c & 0x3c0) << 22); 2935 rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg); 2936 2937 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 2938 reg &= ~0x003f0000; 2939 reg |= ((tx_c & 0x3f) << 16); 2940 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 2941 2942 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 2943 if (((y * val) >> 7) & 0x01) 2944 reg |= 0x20000000; 2945 else 2946 reg &= ~0x20000000; 2947 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 2948 2949 if (rx[0] == 0xff || rx[1] == 0xff) 2950 return; 2951 2952 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain)); 2953 reg &= ~0x3ff; 2954 reg |= (rx[0] & 0x3ff); 2955 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 2956 2957 reg &= ~0xfc00; 2958 reg |= ((rx[1] & 0x03f) << 10); 2959 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 2960 2961 if (chain == 0) { 2962 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA); 2963 reg &= ~0xf0000000; 2964 reg |= ((rx[1] & 0x3c0) << 22); 2965 rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg); 2966 } else { 2967 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE); 2968 reg &= ~0xf000; 2969 reg |= ((rx[1] & 0x3c0) << 6); 2970 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg); 2971 } 2972 } 2973 2974 #define RTWN_IQ_CAL_NRUN 3 2975 void 2976 rtwn_iq_calib(struct rtwn_softc *sc) 2977 { 2978 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 2979 int n, valid; 2980 struct rtwn_iq_cal_regs regs; 2981 2982 valid = 0; 2983 memset(®s, 0, sizeof(regs)); 2984 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 2985 rtwn_iq_calib_run(sc, n, tx[n], rx[n], ®s); 2986 2987 if (n == 0) 2988 continue; 2989 2990 /* Valid results remain stable after consecutive runs. */ 2991 valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1], 2992 tx[n], rx[n], sc->ntxchains); 2993 if (valid) 2994 break; 2995 } 2996 2997 if (valid) { 2998 rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 2999 if (sc->ntxchains > 1) 3000 rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 3001 } 3002 } 3003 #undef RTWN_IQ_CAL_NRUN 3004 3005 void 3006 rtwn_lc_calib(struct rtwn_softc *sc) 3007 { 3008 uint32_t rf_ac[2]; 3009 uint8_t txmode; 3010 int i; 3011 3012 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3013 if ((txmode & 0x70) != 0) { 3014 /* Disable all continuous Tx. */ 3015 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3016 3017 /* Set RF mode to standby mode. */ 3018 for (i = 0; i < sc->nrxchains; i++) { 3019 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3020 rtwn_rf_write(sc, i, R92C_RF_AC, 3021 RW(rf_ac[i], R92C_RF_AC_MODE, 3022 R92C_RF_AC_MODE_STANDBY)); 3023 } 3024 } else { 3025 /* Block all Tx queues. */ 3026 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TXPAUSE_ALL); 3027 } 3028 /* Start calibration. */ 3029 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3030 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3031 3032 /* Give calibration the time to complete. */ 3033 DELAY(100); 3034 3035 /* Restore configuration. */ 3036 if ((txmode & 0x70) != 0) { 3037 /* Restore Tx mode. */ 3038 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3039 /* Restore RF mode. */ 3040 for (i = 0; i < sc->nrxchains; i++) 3041 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3042 } else { 3043 /* Unblock all Tx queues. */ 3044 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3045 } 3046 } 3047 3048 void 3049 rtwn_temp_calib(struct rtwn_softc *sc) 3050 { 3051 int temp, t_meter_reg, t_meter_val; 3052 3053 if (sc->chip & RTWN_CHIP_92E) { 3054 t_meter_reg = R92E_RF_T_METER; 3055 t_meter_val = 0x37cf8; 3056 } else { 3057 t_meter_reg = R92C_RF_T_METER; 3058 t_meter_val = 0x60; 3059 } 3060 3061 if (sc->thcal_state == 0) { 3062 /* Start measuring temperature. */ 3063 rtwn_rf_write(sc, 0, t_meter_reg, t_meter_val); 3064 sc->thcal_state = 1; 3065 return; 3066 } 3067 sc->thcal_state = 0; 3068 3069 /* Read measured temperature. */ 3070 temp = rtwn_rf_read(sc, 0, t_meter_reg) & 0x1f; 3071 if (temp == 0) /* Read failed, skip. */ 3072 return; 3073 DPRINTFN(2, ("temperature=%d\n", temp)); 3074 3075 /* 3076 * Redo IQ and LC calibration if temperature changed significantly 3077 * since last calibration. 3078 */ 3079 if (sc->thcal_lctemp == 0) { 3080 /* First calibration is performed in rtwn_init(). */ 3081 sc->thcal_lctemp = temp; 3082 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3083 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3084 sc->thcal_lctemp, temp)); 3085 rtwn_iq_calib(sc); 3086 rtwn_lc_calib(sc); 3087 /* Record temperature of last calibration. */ 3088 sc->thcal_lctemp = temp; 3089 } 3090 } 3091 3092 void 3093 rtwn_enable_intr(struct rtwn_softc *sc) 3094 { 3095 if (sc->chip & RTWN_CHIP_92E) { 3096 rtwn_write_4(sc, R88E_HISR, 0xffffffff); 3097 rtwn_write_4(sc, R88E_HISRE, 0xffffffff); 3098 rtwn_write_4(sc, R88E_HIMR, 0); 3099 rtwn_write_4(sc, R88E_HIMRE, 0); 3100 } else if (sc->chip & RTWN_CHIP_88E) { 3101 rtwn_write_4(sc, R88E_HISR, 0xffffffff); 3102 if (sc->chip & RTWN_CHIP_USB) { 3103 rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | 3104 R88E_HIMR_CPWM2 | R88E_HIMR_TBDER | 3105 R88E_HIMR_PSTIMEOUT); 3106 rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3107 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | 3108 R88E_HIMRE_TXERR); 3109 } else { 3110 rtwn_write_4(sc, R88E_HIMR, 3111 RTWN_88E_INT_ENABLE); 3112 rtwn_write_4(sc, R88E_HIMRE, 3113 R88E_HIMRE_RXFOVW); 3114 rtwn_write_1(sc, R92C_C2HEVT_CLEAR, 0); 3115 rtwn_write_4(sc, R92C_HSIMR, 3116 R88E_HSIMR_PDN_INT_EN | R88E_HSIMR_RON_INT_EN); 3117 } 3118 3119 if (sc->chip & RTWN_CHIP_USB) { 3120 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3121 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3122 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3123 } 3124 } else { 3125 uint32_t imask = 0; 3126 3127 if (sc->chip & RTWN_CHIP_USB) 3128 imask = 0xffffffff; 3129 else if (sc->chip & RTWN_CHIP_PCI) 3130 imask = RTWN_92C_INT_ENABLE; 3131 else 3132 panic("unknown chip type 0x%x", sc->chip); 3133 3134 /* CLear pending interrupts. */ 3135 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3136 3137 /* Enable interrupts. */ 3138 rtwn_write_4(sc, R92C_HIMR, imask); 3139 } 3140 } 3141 3142 void 3143 rtwn_disable_intr(struct rtwn_softc *sc) 3144 { 3145 if (sc->chip & RTWN_CHIP_88E) { 3146 rtwn_write_4(sc, R88E_HISR, 0x00000000); 3147 rtwn_write_4(sc, R88E_HIMR, 0x00000000); 3148 rtwn_write_4(sc, R88E_HIMRE, 0x00000000); 3149 if (sc->chip & RTWN_CHIP_USB) { 3150 rtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3151 rtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) & 3152 ~R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3153 } 3154 } else { 3155 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3156 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3157 } 3158 } 3159 3160 int 3161 rtwn_init(struct ifnet *ifp) 3162 { 3163 struct rtwn_softc *sc = ifp->if_softc; 3164 struct ieee80211com *ic = &sc->sc_ic; 3165 uint32_t reg; 3166 int i, error; 3167 3168 /* Init firmware commands ring. */ 3169 sc->fwcur = 0; 3170 3171 error = sc->sc_ops.alloc_buffers(sc->sc_ops.cookie); 3172 if (error) 3173 goto fail; 3174 3175 /* Power on adapter. */ 3176 error = sc->sc_ops.power_on(sc->sc_ops.cookie); 3177 if (error != 0) { 3178 printf("%s: could not power on adapter\n", 3179 sc->sc_pdev->dv_xname); 3180 goto fail; 3181 } 3182 3183 /* Initialize DMA. */ 3184 error = sc->sc_ops.dma_init(sc->sc_ops.cookie); 3185 if (error != 0) { 3186 printf("%s: could not initialize DMA\n", 3187 sc->sc_pdev->dv_xname); 3188 goto fail; 3189 } 3190 3191 /* Set info size in Rx descriptors (in 64-bit words). */ 3192 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3193 3194 if ((sc->chip & RTWN_CHIP_USB) && !(sc->chip & RTWN_CHIP_88F)) { 3195 /* Init interrupts. */ 3196 rtwn_enable_intr(sc); 3197 } else if (sc->chip & RTWN_CHIP_PCI) { 3198 rtwn_disable_intr(sc); 3199 } 3200 3201 /* Set MAC address. */ 3202 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); 3203 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3204 rtwn_write_1(sc, R92C_MACID + i, ic->ic_myaddr[i]); 3205 3206 /* Set initial network type. */ 3207 rtwn_set_nettype(sc, IEEE80211_M_MONITOR); 3208 3209 rtwn_rxfilter_init(sc); 3210 3211 reg = rtwn_read_4(sc, R92C_RRSR); 3212 if (sc->chip & RTWN_CHIP_USB) { 3213 reg = RW(reg, R92C_RRSR_RATE_BITMAP, 3214 R92C_RRSR_RATE_CCK_ONLY_1M); 3215 } else { 3216 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3217 } 3218 rtwn_write_4(sc, R92C_RRSR, reg); 3219 3220 /* Set short/long retry limits. */ 3221 if (sc->chip & RTWN_CHIP_USB) { 3222 rtwn_write_2(sc, R92C_RL, 3223 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3224 } else { 3225 rtwn_write_2(sc, R92C_RL, 3226 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3227 } 3228 3229 /* Initialize EDCA parameters. */ 3230 rtwn_edca_init(sc); 3231 3232 /* Set data and response automatic rate fallback retry counts. */ 3233 rtwn_rate_fallback_init(sc); 3234 3235 if (sc->chip & RTWN_CHIP_USB) { 3236 rtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3237 rtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3238 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3239 } else { 3240 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3241 } 3242 3243 /* Set ACK timeout. */ 3244 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3245 3246 /* Setup USB aggregation. */ 3247 if (sc->chip & RTWN_CHIP_USB) 3248 sc->sc_ops.aggr_init(sc->sc_ops.cookie); 3249 3250 /* Initialize beacon parameters. */ 3251 rtwn_write_2(sc, R92C_BCN_CTRL, 3252 (R92C_BCN_CTRL_DIS_TSF_UDT0 << 8) | R92C_BCN_CTRL_DIS_TSF_UDT0); 3253 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3254 if (!(sc->chip & RTWN_CHIP_88F)) 3255 rtwn_write_1(sc, R92C_DRVERLYINT, R92C_DRVERLYINT_INIT_TIME); 3256 rtwn_write_1(sc, R92C_BCNDMATIM, R92C_BCNDMATIM_INIT_TIME); 3257 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3258 3259 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) { 3260 /* Setup AMPDU aggregation. */ 3261 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3262 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3263 rtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3264 3265 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3266 } 3267 3268 if (sc->chip & RTWN_CHIP_PCI) { 3269 /* Reset H2C protection register. */ 3270 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3271 } 3272 3273 /* Load 8051 microcode. */ 3274 error = rtwn_load_firmware(sc); 3275 if (error != 0) 3276 goto fail; 3277 3278 /* Initialize MAC/BB/RF blocks. */ 3279 sc->sc_ops.mac_init(sc->sc_ops.cookie); 3280 sc->sc_ops.bb_init(sc->sc_ops.cookie); 3281 rtwn_rf_init(sc); 3282 3283 if (sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E)) { 3284 rtwn_write_2(sc, R92C_CR, 3285 rtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3286 R92C_CR_MACRXEN); 3287 } 3288 3289 /* Turn CCK and OFDM blocks on. */ 3290 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3291 reg |= R92C_RFMOD_CCK_EN; 3292 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3293 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3294 reg |= R92C_RFMOD_OFDM_EN; 3295 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3296 3297 /* Clear per-station keys table. */ 3298 rtwn_cam_init(sc); 3299 3300 /* Enable decryption / encryption. */ 3301 if (sc->chip & RTWN_CHIP_USB) { 3302 rtwn_write_2(sc, R92C_SECCFG, 3303 R92C_SECCFG_TXUCKEY_DEF | R92C_SECCFG_RXUCKEY_DEF | 3304 R92C_SECCFG_TXENC_ENA | R92C_SECCFG_RXENC_ENA | 3305 R92C_SECCFG_TXBCKEY_DEF | R92C_SECCFG_RXBCKEY_DEF); 3306 } 3307 3308 /* Enable hardware sequence numbering. */ 3309 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3310 3311 if (sc->chip & RTWN_CHIP_92E) { 3312 rtwn_write_1(sc, R92C_QUEUE_CTRL, 3313 rtwn_read_1(sc, R92C_QUEUE_CTRL) & ~0x08); 3314 } 3315 3316 /* Perform LO and IQ calibrations. */ 3317 rtwn_iq_calib(sc); 3318 /* Perform LC calibration. */ 3319 rtwn_lc_calib(sc); 3320 3321 /* Fix USB interference issue. */ 3322 if (sc->chip & RTWN_CHIP_USB) { 3323 if (!(sc->chip & 3324 (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) { 3325 rtwn_write_1(sc, 0xfe40, 0xe0); 3326 rtwn_write_1(sc, 0xfe41, 0x8d); 3327 rtwn_write_1(sc, 0xfe42, 0x80); 3328 3329 rtwn_pa_bias_init(sc); 3330 } 3331 } 3332 3333 /* Initialize GPIO setting. */ 3334 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3335 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3336 3337 /* Fix for lower temperature. */ 3338 if (!(sc->chip & (RTWN_CHIP_88E | RTWN_CHIP_88F | RTWN_CHIP_92E))) 3339 rtwn_write_1(sc, 0x15, 0xe9); 3340 3341 /* Set default channel. */ 3342 ic->ic_bss->ni_chan = ic->ic_ibss_chan; 3343 rtwn_set_chan(sc, ic->ic_ibss_chan, NULL); 3344 3345 if (sc->chip & RTWN_CHIP_PCI) 3346 rtwn_enable_intr(sc); 3347 3348 error = sc->sc_ops.init(sc->sc_ops.cookie); 3349 if (error) 3350 goto fail; 3351 3352 /* We're ready to go. */ 3353 ifq_clr_oactive(&ifp->if_snd); 3354 ifp->if_flags |= IFF_RUNNING; 3355 3356 if ((ic->ic_flags & IEEE80211_F_WEPON) && 3357 (sc->chip & RTWN_CHIP_USB)) { 3358 /* Install WEP keys. */ 3359 for (i = 0; i < IEEE80211_WEP_NKID; i++) 3360 ic->ic_set_key(ic, NULL, &ic->ic_nw_keys[i]); 3361 sc->sc_ops.wait_async(sc->sc_ops.cookie); 3362 } 3363 3364 if (ic->ic_opmode == IEEE80211_M_MONITOR) 3365 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 3366 else 3367 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 3368 return (0); 3369 fail: 3370 rtwn_stop(ifp); 3371 return (error); 3372 } 3373 3374 void 3375 rtwn_init_task(void *arg1) 3376 { 3377 struct rtwn_softc *sc = arg1; 3378 struct ifnet *ifp = &sc->sc_ic.ic_if; 3379 int s; 3380 3381 s = splnet(); 3382 while (sc->sc_flags & RTWN_FLAG_BUSY) 3383 tsleep_nsec(&sc->sc_flags, 0, "rtwnpwr", INFSLP); 3384 sc->sc_flags |= RTWN_FLAG_BUSY; 3385 3386 rtwn_stop(ifp); 3387 3388 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == IFF_UP) 3389 rtwn_init(ifp); 3390 3391 sc->sc_flags &= ~RTWN_FLAG_BUSY; 3392 wakeup(&sc->sc_flags); 3393 splx(s); 3394 } 3395 3396 void 3397 rtwn_stop(struct ifnet *ifp) 3398 { 3399 struct rtwn_softc *sc = ifp->if_softc; 3400 struct ieee80211com *ic = &sc->sc_ic; 3401 int s; 3402 3403 sc->sc_tx_timer = 0; 3404 ifp->if_timer = 0; 3405 ifp->if_flags &= ~IFF_RUNNING; 3406 ifq_clr_oactive(&ifp->if_snd); 3407 3408 s = splnet(); 3409 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 3410 splx(s); 3411 3412 sc->sc_ops.wait_async(sc->sc_ops.cookie); 3413 3414 s = splnet(); 3415 3416 sc->sc_ops.cancel_scan(sc->sc_ops.cookie); 3417 sc->sc_ops.cancel_calib(sc->sc_ops.cookie); 3418 3419 task_del(systq, &sc->init_task); 3420 3421 splx(s); 3422 3423 sc->sc_ops.stop(sc->sc_ops.cookie); 3424 } 3425