xref: /netbsd-src/sys/arch/atari/pci/pci_tseng.c (revision 2a84159ada57dac1a3a322c289d36b976db1a473)
1 /*	$NetBSD: pci_tseng.c,v 1.14 2023/01/06 10:28:28 tsutsui Exp $	*/
2 
3 /*
4  * Copyright (c) 1999 Leo Weppelman.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: pci_tseng.c,v 1.14 2023/01/06 10:28:28 tsutsui Exp $");
29 
30 #include <sys/param.h>
31 #include <sys/queue.h>
32 #include <sys/systm.h>
33 #include <dev/pci/pcireg.h>
34 #include <dev/pci/pcivar.h>
35 #include <dev/pci/pcidevs.h>
36 #include <atari/pci/pci_vga.h>
37 #include <atari/dev/grf_etreg.h>
38 
39 #define PCI_LINMEMBASE	0x0e000000
40 #define PCI_IOBASE	0x800
41 
42 static void et6000_init(volatile uint8_t *, uint8_t *, int);
43 
44 /*
45  * Use tables for the card init...
46  */
47 static const uint8_t seq_tab[] = {
48 	0x03, 0x01, 0x03, 0x00, 0x02, 0x00, 0x00, 0xb4
49 };
50 
51 static const uint8_t gfx_tab[] = {
52 	0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x0f, 0xff
53 };
54 
55 static const uint8_t attr_tab[] = {
56 	0x0a, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00
57 };
58 
59 static const uint8_t crt_tab[] = {
60 	0x60, 0x53, 0x4f, 0x94, 0x56, 0x05, 0xc1, 0x1f,
61 	0x00, 0x4f, 0x00, 0x0f, 0x00, 0x00, 0x07, 0x80,
62 	0x98, 0x3d, 0x8f, 0x28, 0x0f, 0x8f, 0xc2, 0xa3,
63 	0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
64 	0x00, 0x00, 0x00, 0x00, 0x56, 0x00, 0x00, 0x00,
65 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
66 #ifdef ET4000_HAS_2MB_MEM
67 	0x00, 0x80, 0xa0, 0x00, 0x00, 0x10, 0x03, 0x89,		/* 2 MB video memory */
68 #else
69 	0x00, 0x80, 0x28, 0x00, 0x00, 0x10, 0x43, 0x09,		/* 1 MB video memory */
70 #endif
71 	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
72 };
73 
74 static const uint8_t ras_cas_tab[] = {
75 	0x11, 0x14, 0x15
76 };
77 
78 void
tseng_init(pci_chipset_tag_t pc,pcitag_t tag,int id,volatile uint8_t * ba,uint8_t * fb)79 tseng_init(pci_chipset_tag_t pc, pcitag_t tag, int id, volatile uint8_t *ba,
80     uint8_t *fb)
81 {
82 	int i, j;
83 	int is_et6000 = 0;
84 	uint32_t csr;
85 
86 	is_et6000 = (id ==  PCI_PRODUCT_TSENG_ET6000) ? 1 : 0;
87 
88 	/* Turn on the card */
89 	pci_conf_write(pc, tag, PCI_MAPREG_START, PCI_LINMEMBASE);
90 	if (is_et6000)
91 		pci_conf_write(pc, tag, PCI_MAPREG_START + 4,
92 		    PCI_IOBASE | PCI_MAPREG_TYPE_IO);
93 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
94 	csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
95 	csr |= PCI_COMMAND_MASTER_ENABLE;
96 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
97 
98 	if (is_et6000) {
99 		/*
100 		 * The et6[01]000 cards have MDRAM chips. The
101 		 * timing to those chips is not properly initialized
102 		 * by the card on init. The way to determine the
103 		 * values is not documented either :-( So that's why
104 		 * all this mess below (and in et6000_init()....
105 		 */
106 		for (i = 0; i < sizeof(ras_cas_tab); i++) {
107 			et6000_init(ba, fb, i);
108 			for (j = 0; j < 32; j++)
109 				fb[j] = j;
110 			for (j = 0; j < 32; j++)
111 				if (fb[j] != j)
112 					break;
113 			if (j == 32)
114 				break;
115 		}
116 	}
117 
118 	vgaw(ba, GREG_MISC_OUTPUT_W,      0x63);
119 	vgaw(ba, GREG_VIDEOSYSENABLE,     0x01);
120 	WCrt(ba, 0x17               ,     0x00); /* color */
121 	WCrt(ba, 0x11               ,     0x00); /* color */
122 	vgaw(ba, VDAC_MASK          ,     0xff);
123 	WSeq(ba, SEQ_ID_RESET       ,     0x00);
124 	vgaw(ba, GREG_HERCULESCOMPAT,     0x03);
125 	vgaw(ba, GREG_DISPMODECONTROL,    0xa0);
126 
127 	/* Load sequencer */
128 	for (i = 1; i < 8; i++)
129 		WSeq(ba, i, seq_tab[i]);
130 	WSeq(ba, SEQ_ID_RESET       ,     0x03);
131 
132 	vgar(ba, VDAC_ADDRESS);	/* clear old state */
133 	vgar(ba, VDAC_MASK);
134 	vgar(ba, VDAC_MASK);
135 	vgar(ba, VDAC_MASK);
136 	vgar(ba, VDAC_MASK);
137 	vgaw(ba, VDAC_MASK, 0);		/* set to palette */
138 	vgar(ba, VDAC_ADDRESS);		/* clear state */
139 	vgaw(ba, VDAC_MASK, 0xff);
140 
141 	/*
142 	 * Make sure we're allowed to write all crt-registers
143 	 */
144 	WCrt(ba, CRT_ID_END_VER_RETR, (RCrt(ba, CRT_ID_END_VER_RETR) & 0x7f));
145 
146 	/* CRT registers */
147 	for (i = 0; i < 0x3e; i++)
148 		WCrt(ba, i, crt_tab[i]);
149 
150 	/* GCT registers */
151 	for (i = 0; i < 0x09; i++)
152 		WGfx(ba, i, gfx_tab[i]);
153 
154 	for (i = 0; i < 0x10; i++)
155 		WAttr(ba, i, i);
156 	for (; i < 0x18; i++)
157 		WAttr(ba, i, attr_tab[i - 0x10]);
158 	WAttr(ba, 0x20, 0);
159 }
160 
161 /*
162  * Initialize the et6000 specific (PCI) registers. Try to do it like the
163  * video-bios would have done it, so things like Xservers get what they
164  * expect. Most info was kindly provided by Koen Gadeyne.
165  */
166 
167 static void
et6000_init(volatile uint8_t * ba,uint8_t * fb,int iter)168 et6000_init(volatile uint8_t *ba, uint8_t *fb, int iter)
169 {
170 	int		i;
171 	uint8_t		dac_tab[] = { 0x7d,0x67, 0x5d,0x64, 0x56,0x63,
172 				      0x28,0x22, 0x79,0x49, 0x6f,0x47,
173 				      0x28,0x41, 0x6b,0x44, 0x00,0x00,
174 				      0x00,0x00, 0x5d,0x25, 0x00,0x00,
175 				      0x00,0x00, 0x00,0x96 };
176 
177 	ba += 0x800;
178 
179 	ba[0x40] = 0x06;	/* Use standard vga addressing		*/
180 	ba[0x41] = 0x2a;	/* Performance control			*/
181 	ba[0x43] = 0x02;	/* XCLK/SCLK config			*/
182 	ba[0x44] = ras_cas_tab[iter];	/* RAS/CAS config		*/
183 	ba[0x46] = 0x00;	/* CRT display feature			*/
184 	ba[0x47] = 0x10;
185 	ba[0x58] = 0x00;	/* Video Control 1			*/
186 	ba[0x59] = 0x04;	/* Video Control 2			*/
187 
188 	/*
189 	 * Setup a 'standard' CLKDAC
190 	 */
191 	ba[0x42] = 0x00;	/* MCLK == CLK0 */
192 	ba[0x67] = 0x00;	/* Start filling from dac-reg 0 and up... */
193 	for (i = 0; i < 0x16; i++)
194 		ba[0x69] = dac_tab[i];
195 
196 	if (ba[8] == 0x70) { /* et6100, right? */
197 		volatile uint8_t *ma = (volatile uint8_t *)fb;
198 		uint8_t bv;
199 
200 		/*
201 		 * XXX Black magic to get the bloody MDRAM's to function...
202 		 * XXX _Only_ tested on my card! [leo]
203 		 */
204 		bv = ba[45];
205 		ba[0x45] = bv | 0x40;	/* Reset MDRAM's		*/
206 		ba[0x45] = bv | 0x70;	/* Program latency value	*/
207 		ma[0x0] = 0;		/* Yeah, right :-(		*/
208 		ba[0x45] = bv;		/* Back to normal		*/
209 	}
210 }
211