1 /* $NetBSD: tr2a.c,v 1.6 2015/06/23 21:00:23 matt Exp $ */
2
3 /*-
4 * Copyright (c) 2004, 2005 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: tr2a.c,v 1.6 2015/06/23 21:00:23 matt Exp $");
34
35 #define __INTR_PRIVATE
36 #include "fb_sbdio.h"
37 #include "kbms_sbdio.h"
38 #include "zsc_sbdio.h"
39 #include "ewskbd_zsc.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/conf.h>
44 #include <sys/device.h>
45 #include <sys/cpu.h>
46
47 #include <uvm/uvm_extern.h>
48
49 #include <mips/locore.h>
50 #include <mips/cache.h> /* Set L2-cache size */
51
52 #include <machine/autoconf.h>
53 #include <machine/sbdvar.h>
54 #define _SBD_TR2A_PRIVATE
55 #include <machine/sbd_tr2a.h>
56 #include <machine/z8530var.h>
57
58 #include <ews4800mips/ews4800mips/cons_machdep.h>
59
60 #include <dev/cons.h>
61
62 SBD_DECL(tr2a);
63
64 /* EWS4800/360 bus list */
65 static const char * const tr2a_mainbusdevs[] = {
66 "sbdio",
67 #ifdef notyet
68 "apbus",
69 "vme",
70 #endif
71 NULL
72 };
73
74 /* EWS4800/360 System board device list */
75 static const struct sbdiodevdesc tr2a_sbdiodevs[] = {
76 /* name addr1 addr2 irq flags */
77 { "lance", 0x1e400000, -1, 0, 0x0000 }, /* AM79C90 */
78 { "zsc", 0x1e440000, -1, 4, 0x0000 }, /* Z85230 */
79 #if NEWSKBD_ZSC > 0
80 { "zsc", 0x1e480000, -1, 9, 0x0001 }, /* Z85230 */
81 #else
82 { "zkbms", 0x1e480000, -1, 9, 0x0000 }, /* Z85230 */
83 #endif
84 { "mkclock", 0x1e490000, -1, -1, 0x0001 }, /* MK48T18 */
85 { "osiop", 0x1e500000, -1, 6, 0x0001 }, /* 53C710 */
86 { "osiop", 0x1e510000, -1, 10, 0x0001 }, /* 53C710 */
87 /* 0xbe46 MUSE */
88 /* 0xbe42 FDC */
89 /* 0xbe43 LPT */
90 /* 0xbe40-0xbe47 LR? */
91 /* 0xbe80 LR4370-> APbus,VME */
92 /* 72069 */
93 /* XXX: maybe fb should be attached at independent bus */
94 { "fb", 0xf0000000, 0xf5f00000, -1, 0x0001 },
95 { NULL, -1, -1, -1, 0x0000 } /* terminate */
96 };
97
98 static const struct sbdiodevdesc tr2a_sbdiodevs_nofb[] = {
99 /* name addr1 addr2 irq flags */
100 { "lance", 0x1e400000, -1, 0, 0x0000 }, /* AM79C90 */
101 { "zsc", 0x1e440000, -1, 4, 0x0000 }, /* Z85230 */
102 #if NEWSKBD_ZSC > 0
103 { "zsc", 0x1e480000, -1, 9, 0x0001 }, /* Z85230 */
104 #else
105 { "zkbms", 0x1e480000, -1, 9, 0x0000 }, /* Z85230 */
106 #endif
107 { "mkclock", 0x1e490000, -1, -1, 0x0001 }, /* MK48T18 */
108 { "osiop", 0x1e500000, -1, 6, 0x0001 }, /* 53C710 */
109 { "osiop", 0x1e510000, -1, 10, 0x0001 }, /* 53C710 */
110 { NULL, -1, -1, -1, 0x0000 } /* terminate */
111 };
112
113 void
tr2a_init(void)114 tr2a_init(void)
115 {
116 char model_name[32];
117 int have_fb_sbdio;
118
119 have_fb_sbdio = 0;
120
121 platform.machine = MACHINE_TR2A;
122 strlcpy(model_name, SBD_INFO->model_name, sizeof(model_name));
123 if (model_name[0] == '\0') {
124 if (SBD_INFO->model == 0x101f)
125 strcpy(model_name, "EWS4800/360AD");
126 have_fb_sbdio = 1;
127 }
128
129 if (strcmp(model_name, "EWS4800/360ADII") == 0) {
130 platform.cpu_clock = 200000000;
131 have_fb_sbdio = 1;
132 } else if (strcmp(model_name, "EWS4800/360AD") == 0) {
133 platform.cpu_clock = 150000000;
134 have_fb_sbdio = 1;
135 } else if (strcmp(model_name, "EWS4800/360SX") == 0) {
136 /* framebuffer is on APbus */
137 platform.cpu_clock = 200000000;
138 } else if (strcmp(model_name, "EWS4800/360EX") == 0) {
139 /* untested */
140 platform.cpu_clock = 200000000;
141 } else if (strcmp(model_name, "EWS4800/360") == 0) {
142 /* untested */
143 platform.cpu_clock = 133333333;
144 } else {
145 printf("UNKNOWN model %s\n", model_name);
146 platform.cpu_clock = 133333333;
147 }
148
149 curcpu()->ci_cpu_freq = platform.cpu_clock;
150
151 snprintf(platform.name, sizeof(platform.name), "%s (TR2A)", model_name);
152 platform.mainbusdevs = tr2a_mainbusdevs;
153 platform.sbdiodevs = tr2a_sbdiodevs_nofb;
154 if (have_fb_sbdio)
155 platform.sbdiodevs = tr2a_sbdiodevs;
156
157 ipl_sr_map = tr2a_ipl_sr_map;
158
159 kseg2iobufsize = 0x02000000; /* 32MB for APbus and framebuffer */
160
161 /* Register system-board specific ops. */
162 _SBD_OPS_REGISTER_ALL(tr2a);
163
164 mips_locore_jumpvec.ljv_wbflush = platform.wbflush;
165 }
166
167 int
tr2a_ipl_bootdev(void)168 tr2a_ipl_bootdev(void)
169 {
170
171 return *NVSRAM_BOOTDEV;
172 }
173
174 void
tr2a_cache_config(void)175 tr2a_cache_config(void)
176 {
177
178 mips_cache_info.mci_sdcache_size = 1024 * 1024; /* 1MB L2-cache */
179 }
180
181 void
tr2a_wbflush(void)182 tr2a_wbflush(void)
183 {
184
185 *(volatile uint32_t *)0xbe492010;
186 *(volatile uint32_t *)0xbe492010;
187 *(volatile uint32_t *)0xbe492010;
188 *(volatile uint32_t *)0xbe492010;
189
190 #if 0 /* notyet */
191 if (has_apbus)
192 *(volatile uint32_t *)0xbe806000;
193 #endif
194 }
195
196 void
tr2a_mem_init(void * kernstart,void * kernend)197 tr2a_mem_init(void *kernstart, void *kernend)
198 {
199
200 sbd_memcluster_setup(kernstart, kernend);
201 #if 0
202 sbd_memcluster_check();
203 #endif
204 }
205
206 void
tr2a_consinit(void)207 tr2a_consinit(void)
208 {
209 extern struct consdev consdev_zs_sbdio;
210 extern const struct cdevsw zstty_cdevsw;
211 extern int fb_sbdio_cnattach(uint32_t, uint32_t, int);
212 extern void kbd_sbdio_cnattach(uint32_t, uint32_t);
213 extern void ewskbd_zsc_cnattach(uint32_t, uint32_t, int);
214
215 switch (*NVSRAM_CONSTYPE) {
216 #if NFB_SBDIO > 0
217 case 0x80:
218 /* on-board FB on 360AD, 360ADII */
219 cons.type = CONS_FB_KSEG2;
220 if (fb_sbdio_cnattach(TR2A_GAFB_ADDR, TR2A_GAREG_ADDR, 0x0001))
221 break;
222 #if NEWSKBD_ZSC > 0
223 ewskbd_zsc_cnattach(TR2A_KBMS_BASE, TR2A_KBMS_BASE + 4,
224 4915200);
225 #else
226 #if NKBMS_SBDIO > 0
227 kbd_sbdio_cnattach(TR2A_KBMS_BASE, TR2A_KBMS_BASE + 4);
228 #endif
229 #endif
230 return;
231 #endif
232 #if NZSC_SBDIO > 0
233 case 0x01:
234 /* sio 1 (zs channel A) */
235 cons.type = CONS_SIO1;
236 zs_consaddr = (void *)(TR2A_SIO_BASE + 8);
237 cn_tab = &consdev_zs_sbdio;
238 cn_tab->cn_pri = CN_REMOTE;
239 cn_tab->cn_dev =
240 makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
241 (*cn_tab->cn_init)(cn_tab);
242 return;
243 case 0x02:
244 /* sio 2 (zs channel B) */
245 cons.type = CONS_SIO2;
246 zs_consaddr = (void *)(TR2A_SIO_BASE + 0);
247 cn_tab = &consdev_zs_sbdio;
248 cn_tab->cn_pri = CN_REMOTE;
249 cn_tab->cn_dev =
250 makedev(cdevsw_lookup_major(&zstty_cdevsw), 1);
251 (*cn_tab->cn_init)(cn_tab);
252 return;
253 #endif
254 default:
255 break;
256 }
257 rom_cons_init(); /* XXX */
258 }
259
260 void
tr2a_reboot(void)261 tr2a_reboot(void)
262 {
263
264 *SOFTRESET_FLAG |= 0x80000000;
265 *SOFTRESET_REG = 0x01;
266 *(uint8_t *)0xbfbffffc = 0xff;
267 for (;;)
268 ;
269 /*NOTREACHED */
270 }
271
272 void
tr2a_poweroff(void)273 tr2a_poweroff(void)
274 {
275
276 for (;;)
277 *POWEROFF_REG = 1;
278 /* NOTREACHED */
279 }
280
281 void
tr2a_ether_addr(uint8_t * p)282 tr2a_ether_addr(uint8_t *p)
283 {
284 int i;
285
286 for (i = 0; i < 6; i++)
287 p[i] = *(uint8_t *)(NVSRAM_ETHERADDR + i * 4);
288 }
289