xref: /netbsd-src/sys/arch/riscv/riscv/clock_machdep.c (revision 0ad349337a874f932507463a034e8710784222b7)
1 /*	$NetBSD: clock_machdep.c,v 1.9 2024/08/04 08:16:25 skrll Exp $	*/
2 
3 /*-
4  * Copyright (c) 2014 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Matt Thomas of 3am Software Foundry.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 
34 __RCSID("$NetBSD: clock_machdep.c,v 1.9 2024/08/04 08:16:25 skrll Exp $");
35 
36 #include <sys/param.h>
37 #include <sys/cpu.h>
38 #include <sys/device.h>
39 #include <sys/systm.h>
40 #include <sys/timetc.h>
41 
42 #include <machine/machdep.h>
43 #include <machine/sbi.h>
44 #include <machine/sysreg.h>
45 
46 static void (*_riscv_timer_init)(void) = riscv_timer_init;
47 
48 static uint32_t timer_frequency;
49 static uint32_t	timer_ticks_per_hz;
50 static uint32_t timer_ticks_per_usec;
51 
52 static u_int
53 timer_get_timecount(struct timecounter *tc)
54 {
55 	return csr_time_read();
56 }
57 
58 static struct timecounter tc =  {
59 	.tc_get_timecount = timer_get_timecount,
60 	.tc_counter_mask = ~0u,
61 	.tc_name = "riscv",
62 	.tc_quality = 100,
63 };
64 
65 
66 void
67 riscv_timer_frequency_set(uint32_t freq)
68 {
69 	timer_frequency = freq;
70 	timer_ticks_per_hz = freq / hz;
71 	timer_ticks_per_usec = freq / 1000000;
72 }
73 
74 uint32_t
75 riscv_timer_frequency_get(void)
76 {
77 	return timer_frequency;
78 }
79 
80 void
81 riscv_timer_register(void (*timerfn)(void))
82 {
83 	if (_riscv_timer_init != NULL) {
84 #ifdef DIAGNOSTIC
85 		aprint_verbose("%s: timer already registered\n", __func__);
86 #endif
87 	}
88 	_riscv_timer_init = timerfn;
89 }
90 
91 void
92 riscv_timer_init(void)
93 {
94 	struct cpu_info * const ci = curcpu();
95 
96 	evcnt_attach_dynamic(&ci->ci_ev_timer, EVCNT_TYPE_INTR,
97 	    NULL, device_xname(ci->ci_dev), "timer");
98 
99 	ci->ci_lastintr = csr_time_read();
100 	uint64_t next = ci->ci_lastintr + timer_ticks_per_hz;
101 	ci->ci_lastintr_scheduled = next;
102 
103 	sbi_set_timer(next);		/* schedule next timer interrupt */
104 	csr_sie_set(SIE_STIE);		/* enable supervisor timer intr */
105 
106 	if (cpu_index(ci) == 0) {
107 		tc.tc_frequency = timer_frequency;
108 		tc_init(&tc);
109 	}
110 }
111 
112 
113 int
114 riscv_timer_intr(void *arg)
115 {
116 	struct cpu_info * const ci = curcpu();
117 	struct clockframe * const cf = arg;
118 
119 	csr_sip_clear(SIP_STIP);	/* clean pending interrupt status */
120 
121 	const uint64_t now = csr_time_read();
122 
123 	ci->ci_lastintr = now;
124 	ci->ci_ev_timer.ev_count++;
125 
126 	ci->ci_lastintr_scheduled += timer_ticks_per_hz;
127 	while (__predict_false(ci->ci_lastintr_scheduled < now)) {
128 		ci->ci_lastintr_scheduled += timer_ticks_per_hz;
129 		/* XXX count missed timer interrupts */
130 	}
131 	sbi_set_timer(ci->ci_lastintr_scheduled);
132 
133 	hardclock(cf);
134 
135 	return 1;
136 }
137 
138 
139 void
140 cpu_initclocks(void)
141 {
142 	if (_riscv_timer_init == NULL)
143 		panic("cpu_initclocks: no timer registered");
144 	_riscv_timer_init();
145 }
146 
147 
148 void
149 setstatclockrate(int newhz)
150 {
151 }
152 
153 void
154 delay(unsigned long us)
155 {
156 	const uint64_t ticks = (uint64_t)us * timer_ticks_per_usec;
157 	const uint64_t finish = csr_time_read() + ticks;
158 
159 	while (csr_time_read() < finish) {
160 		/* spin, baby spin */
161 	}
162 }
163