xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/amdgpu_vf_error.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: amdgpu_vf_error.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2017 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  */
25 
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vf_error.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
28 
29 #include "amdgpu.h"
30 #include "amdgpu_vf_error.h"
31 #include "mxgpu_ai.h"
32 
amdgpu_vf_error_put(struct amdgpu_device * adev,uint16_t sub_error_code,uint16_t error_flags,uint64_t error_data)33 void amdgpu_vf_error_put(struct amdgpu_device *adev,
34 			 uint16_t sub_error_code,
35 			 uint16_t error_flags,
36 			 uint64_t error_data)
37 {
38 	int index;
39 	uint16_t error_code;
40 
41 	if (!amdgpu_sriov_vf(adev))
42 		return;
43 
44 	error_code = AMDGIM_ERROR_CODE(AMDGIM_ERROR_CATEGORY_VF, sub_error_code);
45 
46 	mutex_lock(&adev->virt.vf_errors.lock);
47 	index = adev->virt.vf_errors.write_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
48 	adev->virt.vf_errors.code [index] = error_code;
49 	adev->virt.vf_errors.flags [index] = error_flags;
50 	adev->virt.vf_errors.data [index] = error_data;
51 	adev->virt.vf_errors.write_count ++;
52 	mutex_unlock(&adev->virt.vf_errors.lock);
53 }
54 
55 
amdgpu_vf_error_trans_all(struct amdgpu_device * adev)56 void amdgpu_vf_error_trans_all(struct amdgpu_device *adev)
57 {
58 	/* u32 pf2vf_flags = 0; */
59 	u32 data1, data2, data3;
60 	int index;
61 
62 	if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) ||
63 	    (!adev->virt.ops) || (!adev->virt.ops->trans_msg)) {
64 		return;
65 	}
66 /*
67  	TODO: Enable these code when pv2vf_info is merged
68 	AMDGPU_FW_VRAM_PF2VF_READ (adev, feature_flags, &pf2vf_flags);
69 	if (!(pf2vf_flags & AMDGIM_FEATURE_ERROR_LOG_COLLECT)) {
70 		return;
71 	}
72 */
73 
74 	mutex_lock(&adev->virt.vf_errors.lock);
75 	/* The errors are overlay of array, correct read_count as full. */
76 	if (adev->virt.vf_errors.write_count - adev->virt.vf_errors.read_count > AMDGPU_VF_ERROR_ENTRY_SIZE) {
77 		adev->virt.vf_errors.read_count = adev->virt.vf_errors.write_count - AMDGPU_VF_ERROR_ENTRY_SIZE;
78 	}
79 
80 	while (adev->virt.vf_errors.read_count < adev->virt.vf_errors.write_count) {
81 		index =adev->virt.vf_errors.read_count % AMDGPU_VF_ERROR_ENTRY_SIZE;
82 		data1 = AMDGIM_ERROR_CODE_FLAGS_TO_MAILBOX(adev->virt.vf_errors.code[index],
83 							   adev->virt.vf_errors.flags[index]);
84 		data2 = adev->virt.vf_errors.data[index] & 0xFFFFFFFF;
85 		data3 = (adev->virt.vf_errors.data[index] >> 32) & 0xFFFFFFFF;
86 
87 		adev->virt.ops->trans_msg(adev, IDH_LOG_VF_ERROR, data1, data2, data3);
88 		adev->virt.vf_errors.read_count ++;
89 	}
90 	mutex_unlock(&adev->virt.vf_errors.lock);
91 }
92