1 //===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the AVR implementation of the TargetRegisterInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "AVRRegisterInfo.h" 14 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 19 #include "llvm/CodeGen/TargetFrameLowering.h" 20 21 #include "AVR.h" 22 #include "AVRInstrInfo.h" 23 #include "AVRMachineFunctionInfo.h" 24 #include "AVRTargetMachine.h" 25 #include "MCTargetDesc/AVRMCTargetDesc.h" 26 27 #define GET_REGINFO_TARGET_DESC 28 #include "AVRGenRegisterInfo.inc" 29 30 namespace llvm { 31 32 AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {} 33 34 const uint16_t * 35 AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 36 const AVRMachineFunctionInfo *AFI = MF->getInfo<AVRMachineFunctionInfo>(); 37 const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>(); 38 if (STI.hasTinyEncoding()) 39 return AFI->isInterruptOrSignalHandler() ? CSR_InterruptsTiny_SaveList 40 : CSR_NormalTiny_SaveList; 41 else 42 return AFI->isInterruptOrSignalHandler() ? CSR_Interrupts_SaveList 43 : CSR_Normal_SaveList; 44 } 45 46 const uint32_t * 47 AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 48 CallingConv::ID CC) const { 49 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>(); 50 return STI.hasTinyEncoding() ? CSR_NormalTiny_RegMask : CSR_Normal_RegMask; 51 } 52 53 BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 54 BitVector Reserved(getNumRegs()); 55 56 // Reserve the intermediate result registers r1 and r2 57 // The result of instructions like 'mul' is always stored here. 58 // R0/R1/R1R0 are always reserved on both avr and avrtiny. 59 Reserved.set(AVR::R0); 60 Reserved.set(AVR::R1); 61 Reserved.set(AVR::R1R0); 62 63 // Reserve the stack pointer. 64 Reserved.set(AVR::SPL); 65 Reserved.set(AVR::SPH); 66 Reserved.set(AVR::SP); 67 68 // Reserve R2~R17 only on avrtiny. 69 if (MF.getSubtarget<AVRSubtarget>().hasTinyEncoding()) { 70 // Reserve 8-bit registers R2~R15, Rtmp(R16) and Zero(R17). 71 for (unsigned Reg = AVR::R2; Reg <= AVR::R17; Reg++) 72 Reserved.set(Reg); 73 // Reserve 16-bit registers R3R2~R18R17. 74 for (unsigned Reg = AVR::R3R2; Reg <= AVR::R18R17; Reg++) 75 Reserved.set(Reg); 76 } 77 78 // We tenatively reserve the frame pointer register r29:r28 because the 79 // function may require one, but we cannot tell until register allocation 80 // is complete, which can be too late. 81 // 82 // Instead we just unconditionally reserve the Y register. 83 // 84 // TODO: Write a pass to enumerate functions which reserved the Y register 85 // but didn't end up needing a frame pointer. In these, we can 86 // convert one or two of the spills inside to use the Y register. 87 Reserved.set(AVR::R28); 88 Reserved.set(AVR::R29); 89 Reserved.set(AVR::R29R28); 90 91 return Reserved; 92 } 93 94 const TargetRegisterClass * 95 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 96 const MachineFunction &MF) const { 97 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); 98 if (TRI->isTypeLegalForClass(*RC, MVT::i16)) { 99 return &AVR::DREGSRegClass; 100 } 101 102 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) { 103 return &AVR::GPR8RegClass; 104 } 105 106 llvm_unreachable("Invalid register size"); 107 } 108 109 /// Fold a frame offset shared between two add instructions into a single one. 110 static void foldFrameOffset(MachineBasicBlock::iterator &II, int &Offset, 111 Register DstReg) { 112 MachineInstr &MI = *II; 113 int Opcode = MI.getOpcode(); 114 115 // Don't bother trying if the next instruction is not an add or a sub. 116 if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) { 117 return; 118 } 119 120 // Check that DstReg matches with next instruction, otherwise the instruction 121 // is not related to stack address manipulation. 122 if (DstReg != MI.getOperand(0).getReg()) { 123 return; 124 } 125 126 // Add the offset in the next instruction to our offset. 127 switch (Opcode) { 128 case AVR::SUBIWRdK: 129 Offset += -MI.getOperand(2).getImm(); 130 break; 131 case AVR::ADIWRdK: 132 Offset += MI.getOperand(2).getImm(); 133 break; 134 } 135 136 // Finally remove the instruction. 137 II++; 138 MI.eraseFromParent(); 139 } 140 141 bool AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 142 int SPAdj, unsigned FIOperandNum, 143 RegScavenger *RS) const { 144 assert(SPAdj == 0 && "Unexpected SPAdj value"); 145 146 MachineInstr &MI = *II; 147 DebugLoc dl = MI.getDebugLoc(); 148 MachineBasicBlock &MBB = *MI.getParent(); 149 const MachineFunction &MF = *MBB.getParent(); 150 const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget(); 151 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo(); 152 const MachineFrameInfo &MFI = MF.getFrameInfo(); 153 const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering(); 154 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>(); 155 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 156 int Offset = MFI.getObjectOffset(FrameIndex); 157 158 // Add one to the offset because SP points to an empty slot. 159 Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1; 160 // Fold incoming offset. 161 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 162 163 // This is actually "load effective address" of the stack slot 164 // instruction. We have only two-address instructions, thus we need to 165 // expand it into move + add. 166 if (MI.getOpcode() == AVR::FRMIDX) { 167 Register DstReg = MI.getOperand(0).getReg(); 168 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer"); 169 170 // Copy the frame pointer. 171 if (STI.hasMOVW()) { 172 BuildMI(MBB, MI, dl, TII.get(AVR::MOVWRdRr), DstReg) 173 .addReg(AVR::R29R28); 174 } else { 175 Register DstLoReg, DstHiReg; 176 splitReg(DstReg, DstLoReg, DstHiReg); 177 BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstLoReg) 178 .addReg(AVR::R28); 179 BuildMI(MBB, MI, dl, TII.get(AVR::MOVRdRr), DstHiReg) 180 .addReg(AVR::R29); 181 } 182 183 assert(Offset > 0 && "Invalid offset"); 184 185 // We need to materialize the offset via an add instruction. 186 unsigned Opcode; 187 188 II++; // Skip over the FRMIDX instruction. 189 190 // Generally, to load a frame address two add instructions are emitted that 191 // could get folded into a single one: 192 // movw r31:r30, r29:r28 193 // adiw r31:r30, 29 194 // adiw r31:r30, 16 195 // to: 196 // movw r31:r30, r29:r28 197 // adiw r31:r30, 45 198 if (II != MBB.end()) 199 foldFrameOffset(II, Offset, DstReg); 200 201 // Select the best opcode based on DstReg and the offset size. 202 switch (DstReg) { 203 case AVR::R25R24: 204 case AVR::R27R26: 205 case AVR::R31R30: { 206 if (isUInt<6>(Offset) && STI.hasADDSUBIW()) { 207 Opcode = AVR::ADIWRdK; 208 break; 209 } 210 [[fallthrough]]; 211 } 212 default: { 213 // This opcode will get expanded into a pair of subi/sbci. 214 Opcode = AVR::SUBIWRdK; 215 Offset = -Offset; 216 break; 217 } 218 } 219 220 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg) 221 .addReg(DstReg, RegState::Kill) 222 .addImm(Offset); 223 New->getOperand(3).setIsDead(); 224 225 MI.eraseFromParent(); // remove FRMIDX 226 227 return false; 228 } 229 230 // On most AVRs, we can use an offset up to 62 for load/store with 231 // displacement (63 for byte values, 62 for word values). However, the 232 // "reduced tiny" cores don't support load/store with displacement. So for 233 // them, we force an offset of 0 meaning that any positive offset will require 234 // adjusting the frame pointer. 235 int MaxOffset = STI.hasTinyEncoding() ? 0 : 62; 236 237 // If the offset is too big we have to adjust and restore the frame pointer 238 // to materialize a valid load/store with displacement. 239 //: TODO: consider using only one adiw/sbiw chain for more than one frame 240 //: index 241 if (Offset > MaxOffset) { 242 unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK; 243 int AddOffset = Offset - MaxOffset; 244 245 // For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci. 246 if ((Offset - MaxOffset) > 63 || !STI.hasADDSUBIW()) { 247 AddOpc = AVR::SUBIWRdK; 248 SubOpc = AVR::SUBIWRdK; 249 AddOffset = -AddOffset; 250 } 251 252 // It is possible that the spiller places this frame instruction in between 253 // a compare and branch, invalidating the contents of SREG set by the 254 // compare instruction because of the add/sub pairs. Conservatively save and 255 // restore SREG before and after each add/sub pair. 256 BuildMI(MBB, II, dl, TII.get(AVR::INRdA), STI.getTmpRegister()) 257 .addImm(STI.getIORegSREG()); 258 259 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28) 260 .addReg(AVR::R29R28, RegState::Kill) 261 .addImm(AddOffset); 262 New->getOperand(3).setIsDead(); 263 264 // Restore SREG. 265 BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr)) 266 .addImm(STI.getIORegSREG()) 267 .addReg(STI.getTmpRegister(), RegState::Kill); 268 269 // No need to set SREG as dead here otherwise if the next instruction is a 270 // cond branch it will be using a dead register. 271 BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28) 272 .addReg(AVR::R29R28, RegState::Kill) 273 .addImm(Offset - MaxOffset); 274 275 Offset = MaxOffset; 276 } 277 278 MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false); 279 assert(isUInt<6>(Offset) && "Offset is out of range"); 280 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 281 return false; 282 } 283 284 Register AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 285 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 286 if (TFI->hasFP(MF)) { 287 // The Y pointer register 288 return AVR::R28; 289 } 290 291 return AVR::SP; 292 } 293 294 const TargetRegisterClass * 295 AVRRegisterInfo::getPointerRegClass(const MachineFunction &MF, 296 unsigned Kind) const { 297 // FIXME: Currently we're using avr-gcc as reference, so we restrict 298 // ptrs to Y and Z regs. Though avr-gcc has buggy implementation 299 // of memory constraint, so we can fix it and bit avr-gcc here ;-) 300 return &AVR::PTRDISPREGSRegClass; 301 } 302 303 void AVRRegisterInfo::splitReg(Register Reg, Register &LoReg, 304 Register &HiReg) const { 305 assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers"); 306 307 LoReg = getSubReg(Reg, AVR::sub_lo); 308 HiReg = getSubReg(Reg, AVR::sub_hi); 309 } 310 311 bool AVRRegisterInfo::shouldCoalesce( 312 MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, 313 const TargetRegisterClass *DstRC, unsigned DstSubReg, 314 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const { 315 if (this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { 316 return false; 317 } 318 319 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, 320 NewRC, LIS); 321 } 322 323 } // end of namespace llvm 324