1 /* $NetBSD: smu_v11_0_pptable.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 #ifndef SMU_11_0_PPTABLE_H 25 #define SMU_11_0_PPTABLE_H 26 27 28 #define SMU_11_0_TABLE_FORMAT_REVISION 12 29 30 //// POWERPLAYTABLE::ulPlatformCaps 31 #define SMU_11_0_PP_PLATFORM_CAP_POWERPLAY 0x1 32 #define SMU_11_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 33 #define SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC 0x4 34 #define SMU_11_0_PP_PLATFORM_CAP_BACO 0x8 35 #define SMU_11_0_PP_PLATFORM_CAP_MACO 0x10 36 #define SMU_11_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20 37 38 // SMU_11_0_PP_THERMALCONTROLLER - Thermal Controller Type 39 #define SMU_11_0_PP_THERMALCONTROLLER_NONE 0 40 41 #define SMU_11_0_PP_OVERDRIVE_VERSION 0x0800 42 #define SMU_11_0_PP_POWERSAVINGCLOCK_VERSION 0x0100 43 44 enum SMU_11_0_ODFEATURE_CAP { 45 SMU_11_0_ODCAP_GFXCLK_LIMITS = 0, 46 SMU_11_0_ODCAP_GFXCLK_CURVE, 47 SMU_11_0_ODCAP_UCLK_MAX, 48 SMU_11_0_ODCAP_POWER_LIMIT, 49 SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT, 50 SMU_11_0_ODCAP_FAN_SPEED_MIN, 51 SMU_11_0_ODCAP_TEMPERATURE_FAN, 52 SMU_11_0_ODCAP_TEMPERATURE_SYSTEM, 53 SMU_11_0_ODCAP_MEMORY_TIMING_TUNE, 54 SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL, 55 SMU_11_0_ODCAP_AUTO_UV_ENGINE, 56 SMU_11_0_ODCAP_AUTO_OC_ENGINE, 57 SMU_11_0_ODCAP_AUTO_OC_MEMORY, 58 SMU_11_0_ODCAP_FAN_CURVE, 59 SMU_11_0_ODCAP_COUNT, 60 }; 61 62 enum SMU_11_0_ODFEATURE_ID { 63 SMU_11_0_ODFEATURE_GFXCLK_LIMITS = 1 << SMU_11_0_ODCAP_GFXCLK_LIMITS, //GFXCLK Limit feature 64 SMU_11_0_ODFEATURE_GFXCLK_CURVE = 1 << SMU_11_0_ODCAP_GFXCLK_CURVE, //GFXCLK Curve feature 65 SMU_11_0_ODFEATURE_UCLK_MAX = 1 << SMU_11_0_ODCAP_UCLK_MAX, //UCLK Limit feature 66 SMU_11_0_ODFEATURE_POWER_LIMIT = 1 << SMU_11_0_ODCAP_POWER_LIMIT, //Power Limit feature 67 SMU_11_0_ODFEATURE_FAN_ACOUSTIC_LIMIT = 1 << SMU_11_0_ODCAP_FAN_ACOUSTIC_LIMIT, //Fan Acoustic RPM feature 68 SMU_11_0_ODFEATURE_FAN_SPEED_MIN = 1 << SMU_11_0_ODCAP_FAN_SPEED_MIN, //Minimum Fan Speed feature 69 SMU_11_0_ODFEATURE_TEMPERATURE_FAN = 1 << SMU_11_0_ODCAP_TEMPERATURE_FAN, //Fan Target Temperature Limit feature 70 SMU_11_0_ODFEATURE_TEMPERATURE_SYSTEM = 1 << SMU_11_0_ODCAP_TEMPERATURE_SYSTEM, //Operating Temperature Limit feature 71 SMU_11_0_ODFEATURE_MEMORY_TIMING_TUNE = 1 << SMU_11_0_ODCAP_MEMORY_TIMING_TUNE, //AC Timing Tuning feature 72 SMU_11_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_11_0_ODCAP_FAN_ZERO_RPM_CONTROL, //Zero RPM feature 73 SMU_11_0_ODFEATURE_AUTO_UV_ENGINE = 1 << SMU_11_0_ODCAP_AUTO_UV_ENGINE, //Auto Under Volt GFXCLK feature 74 SMU_11_0_ODFEATURE_AUTO_OC_ENGINE = 1 << SMU_11_0_ODCAP_AUTO_OC_ENGINE, //Auto Over Clock GFXCLK feature 75 SMU_11_0_ODFEATURE_AUTO_OC_MEMORY = 1 << SMU_11_0_ODCAP_AUTO_OC_MEMORY, //Auto Over Clock MCLK feature 76 SMU_11_0_ODFEATURE_FAN_CURVE = 1 << SMU_11_0_ODCAP_FAN_CURVE, //Fan Curve feature 77 SMU_11_0_ODFEATURE_COUNT = 14, 78 }; 79 #define SMU_11_0_MAX_ODFEATURE 32 //Maximum Number of OD Features 80 81 enum SMU_11_0_ODSETTING_ID { 82 SMU_11_0_ODSETTING_GFXCLKFMAX = 0, 83 SMU_11_0_ODSETTING_GFXCLKFMIN, 84 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, 85 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, 86 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, 87 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, 88 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, 89 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, 90 SMU_11_0_ODSETTING_UCLKFMAX, 91 SMU_11_0_ODSETTING_POWERPERCENTAGE, 92 SMU_11_0_ODSETTING_FANRPMMIN, 93 SMU_11_0_ODSETTING_FANRPMACOUSTICLIMIT, 94 SMU_11_0_ODSETTING_FANTARGETTEMPERATURE, 95 SMU_11_0_ODSETTING_OPERATINGTEMPMAX, 96 SMU_11_0_ODSETTING_ACTIMING, 97 SMU_11_0_ODSETTING_FAN_ZERO_RPM_CONTROL, 98 SMU_11_0_ODSETTING_AUTOUVENGINE, 99 SMU_11_0_ODSETTING_AUTOOCENGINE, 100 SMU_11_0_ODSETTING_AUTOOCMEMORY, 101 SMU_11_0_ODSETTING_COUNT, 102 }; 103 #define SMU_11_0_MAX_ODSETTING 32 //Maximum Number of ODSettings 104 105 struct smu_11_0_overdrive_table 106 { 107 uint8_t revision; //Revision = SMU_11_0_PP_OVERDRIVE_VERSION 108 uint8_t reserve[3]; //Zero filled field reserved for future use 109 uint32_t feature_count; //Total number of supported features 110 uint32_t setting_count; //Total number of supported settings 111 uint8_t cap[SMU_11_0_MAX_ODFEATURE]; //OD feature support flags 112 uint32_t max[SMU_11_0_MAX_ODSETTING]; //default maximum settings 113 uint32_t min[SMU_11_0_MAX_ODSETTING]; //default minimum settings 114 } __attribute__((packed)); 115 116 enum SMU_11_0_PPCLOCK_ID { 117 SMU_11_0_PPCLOCK_GFXCLK = 0, 118 SMU_11_0_PPCLOCK_VCLK, 119 SMU_11_0_PPCLOCK_DCLK, 120 SMU_11_0_PPCLOCK_ECLK, 121 SMU_11_0_PPCLOCK_SOCCLK, 122 SMU_11_0_PPCLOCK_UCLK, 123 SMU_11_0_PPCLOCK_DCEFCLK, 124 SMU_11_0_PPCLOCK_DISPCLK, 125 SMU_11_0_PPCLOCK_PIXCLK, 126 SMU_11_0_PPCLOCK_PHYCLK, 127 SMU_11_0_PPCLOCK_COUNT, 128 }; 129 #define SMU_11_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks 130 131 struct smu_11_0_power_saving_clock_table 132 { 133 uint8_t revision; //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION 134 uint8_t reserve[3]; //Zero filled field reserved for future use 135 uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT 136 uint32_t max[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz 137 uint32_t min[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz 138 } __attribute__((packed)); 139 140 struct smu_11_0_powerplay_table 141 { 142 struct atom_common_table_header header; 143 uint8_t table_revision; 144 uint16_t table_size; //Driver portion table size. The offset to smc_pptable including header size 145 uint32_t golden_pp_id; 146 uint32_t golden_revision; 147 uint16_t format_id; 148 uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps 149 150 uint8_t thermal_controller_type; //one of SMU_11_0_PP_THERMALCONTROLLER 151 152 uint16_t small_power_limit1; 153 uint16_t small_power_limit2; 154 uint16_t boost_power_limit; 155 uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning. 156 uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning. 157 uint16_t software_shutdown_temp; 158 159 uint16_t reserve[6]; //Zero filled field reserved for future use 160 161 struct smu_11_0_power_saving_clock_table power_saving_clock; 162 struct smu_11_0_overdrive_table overdrive_table; 163 164 #ifndef SMU_11_0_PARTIAL_PPTABLE 165 PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h 166 #endif 167 } __attribute__((packed)); 168 169 #endif 170