1 /* $NetBSD: siisata.c,v 1.7 2017/08/03 19:22:15 phx Exp $ */
2
3 /*-
4 * Copyright (c) 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Tohru Nishimura.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/param.h>
33
34 #include <lib/libsa/stand.h>
35
36 #include "globals.h"
37
38 /*
39 * - no vtophys() translation, vaddr_t == paddr_t.
40 */
41 #define CSR_READ_4(r) in32rb(r)
42 #define CSR_WRITE_4(r,v) out32rb(r,v)
43
44 static int satapresense(struct dkdev_ata *, int);
45
46 static uint32_t pciiobase = PCI_XIOBASE;
47
48 int sata_delay[4] = { 3, 3, 3, 3 }; /* drive power-up delay per channel */
49
50 int
siisata_match(unsigned tag,void * data)51 siisata_match(unsigned tag, void *data)
52 {
53 unsigned v;
54
55 v = pcicfgread(tag, PCI_ID_REG);
56 switch (v) {
57 case PCI_DEVICE(0x1095, 0x3112): /* SiI 3112 SATALink */
58 case PCI_DEVICE(0x1095, 0x3512): /* 3512 SATALink */
59 case PCI_DEVICE(0x1095, 0x3114): /* SiI 3114 SATALink */
60 return 1;
61 }
62 return 0;
63 }
64
65 void *
siisata_init(unsigned tag,void * data)66 siisata_init(unsigned tag, void *data)
67 {
68 unsigned idreg;
69 int n, nchan, retries/*waitforspinup*/;
70 struct dkdev_ata *l;
71
72 l = alloc(sizeof(struct dkdev_ata));
73 memset(l, 0, sizeof(struct dkdev_ata));
74 l->iobuf = allocaligned(512, 16);
75 l->tag = tag;
76
77 idreg = pcicfgread(tag, PCI_ID_REG);
78 l->bar[0] = pciiobase + (pcicfgread(tag, 0x10) &~ 01);
79 l->bar[1] = pciiobase + (pcicfgread(tag, 0x14) &~ 01);
80 l->bar[2] = pciiobase + (pcicfgread(tag, 0x18) &~ 01);
81 l->bar[3] = pciiobase + (pcicfgread(tag, 0x1c) &~ 01);
82 l->bar[4] = pciiobase + (pcicfgread(tag, 0x20) &~ 01);
83 l->bar[5] = pcicfgread(tag, 0x24) &~ 0x3ff;
84
85 if ((PCI_PRODUCT(idreg) & 0xf) == 0x2) {
86 /* 3112/3512 */
87 l->chan[0].cmd = l->bar[0];
88 l->chan[0].ctl = l->chan[0].alt = l->bar[1] | 02;
89 l->chan[0].dma = l->bar[4] + 0x0;
90 l->chan[1].cmd = l->bar[2];
91 l->chan[1].ctl = l->chan[1].alt = l->bar[3] | 02;
92 l->chan[1].dma = l->bar[4] + 0x8;
93 nchan = 2;
94 }
95 else {
96 /* 3114 - assume BA5 access is possible XXX */
97 l->chan[0].cmd = l->bar[5] + 0x080;
98 l->chan[0].ctl = l->chan[0].alt = (l->bar[5] + 0x088) | 02;
99 l->chan[1].cmd = l->bar[5] + 0x0c0;
100 l->chan[1].ctl = l->chan[1].alt = (l->bar[5] + 0x0c8) | 02;
101 l->chan[2].cmd = l->bar[5] + 0x280;
102 l->chan[2].ctl = l->chan[2].alt = (l->bar[5] + 0x288) | 02;
103 l->chan[3].cmd = l->bar[5] + 0x2c0;
104 l->chan[3].ctl = l->chan[3].alt = (l->bar[5] + 0x2c8) | 02;
105 nchan = 4;
106 }
107
108 /* configure PIO transfer mode */
109 pcicfgwrite(tag, 0x80, 0x00);
110 pcicfgwrite(tag, 0x84, 0x00);
111
112 for (n = 0; n < nchan; n++) {
113 l->presense[n] = satapresense(l, n);
114 if (l->presense[n] == 0) {
115 /* wait some seconds to power-up the drive */
116 for (retries = 0; retries < sata_delay[n]; retries++) {
117 wakeup_drive(l, n);
118 printf("Waiting %2d seconds for powering up "
119 "port %d.\r", sata_delay[n] - retries, n);
120 delay(1000 * 1000);
121 if ((l->presense[n] = satapresense(l, n)) != 0)
122 break;
123 }
124 putchar('\n');
125 if (l->presense[n] == 0) {
126 DPRINTF(("port %d not present\n", n));
127 continue;
128 } else {
129 /*
130 * XXX perform_atareset() does not work
131 * when the drive is not completely spun up?
132 * So insert another delay here.
133 */
134 printf("Waiting 15 seconds for port %d "
135 "to spin up.\n", n);
136 delay(15 * 1000 * 1000);
137 }
138 }
139 if (atachkpwr(l, n) != ATA_PWR_ACTIVE) {
140 /* drive is probably sleeping, wake it up */
141 for (retries = 0; retries < 20; retries++) {
142 wakeup_drive(l, n);
143 DPRINTF(("port %d spinning up...\n", n));
144 delay(1000 * 1000);
145 l->presense[n] = perform_atareset(l, n);
146 if (atachkpwr(l, n) == ATA_PWR_ACTIVE)
147 break;
148 }
149 } else {
150 /* check to see whether soft reset works */
151 DPRINTF(("port %d active\n", n));
152 for (retries = 0; retries < 20; retries++) {
153 l->presense[n] = perform_atareset(l, n);
154 if (l->presense[n] != 0)
155 break;
156 wakeup_drive(l, n);
157 DPRINTF(("port %d cold-starting...\n", n));
158 delay(1000 * 1000);
159 }
160 }
161
162 if (l->presense[n])
163 printf("port %d present\n", n);
164 }
165 return l;
166 }
167
168 static int
satapresense(struct dkdev_ata * l,int n)169 satapresense(struct dkdev_ata *l, int n)
170 {
171 #define VND_CH(n) (((n&02)<<8)+((n&01)<<7))
172 #define VND_SC(n) (0x100+VND_CH(n))
173 #define VND_SS(n) (0x104+VND_CH(n))
174
175 uint32_t sc = l->bar[5] + VND_SC(n);
176 uint32_t ss = l->bar[5] + VND_SS(n);
177 unsigned val;
178
179 val = (00 << 4) | (03 << 8); /* any speed, no pwrmgt */
180 CSR_WRITE_4(sc, val | 01); /* perform init */
181 delay(50 * 1000);
182 CSR_WRITE_4(sc, val);
183 delay(50 * 1000);
184 val = CSR_READ_4(ss); /* has completed */
185 return ((val & 03) == 03); /* active drive found */
186 }
187