1 /* $NetBSD: radeon_si_blit_shaders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Alex Deucher <alexander.deucher@amd.com> 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: radeon_si_blit_shaders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $"); 31 32 #include <linux/types.h> 33 #include <linux/bug.h> 34 #include <linux/kernel.h> 35 36 const u32 si_default_state[] = 37 { 38 0xc0066900, 39 0x00000000, 40 0x00000060, /* DB_RENDER_CONTROL */ 41 0x00000000, /* DB_COUNT_CONTROL */ 42 0x00000000, /* DB_DEPTH_VIEW */ 43 0x0000002a, /* DB_RENDER_OVERRIDE */ 44 0x00000000, /* DB_RENDER_OVERRIDE2 */ 45 0x00000000, /* DB_HTILE_DATA_BASE */ 46 47 0xc0046900, 48 0x00000008, 49 0x00000000, /* DB_DEPTH_BOUNDS_MIN */ 50 0x00000000, /* DB_DEPTH_BOUNDS_MAX */ 51 0x00000000, /* DB_STENCIL_CLEAR */ 52 0x00000000, /* DB_DEPTH_CLEAR */ 53 54 0xc0036900, 55 0x0000000f, 56 0x00000000, /* DB_DEPTH_INFO */ 57 0x00000000, /* DB_Z_INFO */ 58 0x00000000, /* DB_STENCIL_INFO */ 59 60 0xc0016900, 61 0x00000080, 62 0x00000000, /* PA_SC_WINDOW_OFFSET */ 63 64 0xc00d6900, 65 0x00000083, 66 0x0000ffff, /* PA_SC_CLIPRECT_RULE */ 67 0x00000000, /* PA_SC_CLIPRECT_0_TL */ 68 0x20002000, /* PA_SC_CLIPRECT_0_BR */ 69 0x00000000, 70 0x20002000, 71 0x00000000, 72 0x20002000, 73 0x00000000, 74 0x20002000, 75 0xaaaaaaaa, /* PA_SC_EDGERULE */ 76 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */ 77 0x0000000f, /* CB_TARGET_MASK */ 78 0x0000000f, /* CB_SHADER_MASK */ 79 80 0xc0226900, 81 0x00000094, 82 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ 83 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ 84 0x80000000, 85 0x20002000, 86 0x80000000, 87 0x20002000, 88 0x80000000, 89 0x20002000, 90 0x80000000, 91 0x20002000, 92 0x80000000, 93 0x20002000, 94 0x80000000, 95 0x20002000, 96 0x80000000, 97 0x20002000, 98 0x80000000, 99 0x20002000, 100 0x80000000, 101 0x20002000, 102 0x80000000, 103 0x20002000, 104 0x80000000, 105 0x20002000, 106 0x80000000, 107 0x20002000, 108 0x80000000, 109 0x20002000, 110 0x80000000, 111 0x20002000, 112 0x80000000, 113 0x20002000, 114 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ 115 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */ 116 117 0xc0026900, 118 0x000000d9, 119 0x00000000, /* CP_RINGID */ 120 0x00000000, /* CP_VMID */ 121 122 0xc0046900, 123 0x00000100, 124 0xffffffff, /* VGT_MAX_VTX_INDX */ 125 0x00000000, /* VGT_MIN_VTX_INDX */ 126 0x00000000, /* VGT_INDX_OFFSET */ 127 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ 128 129 0xc0046900, 130 0x00000105, 131 0x00000000, /* CB_BLEND_RED */ 132 0x00000000, /* CB_BLEND_GREEN */ 133 0x00000000, /* CB_BLEND_BLUE */ 134 0x00000000, /* CB_BLEND_ALPHA */ 135 136 0xc0016900, 137 0x000001e0, 138 0x00000000, /* CB_BLEND0_CONTROL */ 139 140 0xc00e6900, 141 0x00000200, 142 0x00000000, /* DB_DEPTH_CONTROL */ 143 0x00000000, /* DB_EQAA */ 144 0x00cc0010, /* CB_COLOR_CONTROL */ 145 0x00000210, /* DB_SHADER_CONTROL */ 146 0x00010000, /* PA_CL_CLIP_CNTL */ 147 0x00000004, /* PA_SU_SC_MODE_CNTL */ 148 0x00000100, /* PA_CL_VTE_CNTL */ 149 0x00000000, /* PA_CL_VS_OUT_CNTL */ 150 0x00000000, /* PA_CL_NANINF_CNTL */ 151 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */ 152 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */ 153 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */ 154 0x00000000, /* */ 155 0x00000000, /* */ 156 157 0xc0116900, 158 0x00000280, 159 0x00000000, /* PA_SU_POINT_SIZE */ 160 0x00000000, /* PA_SU_POINT_MINMAX */ 161 0x00000008, /* PA_SU_LINE_CNTL */ 162 0x00000000, /* PA_SC_LINE_STIPPLE */ 163 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ 164 0x00000000, /* VGT_HOS_CNTL */ 165 0x00000000, 166 0x00000000, 167 0x00000000, 168 0x00000000, 169 0x00000000, 170 0x00000000, 171 0x00000000, 172 0x00000000, 173 0x00000000, 174 0x00000000, 175 0x00000000, /* VGT_GS_MODE */ 176 177 0xc0026900, 178 0x00000292, 179 0x00000000, /* PA_SC_MODE_CNTL_0 */ 180 0x00000000, /* PA_SC_MODE_CNTL_1 */ 181 182 0xc0016900, 183 0x000002a1, 184 0x00000000, /* VGT_PRIMITIVEID_EN */ 185 186 0xc0016900, 187 0x000002a5, 188 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */ 189 190 0xc0026900, 191 0x000002a8, 192 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ 193 0x00000000, 194 195 0xc0026900, 196 0x000002ad, 197 0x00000000, /* VGT_REUSE_OFF */ 198 0x00000000, 199 200 0xc0016900, 201 0x000002d5, 202 0x00000000, /* VGT_SHADER_STAGES_EN */ 203 204 0xc0016900, 205 0x000002dc, 206 0x0000aa00, /* DB_ALPHA_TO_MASK */ 207 208 0xc0066900, 209 0x000002de, 210 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ 211 0x00000000, 212 0x00000000, 213 0x00000000, 214 0x00000000, 215 0x00000000, 216 217 0xc0026900, 218 0x000002e5, 219 0x00000000, /* VGT_STRMOUT_CONFIG */ 220 0x00000000, 221 222 0xc01b6900, 223 0x000002f5, 224 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */ 225 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */ 226 0x00000000, /* PA_SC_LINE_CNTL */ 227 0x00000000, /* PA_SC_AA_CONFIG */ 228 0x00000005, /* PA_SU_VTX_CNTL */ 229 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ 230 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */ 231 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */ 232 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */ 233 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ 234 0x00000000, 235 0x00000000, 236 0x00000000, 237 0x00000000, 238 0x00000000, 239 0x00000000, 240 0x00000000, 241 0x00000000, 242 0x00000000, 243 0x00000000, 244 0x00000000, 245 0x00000000, 246 0x00000000, 247 0x00000000, 248 0x00000000, 249 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */ 250 0xffffffff, 251 252 0xc0026900, 253 0x00000316, 254 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 255 0x00000010, /* */ 256 }; 257 258 const u32 si_default_size = ARRAY_SIZE(si_default_state); 259