1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
3 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GNU CC.
8
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 #include "config.h"
25 #include "system.h"
26 #include "insn-config.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "flags.h"
30 #include "expr.h"
31 #include "optabs.h"
32 #include "function.h"
33 #include "regs.h"
34 #include "hard-reg-set.h"
35 #include "output.h"
36 #include "insn-attr.h"
37 #include "toplev.h"
38 #include "recog.h"
39 #include "c-pragma.h"
40 #include "integrate.h"
41 #include "tm_p.h"
42 #include "target.h"
43 #include "target-def.h"
44 #include "real.h"
45 #include "langhooks.h"
46
47 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
48
49 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
50 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
51
52 /* These are some macros to abstract register modes. */
53 #define CONST_OK_FOR_ADD(size) \
54 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
55 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
56 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
57 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
58
59 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
60 int current_function_interrupt;
61
62 /* ??? The pragma interrupt support will not work for SH3. */
63 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
64 output code for the next function appropriate for an interrupt handler. */
65 int pragma_interrupt;
66
67 /* This is set by the trap_exit attribute for functions. It specifies
68 a trap number to be used in a trapa instruction at function exit
69 (instead of an rte instruction). */
70 int trap_exit;
71
72 /* This is used by the sp_switch attribute for functions. It specifies
73 a variable holding the address of the stack the interrupt function
74 should switch to/from at entry/exit. */
75 rtx sp_switch;
76
77 /* This is set by #pragma trapa, and is similar to the above, except that
78 the compiler doesn't emit code to preserve all registers. */
79 static int pragma_trapa;
80
81 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
82 which has a separate set of low regs for User and Supervisor modes.
83 This should only be used for the lowest level of interrupts. Higher levels
84 of interrupts must save the registers in case they themselves are
85 interrupted. */
86 int pragma_nosave_low_regs;
87
88 /* This is used for communication between SETUP_INCOMING_VARARGS and
89 sh_expand_prologue. */
90 int current_function_anonymous_args;
91
92 /* Global variables for machine-dependent things. */
93
94 /* Which cpu are we scheduling for. */
95 enum processor_type sh_cpu;
96
97 /* Saved operands from the last compare to use when we generate an scc
98 or bcc insn. */
99
100 rtx sh_compare_op0;
101 rtx sh_compare_op1;
102
103 /* Provides the class number of the smallest class containing
104 reg number. */
105
106 int regno_reg_class[FIRST_PSEUDO_REGISTER] =
107 {
108 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
109 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
110 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
111 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
112 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
113 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
114 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
115 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
116 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
117 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
118 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
119 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
120 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
121 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
122 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
123 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
124 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
125 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
126 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
127 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
128 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
129 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
130 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
131 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
132 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
133 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
134 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
135 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
136 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
137 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
138 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
139 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
140 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
141 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
142 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
143 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
144 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
145 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
146 GENERAL_REGS,
147 };
148
149 char sh_register_names[FIRST_PSEUDO_REGISTER] \
150 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
151
152 char sh_additional_register_names[ADDREGNAMES_SIZE] \
153 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
154 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
155
156 /* Provide reg_class from a letter such as appears in the machine
157 description. *: target independently reserved letter.
158 reg_class_from_letter['e'] is set to NO_REGS for TARGET_FMOVD. */
159
160 enum reg_class reg_class_from_letter[] =
161 {
162 /* a */ ALL_REGS, /* b */ TARGET_REGS, /* c */ FPSCR_REGS, /* d */ DF_REGS,
163 /* e */ FP_REGS, /* f */ FP_REGS, /* g **/ NO_REGS, /* h */ NO_REGS,
164 /* i **/ NO_REGS, /* j */ NO_REGS, /* k */ SIBCALL_REGS, /* l */ PR_REGS,
165 /* m **/ NO_REGS, /* n **/ NO_REGS, /* o **/ NO_REGS, /* p **/ NO_REGS,
166 /* q */ NO_REGS, /* r **/ NO_REGS, /* s **/ NO_REGS, /* t */ T_REGS,
167 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ FP0_REGS, /* x */ MAC_REGS,
168 /* y */ FPUL_REGS, /* z */ R0_REGS
169 };
170
171 int assembler_dialect;
172
173 static void split_branches PARAMS ((rtx));
174 static int branch_dest PARAMS ((rtx));
175 static void force_into PARAMS ((rtx, rtx));
176 static void print_slot PARAMS ((rtx));
177 static rtx add_constant PARAMS ((rtx, enum machine_mode, rtx));
178 static void dump_table PARAMS ((rtx));
179 static int hi_const PARAMS ((rtx));
180 static int broken_move PARAMS ((rtx));
181 static int mova_p PARAMS ((rtx));
182 static rtx find_barrier PARAMS ((int, rtx, rtx));
183 static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *));
184 static rtx gen_block_redirect PARAMS ((rtx, int, int));
185 static void output_stack_adjust PARAMS ((int, rtx, int, rtx (*) (rtx)));
186 static rtx frame_insn PARAMS ((rtx));
187 static rtx push PARAMS ((int));
188 static void pop PARAMS ((int));
189 static void push_regs PARAMS ((HOST_WIDE_INT *));
190 static void calc_live_regs PARAMS ((int *, HOST_WIDE_INT *));
191 static void mark_use PARAMS ((rtx, rtx *));
192 static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
193 static rtx mark_constant_pool_use PARAMS ((rtx));
194 const struct attribute_spec sh_attribute_table[];
195 static tree sh_handle_interrupt_handler_attribute PARAMS ((tree *, tree, tree, int, bool *));
196 static tree sh_handle_sp_switch_attribute PARAMS ((tree *, tree, tree, int, bool *));
197 static tree sh_handle_trap_exit_attribute PARAMS ((tree *, tree, tree, int, bool *));
198 static void sh_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
199 static void sh_insert_attributes PARAMS ((tree, tree *));
200 static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
201 static int sh_use_dfa_interface PARAMS ((void));
202 static int sh_issue_rate PARAMS ((void));
203
204 static bool sh_cannot_modify_jumps_p PARAMS ((void));
205 static bool sh_ms_bitfield_layout_p PARAMS ((tree));
206
207 static void sh_encode_section_info PARAMS ((tree, int));
208 static const char *sh_strip_name_encoding PARAMS ((const char *));
209 static void sh_init_builtins PARAMS ((void));
210 static void sh_media_init_builtins PARAMS ((void));
211 static rtx sh_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
212 static int flow_dependent_p PARAMS ((rtx, rtx));
213 static void flow_dependent_p_1 PARAMS ((rtx, rtx, void *));
214
215
216 /* Initialize the GCC target structure. */
217 #undef TARGET_ATTRIBUTE_TABLE
218 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
219
220 /* The next two are used for debug info when compiling with -gdwarf. */
221 #undef TARGET_ASM_UNALIGNED_HI_OP
222 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
223 #undef TARGET_ASM_UNALIGNED_SI_OP
224 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
225
226 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
227 #undef TARGET_ASM_UNALIGNED_DI_OP
228 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
229 #undef TARGET_ASM_ALIGNED_DI_OP
230 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
231
232 #undef TARGET_ASM_FUNCTION_EPILOGUE
233 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
234
235 #undef TARGET_INSERT_ATTRIBUTES
236 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
237
238 #undef TARGET_SCHED_ADJUST_COST
239 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
240
241 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
242 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
243 sh_use_dfa_interface
244 #undef TARGET_SCHED_ISSUE_RATE
245 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
246
247 #undef TARGET_CANNOT_MODIFY_JUMPS_P
248 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
249
250 #undef TARGET_MS_BITFIELD_LAYOUT_P
251 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
252
253 #undef TARGET_ENCODE_SECTION_INFO
254 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
255 #undef TARGET_STRIP_NAME_ENCODING
256 #define TARGET_STRIP_NAME_ENCODING sh_strip_name_encoding
257
258 #undef TARGET_INIT_BUILTINS
259 #define TARGET_INIT_BUILTINS sh_init_builtins
260 #undef TARGET_EXPAND_BUILTIN
261 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
262
263 struct gcc_target targetm = TARGET_INITIALIZER;
264
265 /* Print the operand address in x to the stream. */
266
267 void
print_operand_address(stream,x)268 print_operand_address (stream, x)
269 FILE *stream;
270 rtx x;
271 {
272 switch (GET_CODE (x))
273 {
274 case REG:
275 case SUBREG:
276 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
277 break;
278
279 case PLUS:
280 {
281 rtx base = XEXP (x, 0);
282 rtx index = XEXP (x, 1);
283
284 switch (GET_CODE (index))
285 {
286 case CONST_INT:
287 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
288 reg_names[true_regnum (base)]);
289 break;
290
291 case REG:
292 case SUBREG:
293 {
294 int base_num = true_regnum (base);
295 int index_num = true_regnum (index);
296
297 fprintf (stream, "@(r0,%s)",
298 reg_names[MAX (base_num, index_num)]);
299 break;
300 }
301
302 default:
303 debug_rtx (x);
304 abort ();
305 }
306 }
307 break;
308
309 case PRE_DEC:
310 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
311 break;
312
313 case POST_INC:
314 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
315 break;
316
317 default:
318 x = mark_constant_pool_use (x);
319 output_addr_const (stream, x);
320 break;
321 }
322 }
323
324 /* Print operand x (an rtx) in assembler syntax to file stream
325 according to modifier code.
326
327 '.' print a .s if insn needs delay slot
328 ',' print LOCAL_LABEL_PREFIX
329 '@' print trap, rte or rts depending upon pragma interruptness
330 '#' output a nop if there is nothing to put in the delay slot
331 ''' print likelyhood suffix (/u for unlikely).
332 'O' print a constant without the #
333 'R' print the LSW of a dp value - changes if in little endian
334 'S' print the MSW of a dp value - changes if in little endian
335 'T' print the next word of a dp value - same as 'R' in big endian mode.
336 'M' print an `x' if `m' will print `base,index'.
337 'N' print 'r63' if the operand is (const_int 0).
338 'm' print a pair `base,offset' or `base,index', for LD and ST.
339 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
340 'o' output an operator. */
341
342 void
print_operand(stream,x,code)343 print_operand (stream, x, code)
344 FILE *stream;
345 rtx x;
346 int code;
347 {
348 int regno;
349 enum machine_mode mode;
350
351 switch (code)
352 {
353 case '.':
354 if (final_sequence
355 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))
356 && get_attr_length (XVECEXP (final_sequence, 0, 1)))
357 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
358 break;
359 case ',':
360 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
361 break;
362 case '@':
363 if (trap_exit)
364 fprintf (stream, "trapa #%d", trap_exit);
365 else if (sh_cfun_interrupt_handler_p ())
366 fprintf (stream, "rte");
367 else
368 fprintf (stream, "rts");
369 break;
370 case '#':
371 /* Output a nop if there's nothing in the delay slot. */
372 if (dbr_sequence_length () == 0)
373 fprintf (stream, "\n\tnop");
374 break;
375 case '\'':
376 {
377 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
378
379 if (note && INTVAL (XEXP (note, 0)) * 2 < REG_BR_PROB_BASE)
380 fputs ("/u", stream);
381 break;
382 }
383 case 'O':
384 x = mark_constant_pool_use (x);
385 output_addr_const (stream, x);
386 break;
387 /* N.B.: %R / %S / %T adjust memory addresses by four.
388 For SHMEDIA, that means they can be used to access the first and
389 second 32 bit part of a 64 bit (or larger) value that
390 might be held in floating point registers or memory.
391 While they can be used to access 64 bit parts of a larger value
392 held in general purpose registers, that won't work with memory -
393 neither for fp registers, since the frxx names are used. */
394 case 'R':
395 if (REG_P (x) || GET_CODE (x) == SUBREG)
396 {
397 regno = true_regnum (x);
398 regno += FP_REGISTER_P (regno) ? 1 : LSW;
399 fputs (reg_names[regno], (stream));
400 }
401 else if (GET_CODE (x) == MEM)
402 {
403 x = adjust_address (x, SImode, 4 * LSW);
404 print_operand_address (stream, XEXP (x, 0));
405 }
406 else
407 {
408 rtx sub = NULL_RTX;
409
410 mode = GET_MODE (x);
411 if (mode == VOIDmode)
412 mode = DImode;
413 if (GET_MODE_SIZE (mode) >= 8)
414 sub = simplify_subreg (SImode, x, mode, 4 * LSW);
415 if (sub)
416 print_operand (stream, sub, 0);
417 else
418 output_operand_lossage ("invalid operand to %%R");
419 }
420 break;
421 case 'S':
422 if (REG_P (x) || GET_CODE (x) == SUBREG)
423 {
424 regno = true_regnum (x);
425 regno += FP_REGISTER_P (regno) ? 0 : MSW;
426 fputs (reg_names[regno], (stream));
427 }
428 else if (GET_CODE (x) == MEM)
429 {
430 x = adjust_address (x, SImode, 4 * MSW);
431 print_operand_address (stream, XEXP (x, 0));
432 }
433 else
434 {
435 rtx sub = NULL_RTX;
436
437 mode = GET_MODE (x);
438 if (mode == VOIDmode)
439 mode = DImode;
440 if (GET_MODE_SIZE (mode) >= 8)
441 sub = simplify_subreg (SImode, x, mode, 4 * MSW);
442 if (sub)
443 print_operand (stream, sub, 0);
444 else
445 output_operand_lossage ("invalid operand to %%S");
446 }
447 break;
448 case 'T':
449 /* Next word of a double. */
450 switch (GET_CODE (x))
451 {
452 case REG:
453 fputs (reg_names[REGNO (x) + 1], (stream));
454 break;
455 case MEM:
456 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
457 && GET_CODE (XEXP (x, 0)) != POST_INC)
458 x = adjust_address (x, SImode, 4);
459 print_operand_address (stream, XEXP (x, 0));
460 break;
461 default:
462 break;
463 }
464 break;
465 case 'o':
466 switch (GET_CODE (x))
467 {
468 case PLUS: fputs ("add", stream); break;
469 case MINUS: fputs ("sub", stream); break;
470 case MULT: fputs ("mul", stream); break;
471 case DIV: fputs ("div", stream); break;
472 case EQ: fputs ("eq", stream); break;
473 case NE: fputs ("ne", stream); break;
474 case GT: case LT: fputs ("gt", stream); break;
475 case GE: case LE: fputs ("ge", stream); break;
476 case GTU: case LTU: fputs ("gtu", stream); break;
477 case GEU: case LEU: fputs ("geu", stream); break;
478 default:
479 break;
480 }
481 break;
482 case 'M':
483 if (GET_CODE (x) == MEM
484 && GET_CODE (XEXP (x, 0)) == PLUS
485 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == REG
486 || GET_CODE (XEXP (XEXP (x, 0), 1)) == SUBREG))
487 fputc ('x', stream);
488 break;
489
490 case 'm':
491 if (GET_CODE (x) != MEM)
492 abort ();
493 x = XEXP (x, 0);
494 switch (GET_CODE (x))
495 {
496 case REG:
497 case SUBREG:
498 print_operand (stream, x, 0);
499 fputs (", 0", stream);
500 break;
501
502 case PLUS:
503 print_operand (stream, XEXP (x, 0), 0);
504 fputs (", ", stream);
505 print_operand (stream, XEXP (x, 1), 0);
506 break;
507
508 default:
509 abort ();
510 }
511 break;
512
513 case 'N':
514 if (x == CONST0_RTX (GET_MODE (x)))
515 {
516 fprintf ((stream), "r63");
517 break;
518 }
519 goto default_output;
520 case 'u':
521 if (GET_CODE (x) == CONST_INT)
522 {
523 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
524 break;
525 }
526 /* Fall through. */
527
528 default_output:
529 default:
530 switch (GET_CODE (x))
531 {
532 /* FIXME: We need this on SHmedia32 because reload generates
533 some sign-extended HI or QI loads into DImode registers
534 but, because Pmode is SImode, the address ends up with a
535 subreg:SI of the DImode register. Maybe reload should be
536 fixed so as to apply alter_subreg to such loads? */
537 case SUBREG:
538 if (SUBREG_BYTE (x) != 0
539 || GET_CODE (SUBREG_REG (x)) != REG)
540 abort ();
541
542 x = SUBREG_REG (x);
543 /* Fall through. */
544
545 case REG:
546 if (FP_REGISTER_P (REGNO (x))
547 && GET_MODE (x) == V16SFmode)
548 fprintf ((stream), "mtrx%s", reg_names[REGNO (x)] + 2);
549 else if (FP_REGISTER_P (REGNO (x))
550 && GET_MODE (x) == V4SFmode)
551 fprintf ((stream), "fv%s", reg_names[REGNO (x)] + 2);
552 else if (GET_CODE (x) == REG
553 && GET_MODE (x) == V2SFmode)
554 fprintf ((stream), "fp%s", reg_names[REGNO (x)] + 2);
555 else if (FP_REGISTER_P (REGNO (x))
556 && GET_MODE_SIZE (GET_MODE (x)) > 4)
557 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
558 else
559 fputs (reg_names[REGNO (x)], (stream));
560 break;
561
562 case MEM:
563 output_address (XEXP (x, 0));
564 break;
565
566 case CONST:
567 if (TARGET_SHMEDIA
568 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
569 && GET_MODE (XEXP (x, 0)) == DImode
570 && GET_CODE (XEXP (XEXP (x, 0), 0)) == TRUNCATE
571 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)
572 {
573 rtx val = XEXP (XEXP (XEXP (x, 0), 0), 0);
574
575 fputc ('(', stream);
576 if (GET_CODE (val) == ASHIFTRT)
577 {
578 fputc ('(', stream);
579 if (GET_CODE (XEXP (val, 0)) == CONST)
580 fputc ('(', stream);
581 output_addr_const (stream, XEXP (val, 0));
582 if (GET_CODE (XEXP (val, 0)) == CONST)
583 fputc (')', stream);
584 fputs (" >> ", stream);
585 output_addr_const (stream, XEXP (val, 1));
586 fputc (')', stream);
587 }
588 else
589 {
590 if (GET_CODE (val) == CONST)
591 fputc ('(', stream);
592 output_addr_const (stream, val);
593 if (GET_CODE (val) == CONST)
594 fputc (')', stream);
595 }
596 fputs (" & 65535)", stream);
597 break;
598 }
599
600 /* Fall through. */
601 default:
602 if (TARGET_SH1)
603 fputc ('#', stream);
604 output_addr_const (stream, x);
605 break;
606 }
607 break;
608 }
609 }
610
611 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
612 static void
force_into(value,target)613 force_into (value, target)
614 rtx value, target;
615 {
616 value = force_operand (value, target);
617 if (! rtx_equal_p (value, target))
618 emit_insn (gen_move_insn (target, value));
619 }
620
621 /* Emit code to perform a block move. Choose the best method.
622
623 OPERANDS[0] is the destination.
624 OPERANDS[1] is the source.
625 OPERANDS[2] is the size.
626 OPERANDS[3] is the alignment safe to use. */
627
628 int
expand_block_move(operands)629 expand_block_move (operands)
630 rtx *operands;
631 {
632 int align = INTVAL (operands[3]);
633 int constp = (GET_CODE (operands[2]) == CONST_INT);
634 int bytes = (constp ? INTVAL (operands[2]) : 0);
635
636 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
637 alignment, or if it isn't a multiple of 4 bytes, then fail. */
638 if (! constp || align < 4 || (bytes % 4 != 0))
639 return 0;
640
641 if (TARGET_HARD_SH4)
642 {
643 if (bytes < 12)
644 return 0;
645 else if (bytes == 12)
646 {
647 tree entry_name;
648 rtx sym;
649 rtx func_addr_rtx;
650 rtx r4 = gen_rtx (REG, SImode, 4);
651 rtx r5 = gen_rtx (REG, SImode, 5);
652
653 entry_name = get_identifier ("__movstrSI12_i4");
654
655 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
656 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
657 force_into (XEXP (operands[0], 0), r4);
658 force_into (XEXP (operands[1], 0), r5);
659 emit_insn (gen_block_move_real_i4 (func_addr_rtx));
660 return 1;
661 }
662 else if (! TARGET_SMALLCODE)
663 {
664 tree entry_name;
665 rtx sym;
666 rtx func_addr_rtx;
667 int dwords;
668 rtx r4 = gen_rtx (REG, SImode, 4);
669 rtx r5 = gen_rtx (REG, SImode, 5);
670 rtx r6 = gen_rtx (REG, SImode, 6);
671
672 entry_name = get_identifier (bytes & 4
673 ? "__movstr_i4_odd"
674 : "__movstr_i4_even");
675 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
676 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
677 force_into (XEXP (operands[0], 0), r4);
678 force_into (XEXP (operands[1], 0), r5);
679
680 dwords = bytes >> 3;
681 emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
682 emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
683 return 1;
684 }
685 else
686 return 0;
687 }
688 if (bytes < 64)
689 {
690 char entry[30];
691 tree entry_name;
692 rtx sym;
693 rtx func_addr_rtx;
694 rtx r4 = gen_rtx_REG (SImode, 4);
695 rtx r5 = gen_rtx_REG (SImode, 5);
696
697 sprintf (entry, "__movstrSI%d", bytes);
698 entry_name = get_identifier (entry);
699 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
700 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
701 force_into (XEXP (operands[0], 0), r4);
702 force_into (XEXP (operands[1], 0), r5);
703 emit_insn (gen_block_move_real (func_addr_rtx));
704 return 1;
705 }
706
707 /* This is the same number of bytes as a memcpy call, but to a different
708 less common function name, so this will occasionally use more space. */
709 if (! TARGET_SMALLCODE)
710 {
711 tree entry_name;
712 rtx sym;
713 rtx func_addr_rtx;
714 int final_switch, while_loop;
715 rtx r4 = gen_rtx_REG (SImode, 4);
716 rtx r5 = gen_rtx_REG (SImode, 5);
717 rtx r6 = gen_rtx_REG (SImode, 6);
718
719 entry_name = get_identifier ("__movstr");
720 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (entry_name));
721 func_addr_rtx = copy_to_mode_reg (Pmode, sym);
722 force_into (XEXP (operands[0], 0), r4);
723 force_into (XEXP (operands[1], 0), r5);
724
725 /* r6 controls the size of the move. 16 is decremented from it
726 for each 64 bytes moved. Then the negative bit left over is used
727 as an index into a list of move instructions. e.g., a 72 byte move
728 would be set up with size(r6) = 14, for one iteration through the
729 big while loop, and a switch of -2 for the last part. */
730
731 final_switch = 16 - ((bytes / 4) % 16);
732 while_loop = ((bytes / 4) / 16 - 1) * 16;
733 emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
734 emit_insn (gen_block_lump_real (func_addr_rtx));
735 return 1;
736 }
737
738 return 0;
739 }
740
741 /* Prepare operands for a move define_expand; specifically, one of the
742 operands must be in a register. */
743
744 int
prepare_move_operands(operands,mode)745 prepare_move_operands (operands, mode)
746 rtx operands[];
747 enum machine_mode mode;
748 {
749 if ((mode == SImode || mode == DImode) && flag_pic)
750 {
751 rtx temp;
752 if (SYMBOLIC_CONST_P (operands[1]))
753 {
754 if (GET_CODE (operands[0]) == MEM)
755 operands[1] = force_reg (Pmode, operands[1]);
756 else if (TARGET_SHMEDIA
757 && GET_CODE (operands[1]) == LABEL_REF
758 && target_reg_operand (operands[0], mode))
759 /* It's ok. */;
760 else
761 {
762 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
763 operands[1] = legitimize_pic_address (operands[1], mode, temp);
764 }
765 }
766 else if (GET_CODE (operands[1]) == CONST
767 && GET_CODE (XEXP (operands[1], 0)) == PLUS
768 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
769 {
770 temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
771 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
772 mode, temp);
773 operands[1] = expand_binop (mode, add_optab, temp,
774 XEXP (XEXP (operands[1], 0), 1),
775 no_new_pseudos ? temp
776 : gen_reg_rtx (Pmode),
777 0, OPTAB_LIB_WIDEN);
778 }
779 }
780
781 if (! reload_in_progress && ! reload_completed)
782 {
783 /* Copy the source to a register if both operands aren't registers. */
784 if (! register_operand (operands[0], mode)
785 && ! sh_register_operand (operands[1], mode))
786 operands[1] = copy_to_mode_reg (mode, operands[1]);
787
788 /* This case can happen while generating code to move the result
789 of a library call to the target. Reject `st r0,@(rX,rY)' because
790 reload will fail to find a spill register for rX, since r0 is already
791 being used for the source. */
792 else if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 0
793 && GET_CODE (operands[0]) == MEM
794 && GET_CODE (XEXP (operands[0], 0)) == PLUS
795 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == REG)
796 operands[1] = copy_to_mode_reg (mode, operands[1]);
797 }
798
799 return 0;
800 }
801
802 /* Prepare the operands for an scc instruction; make sure that the
803 compare has been done. */
804 rtx
prepare_scc_operands(code)805 prepare_scc_operands (code)
806 enum rtx_code code;
807 {
808 rtx t_reg = gen_rtx_REG (SImode, T_REG);
809 enum rtx_code oldcode = code;
810 enum machine_mode mode;
811
812 /* First need a compare insn. */
813 switch (code)
814 {
815 case NE:
816 /* It isn't possible to handle this case. */
817 abort ();
818 case LT:
819 code = GT;
820 break;
821 case LE:
822 code = GE;
823 break;
824 case LTU:
825 code = GTU;
826 break;
827 case LEU:
828 code = GEU;
829 break;
830 default:
831 break;
832 }
833 if (code != oldcode)
834 {
835 rtx tmp = sh_compare_op0;
836 sh_compare_op0 = sh_compare_op1;
837 sh_compare_op1 = tmp;
838 }
839
840 mode = GET_MODE (sh_compare_op0);
841 if (mode == VOIDmode)
842 mode = GET_MODE (sh_compare_op1);
843
844 sh_compare_op0 = force_reg (mode, sh_compare_op0);
845 if ((code != EQ && code != NE
846 && (sh_compare_op1 != const0_rtx
847 || code == GTU || code == GEU || code == LTU || code == LEU))
848 || (mode == DImode && sh_compare_op1 != const0_rtx)
849 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
850 sh_compare_op1 = force_reg (mode, sh_compare_op1);
851
852 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
853 (mode == SFmode ? emit_sf_insn : emit_df_insn)
854 (gen_rtx (PARALLEL, VOIDmode, gen_rtvec (2,
855 gen_rtx (SET, VOIDmode, t_reg,
856 gen_rtx (code, SImode,
857 sh_compare_op0, sh_compare_op1)),
858 gen_rtx (USE, VOIDmode, get_fpscr_rtx ()))));
859 else
860 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
861 gen_rtx (code, SImode, sh_compare_op0,
862 sh_compare_op1)));
863
864 return t_reg;
865 }
866
867 /* Called from the md file, set up the operands of a compare instruction. */
868
869 void
from_compare(operands,code)870 from_compare (operands, code)
871 rtx *operands;
872 int code;
873 {
874 enum machine_mode mode = GET_MODE (sh_compare_op0);
875 rtx insn;
876 if (mode == VOIDmode)
877 mode = GET_MODE (sh_compare_op1);
878 if (code != EQ
879 || mode == DImode
880 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
881 {
882 /* Force args into regs, since we can't use constants here. */
883 sh_compare_op0 = force_reg (mode, sh_compare_op0);
884 if (sh_compare_op1 != const0_rtx
885 || code == GTU || code == GEU
886 || (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT))
887 sh_compare_op1 = force_reg (mode, sh_compare_op1);
888 }
889 if (TARGET_SH3E && GET_MODE_CLASS (mode) == MODE_FLOAT && code == GE)
890 {
891 from_compare (operands, GT);
892 insn = gen_ieee_ccmpeqsf_t (sh_compare_op0, sh_compare_op1);
893 }
894 else
895 insn = gen_rtx_SET (VOIDmode,
896 gen_rtx_REG (SImode, T_REG),
897 gen_rtx (code, SImode, sh_compare_op0,
898 sh_compare_op1));
899 if (TARGET_SH4 && GET_MODE_CLASS (mode) == MODE_FLOAT)
900 {
901 insn = gen_rtx (PARALLEL, VOIDmode,
902 gen_rtvec (2, insn,
903 gen_rtx (USE, VOIDmode, get_fpscr_rtx ())));
904 (mode == SFmode ? emit_sf_insn : emit_df_insn) (insn);
905 }
906 else
907 emit_insn (insn);
908 }
909
910 /* Functions to output assembly code. */
911
912 /* Return a sequence of instructions to perform DI or DF move.
913
914 Since the SH cannot move a DI or DF in one instruction, we have
915 to take care when we see overlapping source and dest registers. */
916
917 const char *
output_movedouble(insn,operands,mode)918 output_movedouble (insn, operands, mode)
919 rtx insn ATTRIBUTE_UNUSED;
920 rtx operands[];
921 enum machine_mode mode;
922 {
923 rtx dst = operands[0];
924 rtx src = operands[1];
925
926 if (GET_CODE (dst) == MEM
927 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
928 return "mov.l %T1,%0\n\tmov.l %1,%0";
929
930 if (register_operand (dst, mode)
931 && register_operand (src, mode))
932 {
933 if (REGNO (src) == MACH_REG)
934 return "sts mach,%S0\n\tsts macl,%R0";
935
936 /* When mov.d r1,r2 do r2->r3 then r1->r2;
937 when mov.d r1,r0 do r1->r0 then r2->r1. */
938
939 if (REGNO (src) + 1 == REGNO (dst))
940 return "mov %T1,%T0\n\tmov %1,%0";
941 else
942 return "mov %1,%0\n\tmov %T1,%T0";
943 }
944 else if (GET_CODE (src) == CONST_INT)
945 {
946 if (INTVAL (src) < 0)
947 output_asm_insn ("mov #-1,%S0", operands);
948 else
949 output_asm_insn ("mov #0,%S0", operands);
950
951 return "mov %1,%R0";
952 }
953 else if (GET_CODE (src) == MEM)
954 {
955 int ptrreg = -1;
956 int dreg = REGNO (dst);
957 rtx inside = XEXP (src, 0);
958
959 if (GET_CODE (inside) == REG)
960 ptrreg = REGNO (inside);
961 else if (GET_CODE (inside) == SUBREG)
962 ptrreg = subreg_regno (inside);
963 else if (GET_CODE (inside) == PLUS)
964 {
965 ptrreg = REGNO (XEXP (inside, 0));
966 /* ??? A r0+REG address shouldn't be possible here, because it isn't
967 an offsettable address. Unfortunately, offsettable addresses use
968 QImode to check the offset, and a QImode offsettable address
969 requires r0 for the other operand, which is not currently
970 supported, so we can't use the 'o' constraint.
971 Thus we must check for and handle r0+REG addresses here.
972 We punt for now, since this is likely very rare. */
973 if (GET_CODE (XEXP (inside, 1)) == REG)
974 abort ();
975 }
976 else if (GET_CODE (inside) == LABEL_REF)
977 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
978 else if (GET_CODE (inside) == POST_INC)
979 return "mov.l %1,%0\n\tmov.l %1,%T0";
980 else
981 abort ();
982
983 /* Work out the safe way to copy. Copy into the second half first. */
984 if (dreg == ptrreg)
985 return "mov.l %T1,%T0\n\tmov.l %1,%0";
986 }
987
988 return "mov.l %1,%0\n\tmov.l %T1,%T0";
989 }
990
991 /* Print an instruction which would have gone into a delay slot after
992 another instruction, but couldn't because the other instruction expanded
993 into a sequence where putting the slot insn at the end wouldn't work. */
994
995 static void
print_slot(insn)996 print_slot (insn)
997 rtx insn;
998 {
999 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file, optimize, 0, 1);
1000
1001 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
1002 }
1003
1004 const char *
output_far_jump(insn,op)1005 output_far_jump (insn, op)
1006 rtx insn;
1007 rtx op;
1008 {
1009 struct { rtx lab, reg, op; } this;
1010 rtx braf_base_lab = NULL_RTX;
1011 const char *jump;
1012 int far;
1013 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
1014 rtx prev;
1015
1016 this.lab = gen_label_rtx ();
1017
1018 if (TARGET_SH2
1019 && offset >= -32764
1020 && offset - get_attr_length (insn) <= 32766)
1021 {
1022 far = 0;
1023 jump = "mov.w %O0,%1; braf %1";
1024 }
1025 else
1026 {
1027 far = 1;
1028 if (flag_pic)
1029 {
1030 if (TARGET_SH2)
1031 jump = "mov.l %O0,%1; braf %1";
1032 else
1033 jump = "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1034 }
1035 else
1036 jump = "mov.l %O0,%1; jmp @%1";
1037 }
1038 /* If we have a scratch register available, use it. */
1039 if (GET_CODE ((prev = prev_nonnote_insn (insn))) == INSN
1040 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
1041 {
1042 this.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
1043 if (REGNO (this.reg) == R0_REG && flag_pic && ! TARGET_SH2)
1044 jump = "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1045 output_asm_insn (jump, &this.lab);
1046 if (dbr_sequence_length ())
1047 print_slot (final_sequence);
1048 else
1049 output_asm_insn ("nop", 0);
1050 }
1051 else
1052 {
1053 /* Output the delay slot insn first if any. */
1054 if (dbr_sequence_length ())
1055 print_slot (final_sequence);
1056
1057 this.reg = gen_rtx_REG (SImode, 13);
1058 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1059 Fortunately, MACL is fixed and call-clobbered, and we never
1060 need its value across jumps, so save r13 in it instead of in
1061 the stack. */
1062 if (TARGET_SH5)
1063 output_asm_insn ("lds r13, macl", 0);
1064 else
1065 output_asm_insn ("mov.l r13,@-r15", 0);
1066 output_asm_insn (jump, &this.lab);
1067 if (TARGET_SH5)
1068 output_asm_insn ("sts macl, r13", 0);
1069 else
1070 output_asm_insn ("mov.l @r15+,r13", 0);
1071 }
1072 if (far && flag_pic && TARGET_SH2)
1073 {
1074 braf_base_lab = gen_label_rtx ();
1075 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
1076 CODE_LABEL_NUMBER (braf_base_lab));
1077 }
1078 if (far)
1079 output_asm_insn (".align 2", 0);
1080 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (this.lab));
1081 this.op = op;
1082 if (far && flag_pic)
1083 {
1084 if (TARGET_SH2)
1085 this.lab = braf_base_lab;
1086 output_asm_insn (".long %O2-%O0", &this.lab);
1087 }
1088 else
1089 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this.lab);
1090 return "";
1091 }
1092
1093 /* Local label counter, used for constants in the pool and inside
1094 pattern branches. */
1095
1096 static int lf = 100;
1097
1098 /* Output code for ordinary branches. */
1099
1100 const char *
output_branch(logic,insn,operands)1101 output_branch (logic, insn, operands)
1102 int logic;
1103 rtx insn;
1104 rtx *operands;
1105 {
1106 switch (get_attr_length (insn))
1107 {
1108 case 6:
1109 /* This can happen if filling the delay slot has caused a forward
1110 branch to exceed its range (we could reverse it, but only
1111 when we know we won't overextend other branches; this should
1112 best be handled by relaxation).
1113 It can also happen when other condbranches hoist delay slot insn
1114 from their destination, thus leading to code size increase.
1115 But the branch will still be in the range -4092..+4098 bytes. */
1116
1117 if (! TARGET_RELAX)
1118 {
1119 int label = lf++;
1120 /* The call to print_slot will clobber the operands. */
1121 rtx op0 = operands[0];
1122
1123 /* If the instruction in the delay slot is annulled (true), then
1124 there is no delay slot where we can put it now. The only safe
1125 place for it is after the label. final will do that by default. */
1126
1127 if (final_sequence
1128 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0)))
1129 {
1130 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
1131 ASSEMBLER_DIALECT ? "/" : ".", label);
1132 print_slot (final_sequence);
1133 }
1134 else
1135 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
1136
1137 output_asm_insn ("bra\t%l0", &op0);
1138 fprintf (asm_out_file, "\tnop\n");
1139 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file, "LF", label);
1140
1141 return "";
1142 }
1143 /* When relaxing, handle this like a short branch. The linker
1144 will fix it up if it still doesn't fit after relaxation. */
1145 case 2:
1146 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
1147 default:
1148 /* There should be no longer branches now - that would
1149 indicate that something has destroyed the branches set
1150 up in machine_dependent_reorg. */
1151 abort ();
1152 }
1153 }
1154
1155 const char *
output_branchy_insn(code,template,insn,operands)1156 output_branchy_insn (code, template, insn, operands)
1157 enum rtx_code code;
1158 const char *template;
1159 rtx insn;
1160 rtx *operands;
1161 {
1162 rtx next_insn = NEXT_INSN (insn);
1163
1164 if (next_insn && GET_CODE (next_insn) == JUMP_INSN && condjump_p (next_insn))
1165 {
1166 rtx src = SET_SRC (PATTERN (next_insn));
1167 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
1168 {
1169 /* Following branch not taken */
1170 operands[9] = gen_label_rtx ();
1171 emit_label_after (operands[9], next_insn);
1172 INSN_ADDRESSES_NEW (operands[9],
1173 INSN_ADDRESSES (INSN_UID (next_insn))
1174 + get_attr_length (next_insn));
1175 return template;
1176 }
1177 else
1178 {
1179 int offset = (branch_dest (next_insn)
1180 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
1181 if (offset >= -252 && offset <= 258)
1182 {
1183 if (GET_CODE (src) == IF_THEN_ELSE)
1184 /* branch_true */
1185 src = XEXP (src, 1);
1186 operands[9] = src;
1187 return template;
1188 }
1189 }
1190 }
1191 operands[9] = gen_label_rtx ();
1192 emit_label_after (operands[9], insn);
1193 INSN_ADDRESSES_NEW (operands[9],
1194 INSN_ADDRESSES (INSN_UID (insn))
1195 + get_attr_length (insn));
1196 return template;
1197 }
1198
1199 const char *
output_ieee_ccmpeq(insn,operands)1200 output_ieee_ccmpeq (insn, operands)
1201 rtx insn, *operands;
1202 {
1203 return output_branchy_insn (NE, "bt\t%l9\\;fcmp/eq\t%1,%0", insn, operands);
1204 }
1205
1206 /* Output to FILE the start of the assembler file. */
1207
1208 void
output_file_start(file)1209 output_file_start (file)
1210 FILE *file;
1211 {
1212 output_file_directive (file, main_input_filename);
1213
1214 /* Switch to the data section so that the coffsem symbol
1215 isn't in the text section. */
1216 data_section ();
1217
1218 if (TARGET_LITTLE_ENDIAN)
1219 fprintf (file, "\t.little\n");
1220
1221 if (TARGET_SHCOMPACT)
1222 fprintf (file, "\t.mode\tSHcompact\n");
1223 else if (TARGET_SHMEDIA)
1224 fprintf (file, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1225 TARGET_SHMEDIA64 ? 64 : 32);
1226 }
1227
1228 /* Actual number of instructions used to make a shift by N. */
1229 static const char ashiftrt_insns[] =
1230 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1231
1232 /* Left shift and logical right shift are the same. */
1233 static const char shift_insns[] =
1234 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1235
1236 /* Individual shift amounts needed to get the above length sequences.
1237 One bit right shifts clobber the T bit, so when possible, put one bit
1238 shifts in the middle of the sequence, so the ends are eligible for
1239 branch delay slots. */
1240 static const short shift_amounts[32][5] = {
1241 {0}, {1}, {2}, {2, 1},
1242 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1243 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1244 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1245 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1246 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1247 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1248 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1249
1250 /* Likewise, but for shift amounts < 16, up to three highmost bits
1251 might be clobbered. This is typically used when combined with some
1252 kind of sign or zero extension. */
1253
1254 static const char ext_shift_insns[] =
1255 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1256
1257 static const short ext_shift_amounts[32][4] = {
1258 {0}, {1}, {2}, {2, 1},
1259 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1260 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1261 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1262 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1263 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1264 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1265 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1266
1267 /* Assuming we have a value that has been sign-extended by at least one bit,
1268 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1269 to shift it by N without data loss, and quicker than by other means? */
1270 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1271
1272 /* This is used in length attributes in sh.md to help compute the length
1273 of arbitrary constant shift instructions. */
1274
1275 int
shift_insns_rtx(insn)1276 shift_insns_rtx (insn)
1277 rtx insn;
1278 {
1279 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1280 int shift_count = INTVAL (XEXP (set_src, 1));
1281 enum rtx_code shift_code = GET_CODE (set_src);
1282
1283 switch (shift_code)
1284 {
1285 case ASHIFTRT:
1286 return ashiftrt_insns[shift_count];
1287 case LSHIFTRT:
1288 case ASHIFT:
1289 return shift_insns[shift_count];
1290 default:
1291 abort();
1292 }
1293 }
1294
1295 /* Return the cost of a shift. */
1296
1297 int
shiftcosts(x)1298 shiftcosts (x)
1299 rtx x;
1300 {
1301 int value;
1302
1303 if (TARGET_SHMEDIA)
1304 return 1;
1305
1306 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
1307 {
1308 if (GET_MODE (x) == DImode
1309 && GET_CODE (XEXP (x, 1)) == CONST_INT
1310 && INTVAL (XEXP (x, 1)) == 1)
1311 return 2;
1312
1313 /* Everything else is invalid, because there is no pattern for it. */
1314 return 10000;
1315 }
1316 /* If shift by a non constant, then this will be expensive. */
1317 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1318 return SH_DYNAMIC_SHIFT_COST;
1319
1320 value = INTVAL (XEXP (x, 1));
1321
1322 /* Otherwise, return the true cost in instructions. */
1323 if (GET_CODE (x) == ASHIFTRT)
1324 {
1325 int cost = ashiftrt_insns[value];
1326 /* If SH3, then we put the constant in a reg and use shad. */
1327 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
1328 cost = 1 + SH_DYNAMIC_SHIFT_COST;
1329 return cost;
1330 }
1331 else
1332 return shift_insns[value];
1333 }
1334
1335 /* Return the cost of an AND operation. */
1336
1337 int
andcosts(x)1338 andcosts (x)
1339 rtx x;
1340 {
1341 int i;
1342
1343 /* Anding with a register is a single cycle and instruction. */
1344 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
1345 return 1;
1346
1347 i = INTVAL (XEXP (x, 1));
1348
1349 if (TARGET_SHMEDIA)
1350 {
1351 if ((GET_CODE (XEXP (x, 1)) == CONST_INT
1352 && CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1353 || EXTRA_CONSTRAINT_S (XEXP (x, 1)))
1354 return 1;
1355 else
1356 return 2;
1357 }
1358
1359 /* These constants are single cycle extu.[bw] instructions. */
1360 if (i == 0xff || i == 0xffff)
1361 return 1;
1362 /* Constants that can be used in an and immediate instruction is a single
1363 cycle, but this requires r0, so make it a little more expensive. */
1364 if (CONST_OK_FOR_L (i))
1365 return 2;
1366 /* Constants that can be loaded with a mov immediate and an and.
1367 This case is probably unnecessary. */
1368 if (CONST_OK_FOR_I (i))
1369 return 2;
1370 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1371 This case is probably unnecessary. */
1372 return 3;
1373 }
1374
1375 /* Return the cost of an addition or a subtraction. */
1376
1377 int
addsubcosts(x)1378 addsubcosts (x)
1379 rtx x;
1380 {
1381 /* Adding a register is a single cycle insn. */
1382 if (GET_CODE (XEXP (x, 1)) == REG
1383 || GET_CODE (XEXP (x, 1)) == SUBREG)
1384 return 1;
1385
1386 /* Likewise for small constants. */
1387 if (GET_CODE (XEXP (x, 1)) == CONST_INT
1388 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
1389 return 1;
1390
1391 if (TARGET_SHMEDIA)
1392 switch (GET_CODE (XEXP (x, 1)))
1393 {
1394 case CONST:
1395 case LABEL_REF:
1396 case SYMBOL_REF:
1397 return TARGET_SHMEDIA64 ? 5 : 3;
1398
1399 case CONST_INT:
1400 if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1))))
1401 return 2;
1402 else if (CONST_OK_FOR_J (INTVAL (XEXP (x, 1)) >> 16))
1403 return 3;
1404 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x, 1)) >> 16) >> 16))
1405 return 4;
1406
1407 /* Fall through. */
1408 default:
1409 return 5;
1410 }
1411
1412 /* Any other constant requires a 2 cycle pc-relative load plus an
1413 addition. */
1414 return 3;
1415 }
1416
1417 /* Return the cost of a multiply. */
1418 int
multcosts(x)1419 multcosts (x)
1420 rtx x ATTRIBUTE_UNUSED;
1421 {
1422 if (TARGET_SHMEDIA)
1423 return 3;
1424
1425 if (TARGET_SH2)
1426 {
1427 /* We have a mul insn, so we can never take more than the mul and the
1428 read of the mac reg, but count more because of the latency and extra
1429 reg usage. */
1430 if (TARGET_SMALLCODE)
1431 return 2;
1432 return 3;
1433 }
1434
1435 /* If we're aiming at small code, then just count the number of
1436 insns in a multiply call sequence. */
1437 if (TARGET_SMALLCODE)
1438 return 5;
1439
1440 /* Otherwise count all the insns in the routine we'd be calling too. */
1441 return 20;
1442 }
1443
1444 /* Code to expand a shift. */
1445
1446 void
gen_ashift(type,n,reg)1447 gen_ashift (type, n, reg)
1448 int type;
1449 int n;
1450 rtx reg;
1451 {
1452 /* Negative values here come from the shift_amounts array. */
1453 if (n < 0)
1454 {
1455 if (type == ASHIFT)
1456 type = LSHIFTRT;
1457 else
1458 type = ASHIFT;
1459 n = -n;
1460 }
1461
1462 switch (type)
1463 {
1464 case ASHIFTRT:
1465 emit_insn (gen_ashrsi3_k (reg, reg, GEN_INT (n)));
1466 break;
1467 case LSHIFTRT:
1468 if (n == 1)
1469 emit_insn (gen_lshrsi3_m (reg, reg, GEN_INT (n)));
1470 else
1471 emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
1472 break;
1473 case ASHIFT:
1474 emit_insn (gen_ashlsi3_std (reg, reg, GEN_INT (n)));
1475 break;
1476 }
1477 }
1478
1479 /* Same for HImode */
1480
1481 void
gen_ashift_hi(type,n,reg)1482 gen_ashift_hi (type, n, reg)
1483 int type;
1484 int n;
1485 rtx reg;
1486 {
1487 /* Negative values here come from the shift_amounts array. */
1488 if (n < 0)
1489 {
1490 if (type == ASHIFT)
1491 type = LSHIFTRT;
1492 else
1493 type = ASHIFT;
1494 n = -n;
1495 }
1496
1497 switch (type)
1498 {
1499 case ASHIFTRT:
1500 case LSHIFTRT:
1501 /* We don't have HImode right shift operations because using the
1502 ordinary 32 bit shift instructions for that doesn't generate proper
1503 zero/sign extension.
1504 gen_ashift_hi is only called in contexts where we know that the
1505 sign extension works out correctly. */
1506 {
1507 int offset = 0;
1508 if (GET_CODE (reg) == SUBREG)
1509 {
1510 offset = SUBREG_BYTE (reg);
1511 reg = SUBREG_REG (reg);
1512 }
1513 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
1514 break;
1515 }
1516 case ASHIFT:
1517 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
1518 break;
1519 }
1520 }
1521
1522 /* Output RTL to split a constant shift into its component SH constant
1523 shift instructions. */
1524
1525 void
gen_shifty_op(code,operands)1526 gen_shifty_op (code, operands)
1527 int code;
1528 rtx *operands;
1529 {
1530 int value = INTVAL (operands[2]);
1531 int max, i;
1532
1533 /* Truncate the shift count in case it is out of bounds. */
1534 value = value & 0x1f;
1535
1536 if (value == 31)
1537 {
1538 if (code == LSHIFTRT)
1539 {
1540 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1541 emit_insn (gen_movt (operands[0]));
1542 return;
1543 }
1544 else if (code == ASHIFT)
1545 {
1546 /* There is a two instruction sequence for 31 bit left shifts,
1547 but it requires r0. */
1548 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 0)
1549 {
1550 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
1551 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1552 return;
1553 }
1554 }
1555 }
1556 else if (value == 0)
1557 {
1558 /* This can happen when not optimizing. We must output something here
1559 to prevent the compiler from aborting in final.c after the try_split
1560 call. */
1561 emit_insn (gen_nop ());
1562 return;
1563 }
1564
1565 max = shift_insns[value];
1566 for (i = 0; i < max; i++)
1567 gen_ashift (code, shift_amounts[value][i], operands[0]);
1568 }
1569
1570 /* Same as above, but optimized for values where the topmost bits don't
1571 matter. */
1572
1573 void
gen_shifty_hi_op(code,operands)1574 gen_shifty_hi_op (code, operands)
1575 int code;
1576 rtx *operands;
1577 {
1578 int value = INTVAL (operands[2]);
1579 int max, i;
1580 void (*gen_fun) PARAMS ((int, int, rtx));
1581
1582 /* This operation is used by and_shl for SImode values with a few
1583 high bits known to be cleared. */
1584 value &= 31;
1585 if (value == 0)
1586 {
1587 emit_insn (gen_nop ());
1588 return;
1589 }
1590
1591 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
1592 if (code == ASHIFT)
1593 {
1594 max = ext_shift_insns[value];
1595 for (i = 0; i < max; i++)
1596 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1597 }
1598 else
1599 /* When shifting right, emit the shifts in reverse order, so that
1600 solitary negative values come first. */
1601 for (i = ext_shift_insns[value] - 1; i >= 0; i--)
1602 gen_fun (code, ext_shift_amounts[value][i], operands[0]);
1603 }
1604
1605 /* Output RTL for an arithmetic right shift. */
1606
1607 /* ??? Rewrite to use super-optimizer sequences. */
1608
1609 int
expand_ashiftrt(operands)1610 expand_ashiftrt (operands)
1611 rtx *operands;
1612 {
1613 rtx sym;
1614 rtx wrk;
1615 char func[18];
1616 tree func_name;
1617 int value;
1618
1619 if (TARGET_SH3)
1620 {
1621 if (GET_CODE (operands[2]) != CONST_INT)
1622 {
1623 rtx count = copy_to_mode_reg (SImode, operands[2]);
1624 emit_insn (gen_negsi2 (count, count));
1625 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1626 return 1;
1627 }
1628 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
1629 > 1 + SH_DYNAMIC_SHIFT_COST)
1630 {
1631 rtx count
1632 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
1633 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
1634 return 1;
1635 }
1636 }
1637 if (GET_CODE (operands[2]) != CONST_INT)
1638 return 0;
1639
1640 value = INTVAL (operands[2]) & 31;
1641
1642 if (value == 31)
1643 {
1644 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
1645 return 1;
1646 }
1647 else if (value >= 16 && value <= 19)
1648 {
1649 wrk = gen_reg_rtx (SImode);
1650 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
1651 value -= 16;
1652 while (value--)
1653 gen_ashift (ASHIFTRT, 1, wrk);
1654 emit_move_insn (operands[0], wrk);
1655 return 1;
1656 }
1657 /* Expand a short sequence inline, longer call a magic routine. */
1658 else if (value <= 5)
1659 {
1660 wrk = gen_reg_rtx (SImode);
1661 emit_move_insn (wrk, operands[1]);
1662 while (value--)
1663 gen_ashift (ASHIFTRT, 1, wrk);
1664 emit_move_insn (operands[0], wrk);
1665 return 1;
1666 }
1667
1668 wrk = gen_reg_rtx (Pmode);
1669
1670 /* Load the value into an arg reg and call a helper. */
1671 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
1672 sprintf (func, "__ashiftrt_r4_%d", value);
1673 func_name = get_identifier (func);
1674 sym = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (func_name));
1675 emit_move_insn (wrk, sym);
1676 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
1677 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
1678 return 1;
1679 }
1680
1681 int
sh_dynamicalize_shift_p(count)1682 sh_dynamicalize_shift_p (count)
1683 rtx count;
1684 {
1685 return shift_insns[INTVAL (count)] > 1 + SH_DYNAMIC_SHIFT_COST;
1686 }
1687
1688 /* Try to find a good way to implement the combiner pattern
1689 [(set (match_operand:SI 0 "register_operand" "r")
1690 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1691 (match_operand:SI 2 "const_int_operand" "n"))
1692 (match_operand:SI 3 "const_int_operand" "n"))) .
1693 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1694 return 0 for simple right / left or left/right shift combination.
1695 return 1 for a combination of shifts with zero_extend.
1696 return 2 for a combination of shifts with an AND that needs r0.
1697 return 3 for a combination of shifts with an AND that needs an extra
1698 scratch register, when the three highmost bits of the AND mask are clear.
1699 return 4 for a combination of shifts with an AND that needs an extra
1700 scratch register, when any of the three highmost bits of the AND mask
1701 is set.
1702 If ATTRP is set, store an initial right shift width in ATTRP[0],
1703 and the instruction length in ATTRP[1] . These values are not valid
1704 when returning 0.
1705 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1706 shift_amounts for the last shift value that is to be used before the
1707 sign extend. */
1708 int
shl_and_kind(left_rtx,mask_rtx,attrp)1709 shl_and_kind (left_rtx, mask_rtx, attrp)
1710 rtx left_rtx, mask_rtx;
1711 int *attrp;
1712 {
1713 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
1714 int left = INTVAL (left_rtx), right;
1715 int best = 0;
1716 int cost, best_cost = 10000;
1717 int best_right = 0, best_len = 0;
1718 int i;
1719 int can_ext;
1720
1721 if (left < 0 || left > 31)
1722 return 0;
1723 if (GET_CODE (mask_rtx) == CONST_INT)
1724 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
1725 else
1726 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
1727 /* Can this be expressed as a right shift / left shift pair ? */
1728 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
1729 right = exact_log2 (lsb);
1730 mask2 = ~(mask + lsb - 1);
1731 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
1732 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1733 if (! mask2)
1734 best_cost = shift_insns[right] + shift_insns[right + left];
1735 /* mask has no trailing zeroes <==> ! right */
1736 else if (! right && mask2 == ~(lsb2 - 1))
1737 {
1738 int late_right = exact_log2 (lsb2);
1739 best_cost = shift_insns[left + late_right] + shift_insns[late_right];
1740 }
1741 /* Try to use zero extend */
1742 if (mask2 == ~(lsb2 - 1))
1743 {
1744 int width, first;
1745
1746 for (width = 8; width <= 16; width += 8)
1747 {
1748 /* Can we zero-extend right away? */
1749 if (lsb2 == (unsigned HOST_WIDE_INT)1 << width)
1750 {
1751 cost
1752 = 1 + ext_shift_insns[right] + ext_shift_insns[left + right];
1753 if (cost < best_cost)
1754 {
1755 best = 1;
1756 best_cost = cost;
1757 best_right = right;
1758 best_len = cost;
1759 if (attrp)
1760 attrp[2] = -1;
1761 }
1762 continue;
1763 }
1764 /* ??? Could try to put zero extend into initial right shift,
1765 or even shift a bit left before the right shift. */
1766 /* Determine value of first part of left shift, to get to the
1767 zero extend cut-off point. */
1768 first = width - exact_log2 (lsb2) + right;
1769 if (first >= 0 && right + left - first >= 0)
1770 {
1771 cost = ext_shift_insns[right] + ext_shift_insns[first] + 1
1772 + ext_shift_insns[right + left - first];
1773 if (cost < best_cost)
1774 {
1775 best = 1;
1776 best_cost = cost;
1777 best_right = right;
1778 best_len = cost;
1779 if (attrp)
1780 attrp[2] = first;
1781 }
1782 }
1783 }
1784 }
1785 /* Try to use r0 AND pattern */
1786 for (i = 0; i <= 2; i++)
1787 {
1788 if (i > right)
1789 break;
1790 if (! CONST_OK_FOR_L (mask >> i))
1791 continue;
1792 cost = (i != 0) + 2 + ext_shift_insns[left + i];
1793 if (cost < best_cost)
1794 {
1795 best = 2;
1796 best_cost = cost;
1797 best_right = i;
1798 best_len = cost - 1;
1799 }
1800 }
1801 /* Try to use a scratch register to hold the AND operand. */
1802 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT)3 << 30)) == 0;
1803 for (i = 0; i <= 2; i++)
1804 {
1805 if (i > right)
1806 break;
1807 cost = (i != 0) + (CONST_OK_FOR_I (mask >> i) ? 2 : 3)
1808 + (can_ext ? ext_shift_insns : shift_insns)[left + i];
1809 if (cost < best_cost)
1810 {
1811 best = 4 - can_ext;
1812 best_cost = cost;
1813 best_right = i;
1814 best_len = cost - 1 - ! CONST_OK_FOR_I (mask >> i);
1815 }
1816 }
1817
1818 if (attrp)
1819 {
1820 attrp[0] = best_right;
1821 attrp[1] = best_len;
1822 }
1823 return best;
1824 }
1825
1826 /* This is used in length attributes of the unnamed instructions
1827 corresponding to shl_and_kind return values of 1 and 2. */
1828 int
shl_and_length(insn)1829 shl_and_length (insn)
1830 rtx insn;
1831 {
1832 rtx set_src, left_rtx, mask_rtx;
1833 int attributes[3];
1834
1835 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1836 left_rtx = XEXP (XEXP (set_src, 0), 1);
1837 mask_rtx = XEXP (set_src, 1);
1838 shl_and_kind (left_rtx, mask_rtx, attributes);
1839 return attributes[1];
1840 }
1841
1842 /* This is used in length attribute of the and_shl_scratch instruction. */
1843
1844 int
shl_and_scr_length(insn)1845 shl_and_scr_length (insn)
1846 rtx insn;
1847 {
1848 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
1849 int len = shift_insns[INTVAL (XEXP (set_src, 1))];
1850 rtx op = XEXP (set_src, 0);
1851 len += shift_insns[INTVAL (XEXP (op, 1))] + 1;
1852 op = XEXP (XEXP (op, 0), 0);
1853 return len + shift_insns[INTVAL (XEXP (op, 1))];
1854 }
1855
1856 /* Generating rtl? */
1857 extern int rtx_equal_function_value_matters;
1858
1859 /* Generate rtl for instructions for which shl_and_kind advised a particular
1860 method of generating them, i.e. returned zero. */
1861
1862 int
gen_shl_and(dest,left_rtx,mask_rtx,source)1863 gen_shl_and (dest, left_rtx, mask_rtx, source)
1864 rtx dest, left_rtx, mask_rtx, source;
1865 {
1866 int attributes[3];
1867 unsigned HOST_WIDE_INT mask;
1868 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
1869 int right, total_shift;
1870 void (*shift_gen_fun) PARAMS ((int, rtx*)) = gen_shifty_hi_op;
1871
1872 right = attributes[0];
1873 total_shift = INTVAL (left_rtx) + right;
1874 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
1875 switch (kind)
1876 {
1877 default:
1878 return -1;
1879 case 1:
1880 {
1881 int first = attributes[2];
1882 rtx operands[3];
1883
1884 if (first < 0)
1885 {
1886 emit_insn ((mask << right) <= 0xff
1887 ? gen_zero_extendqisi2(dest,
1888 gen_lowpart (QImode, source))
1889 : gen_zero_extendhisi2(dest,
1890 gen_lowpart (HImode, source)));
1891 source = dest;
1892 }
1893 if (source != dest)
1894 emit_insn (gen_movsi (dest, source));
1895 operands[0] = dest;
1896 if (right)
1897 {
1898 operands[2] = GEN_INT (right);
1899 gen_shifty_hi_op (LSHIFTRT, operands);
1900 }
1901 if (first > 0)
1902 {
1903 operands[2] = GEN_INT (first);
1904 gen_shifty_hi_op (ASHIFT, operands);
1905 total_shift -= first;
1906 mask <<= first;
1907 }
1908 if (first >= 0)
1909 emit_insn (mask <= 0xff
1910 ? gen_zero_extendqisi2(dest, gen_lowpart (QImode, dest))
1911 : gen_zero_extendhisi2(dest, gen_lowpart (HImode, dest)));
1912 if (total_shift > 0)
1913 {
1914 operands[2] = GEN_INT (total_shift);
1915 gen_shifty_hi_op (ASHIFT, operands);
1916 }
1917 break;
1918 }
1919 case 4:
1920 shift_gen_fun = gen_shifty_op;
1921 case 3:
1922 /* If the topmost bit that matters is set, set the topmost bits
1923 that don't matter. This way, we might be able to get a shorter
1924 signed constant. */
1925 if (mask & ((HOST_WIDE_INT)1 << (31 - total_shift)))
1926 mask |= (HOST_WIDE_INT)~0 << (31 - total_shift);
1927 case 2:
1928 /* Don't expand fine-grained when combining, because that will
1929 make the pattern fail. */
1930 if (rtx_equal_function_value_matters
1931 || reload_in_progress || reload_completed)
1932 {
1933 rtx operands[3];
1934
1935 /* Cases 3 and 4 should be handled by this split
1936 only while combining */
1937 if (kind > 2)
1938 abort ();
1939 if (right)
1940 {
1941 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
1942 source = dest;
1943 }
1944 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
1945 if (total_shift)
1946 {
1947 operands[0] = dest;
1948 operands[1] = dest;
1949 operands[2] = GEN_INT (total_shift);
1950 shift_gen_fun (ASHIFT, operands);
1951 }
1952 break;
1953 }
1954 else
1955 {
1956 int neg = 0;
1957 if (kind != 4 && total_shift < 16)
1958 {
1959 neg = -ext_shift_amounts[total_shift][1];
1960 if (neg > 0)
1961 neg -= ext_shift_amounts[total_shift][2];
1962 else
1963 neg = 0;
1964 }
1965 emit_insn (gen_and_shl_scratch (dest, source,
1966 GEN_INT (right),
1967 GEN_INT (mask),
1968 GEN_INT (total_shift + neg),
1969 GEN_INT (neg)));
1970 emit_insn (gen_movsi (dest, dest));
1971 break;
1972 }
1973 }
1974 return 0;
1975 }
1976
1977 /* Try to find a good way to implement the combiner pattern
1978 [(set (match_operand:SI 0 "register_operand" "=r")
1979 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1980 (match_operand:SI 2 "const_int_operand" "n")
1981 (match_operand:SI 3 "const_int_operand" "n")
1982 (const_int 0)))
1983 (clobber (reg:SI T_REG))]
1984 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1985 return 0 for simple left / right shift combination.
1986 return 1 for left shift / 8 bit sign extend / left shift.
1987 return 2 for left shift / 16 bit sign extend / left shift.
1988 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1989 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1990 return 5 for left shift / 16 bit sign extend / right shift
1991 return 6 for < 8 bit sign extend / left shift.
1992 return 7 for < 8 bit sign extend / left shift / single right shift.
1993 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1994
1995 int
shl_sext_kind(left_rtx,size_rtx,costp)1996 shl_sext_kind (left_rtx, size_rtx, costp)
1997 rtx left_rtx, size_rtx;
1998 int *costp;
1999 {
2000 int left, size, insize, ext;
2001 int cost, best_cost;
2002 int kind;
2003
2004 left = INTVAL (left_rtx);
2005 size = INTVAL (size_rtx);
2006 insize = size - left;
2007 if (insize <= 0)
2008 abort ();
2009 /* Default to left / right shift. */
2010 kind = 0;
2011 best_cost = shift_insns[32 - insize] + ashiftrt_insns[32 - size];
2012 if (size <= 16)
2013 {
2014 /* 16 bit shift / sign extend / 16 bit shift */
2015 cost = shift_insns[16 - insize] + 1 + ashiftrt_insns[16 - size];
2016 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2017 below, by alternative 3 or something even better. */
2018 if (cost < best_cost)
2019 {
2020 kind = 5;
2021 best_cost = cost;
2022 }
2023 }
2024 /* Try a plain sign extend between two shifts. */
2025 for (ext = 16; ext >= insize; ext -= 8)
2026 {
2027 if (ext <= size)
2028 {
2029 cost = ext_shift_insns[ext - insize] + 1 + shift_insns[size - ext];
2030 if (cost < best_cost)
2031 {
2032 kind = ext / (unsigned) 8;
2033 best_cost = cost;
2034 }
2035 }
2036 /* Check if we can do a sloppy shift with a final signed shift
2037 restoring the sign. */
2038 if (EXT_SHIFT_SIGNED (size - ext))
2039 cost = ext_shift_insns[ext - insize] + ext_shift_insns[size - ext] + 1;
2040 /* If not, maybe it's still cheaper to do the second shift sloppy,
2041 and do a final sign extend? */
2042 else if (size <= 16)
2043 cost = ext_shift_insns[ext - insize] + 1
2044 + ext_shift_insns[size > ext ? size - ext : ext - size] + 1;
2045 else
2046 continue;
2047 if (cost < best_cost)
2048 {
2049 kind = ext / (unsigned) 8 + 2;
2050 best_cost = cost;
2051 }
2052 }
2053 /* Check if we can sign extend in r0 */
2054 if (insize < 8)
2055 {
2056 cost = 3 + shift_insns[left];
2057 if (cost < best_cost)
2058 {
2059 kind = 6;
2060 best_cost = cost;
2061 }
2062 /* Try the same with a final signed shift. */
2063 if (left < 31)
2064 {
2065 cost = 3 + ext_shift_insns[left + 1] + 1;
2066 if (cost < best_cost)
2067 {
2068 kind = 7;
2069 best_cost = cost;
2070 }
2071 }
2072 }
2073 if (TARGET_SH3)
2074 {
2075 /* Try to use a dynamic shift. */
2076 cost = shift_insns[32 - insize] + 1 + SH_DYNAMIC_SHIFT_COST;
2077 if (cost < best_cost)
2078 {
2079 kind = 0;
2080 best_cost = cost;
2081 }
2082 }
2083 if (costp)
2084 *costp = best_cost;
2085 return kind;
2086 }
2087
2088 /* Function to be used in the length attribute of the instructions
2089 implementing this pattern. */
2090
2091 int
shl_sext_length(insn)2092 shl_sext_length (insn)
2093 rtx insn;
2094 {
2095 rtx set_src, left_rtx, size_rtx;
2096 int cost;
2097
2098 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
2099 left_rtx = XEXP (XEXP (set_src, 0), 1);
2100 size_rtx = XEXP (set_src, 1);
2101 shl_sext_kind (left_rtx, size_rtx, &cost);
2102 return cost;
2103 }
2104
2105 /* Generate rtl for this pattern */
2106
2107 int
gen_shl_sext(dest,left_rtx,size_rtx,source)2108 gen_shl_sext (dest, left_rtx, size_rtx, source)
2109 rtx dest, left_rtx, size_rtx, source;
2110 {
2111 int kind;
2112 int left, size, insize, cost;
2113 rtx operands[3];
2114
2115 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
2116 left = INTVAL (left_rtx);
2117 size = INTVAL (size_rtx);
2118 insize = size - left;
2119 switch (kind)
2120 {
2121 case 1:
2122 case 2:
2123 case 3:
2124 case 4:
2125 {
2126 int ext = kind & 1 ? 8 : 16;
2127 int shift2 = size - ext;
2128
2129 /* Don't expand fine-grained when combining, because that will
2130 make the pattern fail. */
2131 if (! rtx_equal_function_value_matters
2132 && ! reload_in_progress && ! reload_completed)
2133 {
2134 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2135 emit_insn (gen_movsi (dest, source));
2136 break;
2137 }
2138 if (dest != source)
2139 emit_insn (gen_movsi (dest, source));
2140 operands[0] = dest;
2141 if (ext - insize)
2142 {
2143 operands[2] = GEN_INT (ext - insize);
2144 gen_shifty_hi_op (ASHIFT, operands);
2145 }
2146 emit_insn (kind & 1
2147 ? gen_extendqisi2(dest, gen_lowpart (QImode, dest))
2148 : gen_extendhisi2(dest, gen_lowpart (HImode, dest)));
2149 if (kind <= 2)
2150 {
2151 if (shift2)
2152 {
2153 operands[2] = GEN_INT (shift2);
2154 gen_shifty_op (ASHIFT, operands);
2155 }
2156 }
2157 else
2158 {
2159 if (shift2 > 0)
2160 {
2161 if (EXT_SHIFT_SIGNED (shift2))
2162 {
2163 operands[2] = GEN_INT (shift2 + 1);
2164 gen_shifty_op (ASHIFT, operands);
2165 operands[2] = GEN_INT (1);
2166 gen_shifty_op (ASHIFTRT, operands);
2167 break;
2168 }
2169 operands[2] = GEN_INT (shift2);
2170 gen_shifty_hi_op (ASHIFT, operands);
2171 }
2172 else if (shift2)
2173 {
2174 operands[2] = GEN_INT (-shift2);
2175 gen_shifty_hi_op (LSHIFTRT, operands);
2176 }
2177 emit_insn (size <= 8
2178 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
2179 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2180 }
2181 break;
2182 }
2183 case 5:
2184 {
2185 int i = 16 - size;
2186 if (! rtx_equal_function_value_matters
2187 && ! reload_in_progress && ! reload_completed)
2188 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2189 else
2190 {
2191 operands[0] = dest;
2192 operands[2] = GEN_INT (16 - insize);
2193 gen_shifty_hi_op (ASHIFT, operands);
2194 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
2195 }
2196 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2197 while (--i >= 0)
2198 gen_ashift (ASHIFTRT, 1, dest);
2199 break;
2200 }
2201 case 6:
2202 case 7:
2203 /* Don't expand fine-grained when combining, because that will
2204 make the pattern fail. */
2205 if (! rtx_equal_function_value_matters
2206 && ! reload_in_progress && ! reload_completed)
2207 {
2208 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
2209 emit_insn (gen_movsi (dest, source));
2210 break;
2211 }
2212 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
2213 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
2214 emit_insn (gen_addsi3 (dest, dest, GEN_INT (-1 << (insize - 1))));
2215 operands[0] = dest;
2216 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
2217 gen_shifty_op (ASHIFT, operands);
2218 if (kind == 7)
2219 emit_insn (gen_ashrsi3_k (dest, dest, GEN_INT (1)));
2220 break;
2221 default:
2222 return -1;
2223 }
2224 return 0;
2225 }
2226
2227 /* Prefix a symbol_ref name with "datalabel". */
2228
2229 rtx
gen_datalabel_ref(sym)2230 gen_datalabel_ref (sym)
2231 rtx sym;
2232 {
2233 if (GET_CODE (sym) == LABEL_REF)
2234 return gen_rtx_CONST (GET_MODE (sym),
2235 gen_rtx_UNSPEC (GET_MODE (sym),
2236 gen_rtvec (1, sym),
2237 UNSPEC_DATALABEL));
2238
2239 if (GET_CODE (sym) != SYMBOL_REF)
2240 abort ();
2241
2242 XSTR (sym, 0) = concat (SH_DATALABEL_ENCODING, XSTR (sym, 0), NULL);
2243
2244 return sym;
2245 }
2246
2247
2248 /* The SH cannot load a large constant into a register, constants have to
2249 come from a pc relative load. The reference of a pc relative load
2250 instruction must be less than 1k infront of the instruction. This
2251 means that we often have to dump a constant inside a function, and
2252 generate code to branch around it.
2253
2254 It is important to minimize this, since the branches will slow things
2255 down and make things bigger.
2256
2257 Worst case code looks like:
2258
2259 mov.l L1,rn
2260 bra L2
2261 nop
2262 align
2263 L1: .long value
2264 L2:
2265 ..
2266
2267 mov.l L3,rn
2268 bra L4
2269 nop
2270 align
2271 L3: .long value
2272 L4:
2273 ..
2274
2275 We fix this by performing a scan before scheduling, which notices which
2276 instructions need to have their operands fetched from the constant table
2277 and builds the table.
2278
2279 The algorithm is:
2280
2281 scan, find an instruction which needs a pcrel move. Look forward, find the
2282 last barrier which is within MAX_COUNT bytes of the requirement.
2283 If there isn't one, make one. Process all the instructions between
2284 the find and the barrier.
2285
2286 In the above example, we can tell that L3 is within 1k of L1, so
2287 the first move can be shrunk from the 3 insn+constant sequence into
2288 just 1 insn, and the constant moved to L3 to make:
2289
2290 mov.l L1,rn
2291 ..
2292 mov.l L3,rn
2293 bra L4
2294 nop
2295 align
2296 L3:.long value
2297 L4:.long value
2298
2299 Then the second move becomes the target for the shortening process. */
2300
2301 typedef struct
2302 {
2303 rtx value; /* Value in table. */
2304 rtx label; /* Label of value. */
2305 rtx wend; /* End of window. */
2306 enum machine_mode mode; /* Mode of value. */
2307
2308 /* True if this constant is accessed as part of a post-increment
2309 sequence. Note that HImode constants are never accessed in this way. */
2310 bool part_of_sequence_p;
2311 } pool_node;
2312
2313 /* The maximum number of constants that can fit into one pool, since
2314 the pc relative range is 0...1020 bytes and constants are at least 4
2315 bytes long. */
2316
2317 #define MAX_POOL_SIZE (1020/4)
2318 static pool_node pool_vector[MAX_POOL_SIZE];
2319 static int pool_size;
2320 static rtx pool_window_label;
2321 static int pool_window_last;
2322
2323 /* ??? If we need a constant in HImode which is the truncated value of a
2324 constant we need in SImode, we could combine the two entries thus saving
2325 two bytes. Is this common enough to be worth the effort of implementing
2326 it? */
2327
2328 /* ??? This stuff should be done at the same time that we shorten branches.
2329 As it is now, we must assume that all branches are the maximum size, and
2330 this causes us to almost always output constant pools sooner than
2331 necessary. */
2332
2333 /* Add a constant to the pool and return its label. */
2334
2335 static rtx
add_constant(x,mode,last_value)2336 add_constant (x, mode, last_value)
2337 rtx x;
2338 enum machine_mode mode;
2339 rtx last_value;
2340 {
2341 int i;
2342 rtx lab, new, ref, newref;
2343
2344 /* First see if we've already got it. */
2345 for (i = 0; i < pool_size; i++)
2346 {
2347 if (x->code == pool_vector[i].value->code
2348 && mode == pool_vector[i].mode)
2349 {
2350 if (x->code == CODE_LABEL)
2351 {
2352 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
2353 continue;
2354 }
2355 if (rtx_equal_p (x, pool_vector[i].value))
2356 {
2357 lab = new = 0;
2358 if (! last_value
2359 || ! i
2360 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
2361 {
2362 new = gen_label_rtx ();
2363 LABEL_REFS (new) = pool_vector[i].label;
2364 pool_vector[i].label = lab = new;
2365 }
2366 if (lab && pool_window_label)
2367 {
2368 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2369 ref = pool_vector[pool_window_last].wend;
2370 LABEL_NEXTREF (newref) = ref;
2371 pool_vector[pool_window_last].wend = newref;
2372 }
2373 if (new)
2374 pool_window_label = new;
2375 pool_window_last = i;
2376 return lab;
2377 }
2378 }
2379 }
2380
2381 /* Need a new one. */
2382 pool_vector[pool_size].value = x;
2383 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
2384 {
2385 lab = 0;
2386 pool_vector[pool_size - 1].part_of_sequence_p = true;
2387 }
2388 else
2389 lab = gen_label_rtx ();
2390 pool_vector[pool_size].mode = mode;
2391 pool_vector[pool_size].label = lab;
2392 pool_vector[pool_size].wend = NULL_RTX;
2393 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
2394 if (lab && pool_window_label)
2395 {
2396 newref = gen_rtx_LABEL_REF (VOIDmode, pool_window_label);
2397 ref = pool_vector[pool_window_last].wend;
2398 LABEL_NEXTREF (newref) = ref;
2399 pool_vector[pool_window_last].wend = newref;
2400 }
2401 if (lab)
2402 pool_window_label = lab;
2403 pool_window_last = pool_size;
2404 pool_size++;
2405 return lab;
2406 }
2407
2408 /* Output the literal table. */
2409
2410 static void
dump_table(scan)2411 dump_table (scan)
2412 rtx scan;
2413 {
2414 int i;
2415 int need_align = 1;
2416 rtx lab, ref;
2417 int have_df = 0;
2418
2419 /* Do two passes, first time dump out the HI sized constants. */
2420
2421 for (i = 0; i < pool_size; i++)
2422 {
2423 pool_node *p = &pool_vector[i];
2424
2425 if (p->mode == HImode)
2426 {
2427 if (need_align)
2428 {
2429 scan = emit_insn_after (gen_align_2 (), scan);
2430 need_align = 0;
2431 }
2432 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2433 scan = emit_label_after (lab, scan);
2434 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
2435 scan);
2436 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2437 {
2438 lab = XEXP (ref, 0);
2439 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2440 }
2441 }
2442 else if (p->mode == DFmode)
2443 have_df = 1;
2444 }
2445
2446 need_align = 1;
2447
2448 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
2449 {
2450 rtx align_insn = NULL_RTX;
2451
2452 scan = emit_label_after (gen_label_rtx (), scan);
2453 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2454 need_align = 0;
2455
2456 for (i = 0; i < pool_size; i++)
2457 {
2458 pool_node *p = &pool_vector[i];
2459
2460 switch (p->mode)
2461 {
2462 case HImode:
2463 break;
2464 case SImode:
2465 case SFmode:
2466 if (align_insn && !p->part_of_sequence_p)
2467 {
2468 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2469 emit_label_before (lab, align_insn);
2470 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
2471 align_insn);
2472 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2473 {
2474 lab = XEXP (ref, 0);
2475 emit_insn_before (gen_consttable_window_end (lab),
2476 align_insn);
2477 }
2478 delete_insn (align_insn);
2479 align_insn = NULL_RTX;
2480 continue;
2481 }
2482 else
2483 {
2484 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2485 scan = emit_label_after (lab, scan);
2486 scan = emit_insn_after (gen_consttable_4 (p->value,
2487 const0_rtx), scan);
2488 need_align = ! need_align;
2489 }
2490 break;
2491 case DFmode:
2492 if (need_align)
2493 {
2494 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
2495 align_insn = scan;
2496 need_align = 0;
2497 }
2498 case DImode:
2499 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2500 scan = emit_label_after (lab, scan);
2501 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2502 scan);
2503 break;
2504 default:
2505 abort ();
2506 break;
2507 }
2508
2509 if (p->mode != HImode)
2510 {
2511 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2512 {
2513 lab = XEXP (ref, 0);
2514 scan = emit_insn_after (gen_consttable_window_end (lab),
2515 scan);
2516 }
2517 }
2518 }
2519
2520 pool_size = 0;
2521 }
2522
2523 for (i = 0; i < pool_size; i++)
2524 {
2525 pool_node *p = &pool_vector[i];
2526
2527 switch (p->mode)
2528 {
2529 case HImode:
2530 break;
2531 case SImode:
2532 case SFmode:
2533 if (need_align)
2534 {
2535 need_align = 0;
2536 scan = emit_label_after (gen_label_rtx (), scan);
2537 scan = emit_insn_after (gen_align_4 (), scan);
2538 }
2539 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2540 scan = emit_label_after (lab, scan);
2541 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
2542 scan);
2543 break;
2544 case DFmode:
2545 case DImode:
2546 if (need_align)
2547 {
2548 need_align = 0;
2549 scan = emit_label_after (gen_label_rtx (), scan);
2550 scan = emit_insn_after (gen_align_4 (), scan);
2551 }
2552 for (lab = p->label; lab; lab = LABEL_REFS (lab))
2553 scan = emit_label_after (lab, scan);
2554 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
2555 scan);
2556 break;
2557 default:
2558 abort ();
2559 break;
2560 }
2561
2562 if (p->mode != HImode)
2563 {
2564 for (ref = p->wend; ref; ref = LABEL_NEXTREF (ref))
2565 {
2566 lab = XEXP (ref, 0);
2567 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
2568 }
2569 }
2570 }
2571
2572 scan = emit_insn_after (gen_consttable_end (), scan);
2573 scan = emit_barrier_after (scan);
2574 pool_size = 0;
2575 pool_window_label = NULL_RTX;
2576 pool_window_last = 0;
2577 }
2578
2579 /* Return nonzero if constant would be an ok source for a
2580 mov.w instead of a mov.l. */
2581
2582 static int
hi_const(src)2583 hi_const (src)
2584 rtx src;
2585 {
2586 return (GET_CODE (src) == CONST_INT
2587 && INTVAL (src) >= -32768
2588 && INTVAL (src) <= 32767);
2589 }
2590
2591 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2592
2593 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2594 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2595 need to fix it if the input value is CONST_OK_FOR_I. */
2596
2597 static int
broken_move(insn)2598 broken_move (insn)
2599 rtx insn;
2600 {
2601 if (GET_CODE (insn) == INSN)
2602 {
2603 rtx pat = PATTERN (insn);
2604 if (GET_CODE (pat) == PARALLEL)
2605 pat = XVECEXP (pat, 0, 0);
2606 if (GET_CODE (pat) == SET
2607 /* We can load any 8 bit value if we don't care what the high
2608 order bits end up as. */
2609 && GET_MODE (SET_DEST (pat)) != QImode
2610 && (CONSTANT_P (SET_SRC (pat))
2611 /* Match mova_const. */
2612 || (GET_CODE (SET_SRC (pat)) == UNSPEC
2613 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
2614 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
2615 && ! (TARGET_SH3E
2616 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
2617 && (fp_zero_operand (SET_SRC (pat))
2618 || fp_one_operand (SET_SRC (pat)))
2619 /* ??? If this is a -m4 or -m4-single compilation, in general
2620 we don't know the current setting of fpscr, so disable fldi.
2621 There is an exception if this was a register-register move
2622 before reload - and hence it was ascertained that we have
2623 single precision setting - and in a post-reload optimization
2624 we changed this to do a constant load. In that case
2625 we don't have an r0 clobber, hence we must use fldi. */
2626 && (! TARGET_SH4 || TARGET_FMOVD
2627 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
2628 == SCRATCH))
2629 && GET_CODE (SET_DEST (pat)) == REG
2630 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
2631 && (GET_CODE (SET_SRC (pat)) != CONST_INT
2632 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat)))))
2633 return 1;
2634 }
2635
2636 return 0;
2637 }
2638
2639 static int
mova_p(insn)2640 mova_p (insn)
2641 rtx insn;
2642 {
2643 return (GET_CODE (insn) == INSN
2644 && GET_CODE (PATTERN (insn)) == SET
2645 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
2646 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
2647 /* Don't match mova_const. */
2648 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn)), 0, 0)) == LABEL_REF);
2649 }
2650
2651 /* Find the last barrier from insn FROM which is close enough to hold the
2652 constant pool. If we can't find one, then create one near the end of
2653 the range. */
2654
2655 static rtx
find_barrier(num_mova,mova,from)2656 find_barrier (num_mova, mova, from)
2657 int num_mova;
2658 rtx mova, from;
2659 {
2660 int count_si = 0;
2661 int count_hi = 0;
2662 int found_hi = 0;
2663 int found_si = 0;
2664 int found_di = 0;
2665 int hi_align = 2;
2666 int si_align = 2;
2667 int leading_mova = num_mova;
2668 rtx barrier_before_mova = 0, found_barrier = 0, good_barrier = 0;
2669 int si_limit;
2670 int hi_limit;
2671
2672 /* For HImode: range is 510, add 4 because pc counts from address of
2673 second instruction after this one, subtract 2 for the jump instruction
2674 that we may need to emit before the table, subtract 2 for the instruction
2675 that fills the jump delay slot (in very rare cases, reorg will take an
2676 instruction from after the constant pool or will leave the delay slot
2677 empty). This gives 510.
2678 For SImode: range is 1020, add 4 because pc counts from address of
2679 second instruction after this one, subtract 2 in case pc is 2 byte
2680 aligned, subtract 2 for the jump instruction that we may need to emit
2681 before the table, subtract 2 for the instruction that fills the jump
2682 delay slot. This gives 1018. */
2683
2684 /* The branch will always be shortened now that the reference address for
2685 forward branches is the successor address, thus we need no longer make
2686 adjustments to the [sh]i_limit for -O0. */
2687
2688 si_limit = 1018;
2689 hi_limit = 510;
2690 #if defined(OPENBSD_NATIVE) || defined(OPENBSD_CROSS)
2691 si_limit -= flag_pic ? 16 : 8;
2692 hi_limit -= flag_pic ? 16 : 8;
2693 #endif
2694
2695 while (from && count_si < si_limit && count_hi < hi_limit)
2696 {
2697 int inc = get_attr_length (from);
2698 int new_align = 1;
2699
2700 if (GET_CODE (from) == CODE_LABEL)
2701 {
2702 if (optimize)
2703 new_align = 1 << label_to_alignment (from);
2704 else if (GET_CODE (prev_nonnote_insn (from)) == BARRIER)
2705 new_align = 1 << barrier_align (from);
2706 else
2707 new_align = 1;
2708 inc = 0;
2709 }
2710
2711 if (GET_CODE (from) == BARRIER)
2712 {
2713
2714 found_barrier = from;
2715
2716 /* If we are at the end of the function, or in front of an alignment
2717 instruction, we need not insert an extra alignment. We prefer
2718 this kind of barrier. */
2719 if (barrier_align (from) > 2)
2720 good_barrier = from;
2721 }
2722
2723 if (broken_move (from))
2724 {
2725 rtx pat, src, dst;
2726 enum machine_mode mode;
2727
2728 pat = PATTERN (from);
2729 if (GET_CODE (pat) == PARALLEL)
2730 pat = XVECEXP (pat, 0, 0);
2731 src = SET_SRC (pat);
2732 dst = SET_DEST (pat);
2733 mode = GET_MODE (dst);
2734
2735 /* We must explicitly check the mode, because sometimes the
2736 front end will generate code to load unsigned constants into
2737 HImode targets without properly sign extending them. */
2738 if (mode == HImode
2739 || (mode == SImode && hi_const (src) && REGNO (dst) != FPUL_REG))
2740 {
2741 found_hi += 2;
2742 /* We put the short constants before the long constants, so
2743 we must count the length of short constants in the range
2744 for the long constants. */
2745 /* ??? This isn't optimal, but is easy to do. */
2746 si_limit -= 2;
2747 }
2748 else
2749 {
2750 /* We dump DF/DI constants before SF/SI ones, because
2751 the limit is the same, but the alignment requirements
2752 are higher. We may waste up to 4 additional bytes
2753 for alignment, and the DF/DI constant may have
2754 another SF/SI constant placed before it. */
2755 if (TARGET_SHCOMPACT
2756 && ! found_di
2757 && (mode == DFmode || mode == DImode))
2758 {
2759 found_di = 1;
2760 si_limit -= 8;
2761 }
2762 while (si_align > 2 && found_si + si_align - 2 > count_si)
2763 si_align >>= 1;
2764 if (found_si > count_si)
2765 count_si = found_si;
2766 found_si += GET_MODE_SIZE (mode);
2767 if (num_mova)
2768 si_limit -= GET_MODE_SIZE (mode);
2769 }
2770
2771 /* See the code in machine_dependent_reorg, which has a similar if
2772 statement that generates a new mova insn in many cases. */
2773 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
2774 inc += 2;
2775 }
2776
2777 if (mova_p (from))
2778 {
2779 if (! num_mova++)
2780 {
2781 leading_mova = 0;
2782 mova = from;
2783 barrier_before_mova = good_barrier ? good_barrier : found_barrier;
2784 }
2785 if (found_si > count_si)
2786 count_si = found_si;
2787 }
2788 else if (GET_CODE (from) == JUMP_INSN
2789 && (GET_CODE (PATTERN (from)) == ADDR_VEC
2790 || GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
2791 {
2792 if (num_mova)
2793 num_mova--;
2794 if (barrier_align (next_real_insn (from)) == align_jumps_log)
2795 {
2796 /* We have just passed the barrier in front of the
2797 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2798 the ADDR_DIFF_VEC is accessed as data, just like our pool
2799 constants, this is a good opportunity to accommodate what
2800 we have gathered so far.
2801 If we waited any longer, we could end up at a barrier in
2802 front of code, which gives worse cache usage for separated
2803 instruction / data caches. */
2804 good_barrier = found_barrier;
2805 break;
2806 }
2807 else
2808 {
2809 rtx body = PATTERN (from);
2810 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
2811 }
2812 }
2813 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2814 else if (GET_CODE (from) == JUMP_INSN
2815 && ! TARGET_SH2
2816 && ! TARGET_SMALLCODE)
2817 new_align = 4;
2818
2819 if (found_si)
2820 {
2821 count_si += inc;
2822 if (new_align > si_align)
2823 {
2824 si_limit -= (count_si - 1) & (new_align - si_align);
2825 si_align = new_align;
2826 }
2827 count_si = (count_si + new_align - 1) & -new_align;
2828 }
2829 if (found_hi)
2830 {
2831 count_hi += inc;
2832 if (new_align > hi_align)
2833 {
2834 hi_limit -= (count_hi - 1) & (new_align - hi_align);
2835 hi_align = new_align;
2836 }
2837 count_hi = (count_hi + new_align - 1) & -new_align;
2838 }
2839 from = NEXT_INSN (from);
2840 }
2841
2842 if (num_mova)
2843 {
2844 if (leading_mova)
2845 {
2846 /* Try as we might, the leading mova is out of range. Change
2847 it into a load (which will become a pcload) and retry. */
2848 SET_SRC (PATTERN (mova)) = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
2849 INSN_CODE (mova) = -1;
2850 return find_barrier (0, 0, mova);
2851 }
2852 else
2853 {
2854 /* Insert the constant pool table before the mova instruction,
2855 to prevent the mova label reference from going out of range. */
2856 from = mova;
2857 good_barrier = found_barrier = barrier_before_mova;
2858 }
2859 }
2860
2861 if (found_barrier)
2862 {
2863 if (good_barrier && next_real_insn (found_barrier))
2864 found_barrier = good_barrier;
2865 }
2866 else
2867 {
2868 /* We didn't find a barrier in time to dump our stuff,
2869 so we'll make one. */
2870 rtx label = gen_label_rtx ();
2871
2872 /* If we exceeded the range, then we must back up over the last
2873 instruction we looked at. Otherwise, we just need to undo the
2874 NEXT_INSN at the end of the loop. */
2875 if (count_hi > hi_limit || count_si > si_limit)
2876 from = PREV_INSN (PREV_INSN (from));
2877 else
2878 from = PREV_INSN (from);
2879
2880 /* Walk back to be just before any jump or label.
2881 Putting it before a label reduces the number of times the branch
2882 around the constant pool table will be hit. Putting it before
2883 a jump makes it more likely that the bra delay slot will be
2884 filled. */
2885 while (GET_CODE (from) == JUMP_INSN || GET_CODE (from) == NOTE
2886 || GET_CODE (from) == CODE_LABEL)
2887 from = PREV_INSN (from);
2888
2889 from = emit_jump_insn_after (gen_jump (label), from);
2890 JUMP_LABEL (from) = label;
2891 LABEL_NUSES (label) = 1;
2892 found_barrier = emit_barrier_after (from);
2893 emit_label_after (label, found_barrier);
2894 }
2895
2896 return found_barrier;
2897 }
2898
2899 /* If the instruction INSN is implemented by a special function, and we can
2900 positively find the register that is used to call the sfunc, and this
2901 register is not used anywhere else in this instruction - except as the
2902 destination of a set, return this register; else, return 0. */
2903 rtx
sfunc_uses_reg(insn)2904 sfunc_uses_reg (insn)
2905 rtx insn;
2906 {
2907 int i;
2908 rtx pattern, part, reg_part, reg;
2909
2910 if (GET_CODE (insn) != INSN)
2911 return 0;
2912 pattern = PATTERN (insn);
2913 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
2914 return 0;
2915
2916 for (reg_part = 0, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2917 {
2918 part = XVECEXP (pattern, 0, i);
2919 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
2920 reg_part = part;
2921 }
2922 if (! reg_part)
2923 return 0;
2924 reg = XEXP (reg_part, 0);
2925 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
2926 {
2927 part = XVECEXP (pattern, 0, i);
2928 if (part == reg_part || GET_CODE (part) == CLOBBER)
2929 continue;
2930 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
2931 && GET_CODE (SET_DEST (part)) == REG)
2932 ? SET_SRC (part) : part)))
2933 return 0;
2934 }
2935 return reg;
2936 }
2937
2938 /* See if the only way in which INSN uses REG is by calling it, or by
2939 setting it while calling it. Set *SET to a SET rtx if the register
2940 is set by INSN. */
2941
2942 static int
noncall_uses_reg(reg,insn,set)2943 noncall_uses_reg (reg, insn, set)
2944 rtx reg;
2945 rtx insn;
2946 rtx *set;
2947 {
2948 rtx pattern, reg2;
2949
2950 *set = NULL_RTX;
2951
2952 reg2 = sfunc_uses_reg (insn);
2953 if (reg2 && REGNO (reg2) == REGNO (reg))
2954 {
2955 pattern = single_set (insn);
2956 if (pattern
2957 && GET_CODE (SET_DEST (pattern)) == REG
2958 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2959 *set = pattern;
2960 return 0;
2961 }
2962 if (GET_CODE (insn) != CALL_INSN)
2963 {
2964 /* We don't use rtx_equal_p because we don't care if the mode is
2965 different. */
2966 pattern = single_set (insn);
2967 if (pattern
2968 && GET_CODE (SET_DEST (pattern)) == REG
2969 && REGNO (reg) == REGNO (SET_DEST (pattern)))
2970 {
2971 rtx par, part;
2972 int i;
2973
2974 *set = pattern;
2975 par = PATTERN (insn);
2976 if (GET_CODE (par) == PARALLEL)
2977 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
2978 {
2979 part = XVECEXP (par, 0, i);
2980 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
2981 return 1;
2982 }
2983 return reg_mentioned_p (reg, SET_SRC (pattern));
2984 }
2985
2986 return 1;
2987 }
2988
2989 pattern = PATTERN (insn);
2990
2991 if (GET_CODE (pattern) == PARALLEL)
2992 {
2993 int i;
2994
2995 for (i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
2996 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
2997 return 1;
2998 pattern = XVECEXP (pattern, 0, 0);
2999 }
3000
3001 if (GET_CODE (pattern) == SET)
3002 {
3003 if (reg_mentioned_p (reg, SET_DEST (pattern)))
3004 {
3005 /* We don't use rtx_equal_p, because we don't care if the
3006 mode is different. */
3007 if (GET_CODE (SET_DEST (pattern)) != REG
3008 || REGNO (reg) != REGNO (SET_DEST (pattern)))
3009 return 1;
3010
3011 *set = pattern;
3012 }
3013
3014 pattern = SET_SRC (pattern);
3015 }
3016
3017 if (GET_CODE (pattern) != CALL
3018 || GET_CODE (XEXP (pattern, 0)) != MEM
3019 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
3020 return 1;
3021
3022 return 0;
3023 }
3024
3025 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3026 general registers. Bits 0..15 mean that the respective registers
3027 are used as inputs in the instruction. Bits 16..31 mean that the
3028 registers 0..15, respectively, are used as outputs, or are clobbered.
3029 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3030 int
regs_used(x,is_dest)3031 regs_used (x, is_dest)
3032 rtx x; int is_dest;
3033 {
3034 enum rtx_code code;
3035 const char *fmt;
3036 int i, used = 0;
3037
3038 if (! x)
3039 return used;
3040 code = GET_CODE (x);
3041 switch (code)
3042 {
3043 case REG:
3044 if (REGNO (x) < 16)
3045 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3046 << (REGNO (x) + is_dest));
3047 return 0;
3048 case SUBREG:
3049 {
3050 rtx y = SUBREG_REG (x);
3051
3052 if (GET_CODE (y) != REG)
3053 break;
3054 if (REGNO (y) < 16)
3055 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x))) - 1)
3056 << (REGNO (y) +
3057 subreg_regno_offset (REGNO (y),
3058 GET_MODE (y),
3059 SUBREG_BYTE (x),
3060 GET_MODE (x)) + is_dest));
3061 return 0;
3062 }
3063 case SET:
3064 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
3065 case RETURN:
3066 /* If there was a return value, it must have been indicated with USE. */
3067 return 0x00ffff00;
3068 case CLOBBER:
3069 is_dest = 1;
3070 break;
3071 case MEM:
3072 is_dest = 0;
3073 break;
3074 case CALL:
3075 used |= 0x00ff00f0;
3076 break;
3077 default:
3078 break;
3079 }
3080
3081 fmt = GET_RTX_FORMAT (code);
3082
3083 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3084 {
3085 if (fmt[i] == 'E')
3086 {
3087 register int j;
3088 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3089 used |= regs_used (XVECEXP (x, i, j), is_dest);
3090 }
3091 else if (fmt[i] == 'e')
3092 used |= regs_used (XEXP (x, i), is_dest);
3093 }
3094 return used;
3095 }
3096
3097 /* Create an instruction that prevents redirection of a conditional branch
3098 to the destination of the JUMP with address ADDR.
3099 If the branch needs to be implemented as an indirect jump, try to find
3100 a scratch register for it.
3101 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3102 If any preceding insn that doesn't fit into a delay slot is good enough,
3103 pass 1. Pass 2 if a definite blocking insn is needed.
3104 -1 is used internally to avoid deep recursion.
3105 If a blocking instruction is made or recognized, return it. */
3106
3107 static rtx
gen_block_redirect(jump,addr,need_block)3108 gen_block_redirect (jump, addr, need_block)
3109 rtx jump;
3110 int addr, need_block;
3111 {
3112 int dead = 0;
3113 rtx prev = prev_nonnote_insn (jump);
3114 rtx dest;
3115
3116 /* First, check if we already have an instruction that satisfies our need. */
3117 if (prev && GET_CODE (prev) == INSN && ! INSN_DELETED_P (prev))
3118 {
3119 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
3120 return prev;
3121 if (GET_CODE (PATTERN (prev)) == USE
3122 || GET_CODE (PATTERN (prev)) == CLOBBER
3123 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3124 prev = jump;
3125 else if ((need_block &= ~1) < 0)
3126 return prev;
3127 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
3128 need_block = 0;
3129 }
3130 if (GET_CODE (PATTERN (jump)) == RETURN)
3131 {
3132 if (! need_block)
3133 return prev;
3134 /* Reorg even does nasty things with return insns that cause branches
3135 to go out of range - see find_end_label and callers. */
3136 return emit_insn_before (gen_block_branch_redirect (GEN_INT (0)) , jump);
3137 }
3138 /* We can't use JUMP_LABEL here because it might be undefined
3139 when not optimizing. */
3140 dest = XEXP (SET_SRC (PATTERN (jump)), 0);
3141 /* If the branch is out of range, try to find a scratch register for it. */
3142 if (optimize
3143 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3144 > 4092 + 4098))
3145 {
3146 rtx scan;
3147 /* Don't look for the stack pointer as a scratch register,
3148 it would cause trouble if an interrupt occurred. */
3149 unsigned try = 0x7fff, used;
3150 int jump_left = flag_expensive_optimizations + 1;
3151
3152 /* It is likely that the most recent eligible instruction is wanted for
3153 the delay slot. Therefore, find out which registers it uses, and
3154 try to avoid using them. */
3155
3156 for (scan = jump; (scan = PREV_INSN (scan)); )
3157 {
3158 enum rtx_code code;
3159
3160 if (INSN_DELETED_P (scan))
3161 continue;
3162 code = GET_CODE (scan);
3163 if (code == CODE_LABEL || code == JUMP_INSN)
3164 break;
3165 if (code == INSN
3166 && GET_CODE (PATTERN (scan)) != USE
3167 && GET_CODE (PATTERN (scan)) != CLOBBER
3168 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
3169 {
3170 try &= ~regs_used (PATTERN (scan), 0);
3171 break;
3172 }
3173 }
3174 for (used = dead = 0, scan = JUMP_LABEL (jump);
3175 (scan = NEXT_INSN (scan)); )
3176 {
3177 enum rtx_code code;
3178
3179 if (INSN_DELETED_P (scan))
3180 continue;
3181 code = GET_CODE (scan);
3182 if (GET_RTX_CLASS (code) == 'i')
3183 {
3184 used |= regs_used (PATTERN (scan), 0);
3185 if (code == CALL_INSN)
3186 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
3187 dead |= (used >> 16) & ~used;
3188 if (dead & try)
3189 {
3190 dead &= try;
3191 break;
3192 }
3193 if (code == JUMP_INSN)
3194 {
3195 if (jump_left-- && simplejump_p (scan))
3196 scan = JUMP_LABEL (scan);
3197 else
3198 break;
3199 }
3200 }
3201 }
3202 /* Mask out the stack pointer again, in case it was
3203 the only 'free' register we have found. */
3204 dead &= 0x7fff;
3205 }
3206 /* If the immediate destination is still in range, check for possible
3207 threading with a jump beyond the delay slot insn.
3208 Don't check if we are called recursively; the jump has been or will be
3209 checked in a different invocation then. */
3210
3211 else if (optimize && need_block >= 0)
3212 {
3213 rtx next = next_active_insn (next_active_insn (dest));
3214 if (next && GET_CODE (next) == JUMP_INSN
3215 && GET_CODE (PATTERN (next)) == SET
3216 && recog_memoized (next) == CODE_FOR_jump_compact)
3217 {
3218 dest = JUMP_LABEL (next);
3219 if (dest
3220 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
3221 > 4092 + 4098))
3222 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
3223 }
3224 }
3225
3226 if (dead)
3227 {
3228 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
3229
3230 /* It would be nice if we could convert the jump into an indirect
3231 jump / far branch right now, and thus exposing all constituent
3232 instructions to further optimization. However, reorg uses
3233 simplejump_p to determine if there is an unconditional jump where
3234 it should try to schedule instructions from the target of the
3235 branch; simplejump_p fails for indirect jumps even if they have
3236 a JUMP_LABEL. */
3237 rtx insn = emit_insn_before (gen_indirect_jump_scratch
3238 (reg, GEN_INT (INSN_UID (JUMP_LABEL (jump))))
3239 , jump);
3240 /* ??? We would like this to have the scope of the jump, but that
3241 scope will change when a delay slot insn of an inner scope is added.
3242 Hence, after delay slot scheduling, we'll have to expect
3243 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
3244 the jump. */
3245
3246 INSN_SCOPE (insn) = INSN_SCOPE (jump);
3247 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
3248 return insn;
3249 }
3250 else if (need_block)
3251 /* We can't use JUMP_LABEL here because it might be undefined
3252 when not optimizing. */
3253 return emit_insn_before (gen_block_branch_redirect
3254 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))))
3255 , jump);
3256 return prev;
3257 }
3258
3259 #define CONDJUMP_MIN -252
3260 #define CONDJUMP_MAX 262
3261 struct far_branch
3262 {
3263 /* A label (to be placed) in front of the jump
3264 that jumps to our ultimate destination. */
3265 rtx near_label;
3266 /* Where we are going to insert it if we cannot move the jump any farther,
3267 or the jump itself if we have picked up an existing jump. */
3268 rtx insert_place;
3269 /* The ultimate destination. */
3270 rtx far_label;
3271 struct far_branch *prev;
3272 /* If the branch has already been created, its address;
3273 else the address of its first prospective user. */
3274 int address;
3275 };
3276
3277 static void gen_far_branch PARAMS ((struct far_branch *));
3278 enum mdep_reorg_phase_e mdep_reorg_phase;
3279 static void
gen_far_branch(bp)3280 gen_far_branch (bp)
3281 struct far_branch *bp;
3282 {
3283 rtx insn = bp->insert_place;
3284 rtx jump;
3285 rtx label = gen_label_rtx ();
3286
3287 emit_label_after (label, insn);
3288 if (bp->far_label)
3289 {
3290 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
3291 LABEL_NUSES (bp->far_label)++;
3292 }
3293 else
3294 jump = emit_jump_insn_after (gen_return (), insn);
3295 /* Emit a barrier so that reorg knows that any following instructions
3296 are not reachable via a fall-through path.
3297 But don't do this when not optimizing, since we wouldn't supress the
3298 alignment for the barrier then, and could end up with out-of-range
3299 pc-relative loads. */
3300 if (optimize)
3301 emit_barrier_after (jump);
3302 emit_label_after (bp->near_label, insn);
3303 JUMP_LABEL (jump) = bp->far_label;
3304 if (! invert_jump (insn, label, 1))
3305 abort ();
3306 /* If we are branching around a jump (rather than a return), prevent
3307 reorg from using an insn from the jump target as the delay slot insn -
3308 when reorg did this, it pessimized code (we rather hide the delay slot)
3309 and it could cause branches to go out of range. */
3310 if (bp->far_label)
3311 (emit_insn_after
3312 (gen_stuff_delay_slot
3313 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump)), 0))),
3314 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
3315 insn));
3316 /* Prevent reorg from undoing our splits. */
3317 gen_block_redirect (jump, bp->address += 2, 2);
3318 }
3319
3320 /* Fix up ADDR_DIFF_VECs. */
3321 void
fixup_addr_diff_vecs(first)3322 fixup_addr_diff_vecs (first)
3323 rtx first;
3324 {
3325 rtx insn;
3326
3327 for (insn = first; insn; insn = NEXT_INSN (insn))
3328 {
3329 rtx vec_lab, pat, prev, prevpat, x, braf_label;
3330
3331 if (GET_CODE (insn) != JUMP_INSN
3332 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
3333 continue;
3334 pat = PATTERN (insn);
3335 vec_lab = XEXP (XEXP (pat, 0), 0);
3336
3337 /* Search the matching casesi_jump_2. */
3338 for (prev = vec_lab; ; prev = PREV_INSN (prev))
3339 {
3340 if (GET_CODE (prev) != JUMP_INSN)
3341 continue;
3342 prevpat = PATTERN (prev);
3343 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
3344 continue;
3345 x = XVECEXP (prevpat, 0, 1);
3346 if (GET_CODE (x) != USE)
3347 continue;
3348 x = XEXP (x, 0);
3349 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
3350 break;
3351 }
3352
3353 /* Emit the reference label of the braf where it belongs, right after
3354 the casesi_jump_2 (i.e. braf). */
3355 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
3356 emit_label_after (braf_label, prev);
3357
3358 /* Fix up the ADDR_DIF_VEC to be relative
3359 to the reference address of the braf. */
3360 XEXP (XEXP (pat, 0), 0) = braf_label;
3361 }
3362 }
3363
3364 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3365 a barrier. Return the base 2 logarithm of the desired alignment. */
3366 int
barrier_align(barrier_or_label)3367 barrier_align (barrier_or_label)
3368 rtx barrier_or_label;
3369 {
3370 rtx next = next_real_insn (barrier_or_label), pat, prev;
3371 int slot, credit, jump_to_next = 0;
3372
3373 if (! next)
3374 return 0;
3375
3376 pat = PATTERN (next);
3377
3378 if (GET_CODE (pat) == ADDR_DIFF_VEC)
3379 return 2;
3380
3381 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
3382 /* This is a barrier in front of a constant table. */
3383 return 0;
3384
3385 prev = prev_real_insn (barrier_or_label);
3386 if (GET_CODE (PATTERN (prev)) == ADDR_DIFF_VEC)
3387 {
3388 pat = PATTERN (prev);
3389 /* If this is a very small table, we want to keep the alignment after
3390 the table to the minimum for proper code alignment. */
3391 return ((TARGET_SMALLCODE
3392 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
3393 <= (unsigned)1 << (CACHE_LOG - 2)))
3394 ? 1 << TARGET_SHMEDIA : align_jumps_log);
3395 }
3396
3397 if (TARGET_SMALLCODE)
3398 return 0;
3399
3400 if (! TARGET_SH2 || ! optimize)
3401 return align_jumps_log;
3402
3403 /* When fixing up pcloads, a constant table might be inserted just before
3404 the basic block that ends with the barrier. Thus, we can't trust the
3405 instruction lengths before that. */
3406 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
3407 {
3408 /* Check if there is an immediately preceding branch to the insn beyond
3409 the barrier. We must weight the cost of discarding useful information
3410 from the current cache line when executing this branch and there is
3411 an alignment, against that of fetching unneeded insn in front of the
3412 branch target when there is no alignment. */
3413
3414 /* There are two delay_slot cases to consider. One is the simple case
3415 where the preceding branch is to the insn beyond the barrier (simple
3416 delay slot filling), and the other is where the preceding branch has
3417 a delay slot that is a duplicate of the insn after the barrier
3418 (fill_eager_delay_slots) and the branch is to the insn after the insn
3419 after the barrier. */
3420
3421 /* PREV is presumed to be the JUMP_INSN for the barrier under
3422 investigation. Skip to the insn before it. */
3423 prev = prev_real_insn (prev);
3424
3425 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
3426 credit >= 0 && prev && GET_CODE (prev) == INSN;
3427 prev = prev_real_insn (prev))
3428 {
3429 jump_to_next = 0;
3430 if (GET_CODE (PATTERN (prev)) == USE
3431 || GET_CODE (PATTERN (prev)) == CLOBBER)
3432 continue;
3433 if (GET_CODE (PATTERN (prev)) == SEQUENCE)
3434 {
3435 prev = XVECEXP (PATTERN (prev), 0, 1);
3436 if (INSN_UID (prev) == INSN_UID (next))
3437 {
3438 /* Delay slot was filled with insn at jump target. */
3439 jump_to_next = 1;
3440 continue;
3441 }
3442 }
3443
3444 if (slot &&
3445 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
3446 slot = 0;
3447 credit -= get_attr_length (prev);
3448 }
3449 if (prev
3450 && GET_CODE (prev) == JUMP_INSN
3451 && JUMP_LABEL (prev))
3452 {
3453 rtx x;
3454 if (jump_to_next
3455 || next_real_insn (JUMP_LABEL (prev)) == next
3456 /* If relax_delay_slots() decides NEXT was redundant
3457 with some previous instruction, it will have
3458 redirected PREV's jump to the following insn. */
3459 || JUMP_LABEL (prev) == next_nonnote_insn (next)
3460 /* There is no upper bound on redundant instructions
3461 that might have been skipped, but we must not put an
3462 alignment where none had been before. */
3463 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
3464 (INSN_P (x)
3465 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
3466 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
3467 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
3468 {
3469 rtx pat = PATTERN (prev);
3470 if (GET_CODE (pat) == PARALLEL)
3471 pat = XVECEXP (pat, 0, 0);
3472 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
3473 return 0;
3474 }
3475 }
3476 }
3477
3478 return align_jumps_log;
3479 }
3480
3481 /* If we are inside a phony loop, almost any kind of label can turn up as the
3482 first one in the loop. Aligning a braf label causes incorrect switch
3483 destination addresses; we can detect braf labels because they are
3484 followed by a BARRIER.
3485 Applying loop alignment to small constant or switch tables is a waste
3486 of space, so we suppress this too. */
3487 int
sh_loop_align(label)3488 sh_loop_align (label)
3489 rtx label;
3490 {
3491 rtx next = label;
3492
3493 do
3494 next = next_nonnote_insn (next);
3495 while (next && GET_CODE (next) == CODE_LABEL);
3496
3497 if (! next
3498 || ! INSN_P (next)
3499 || GET_CODE (PATTERN (next)) == ADDR_DIFF_VEC
3500 || recog_memoized (next) == CODE_FOR_consttable_2)
3501 return 0;
3502
3503 return align_loops_log;
3504 }
3505
3506 /* Exported to toplev.c.
3507
3508 Do a final pass over the function, just before delayed branch
3509 scheduling. */
3510
3511 void
machine_dependent_reorg(first)3512 machine_dependent_reorg (first)
3513 rtx first;
3514 {
3515 rtx insn, mova = NULL_RTX;
3516 int num_mova;
3517 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
3518 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
3519
3520 /* We must split call insns before introducing `mova's. If we're
3521 optimizing, they'll have already been split. Otherwise, make
3522 sure we don't split them too late. */
3523 if (! optimize)
3524 split_all_insns_noflow ();
3525
3526 if (TARGET_SHMEDIA)
3527 return;
3528
3529 /* If relaxing, generate pseudo-ops to associate function calls with
3530 the symbols they call. It does no harm to not generate these
3531 pseudo-ops. However, when we can generate them, it enables to
3532 linker to potentially relax the jsr to a bsr, and eliminate the
3533 register load and, possibly, the constant pool entry. */
3534
3535 mdep_reorg_phase = SH_INSERT_USES_LABELS;
3536 if (TARGET_RELAX)
3537 {
3538 /* Remove all REG_LABEL notes. We want to use them for our own
3539 purposes. This works because none of the remaining passes
3540 need to look at them.
3541
3542 ??? But it may break in the future. We should use a machine
3543 dependent REG_NOTE, or some other approach entirely. */
3544 for (insn = first; insn; insn = NEXT_INSN (insn))
3545 {
3546 if (INSN_P (insn))
3547 {
3548 rtx note;
3549
3550 while ((note = find_reg_note (insn, REG_LABEL, NULL_RTX)) != 0)
3551 remove_note (insn, note);
3552 }
3553 }
3554
3555 for (insn = first; insn; insn = NEXT_INSN (insn))
3556 {
3557 rtx pattern, reg, link, set, scan, dies, label;
3558 int rescan = 0, foundinsn = 0;
3559
3560 if (GET_CODE (insn) == CALL_INSN)
3561 {
3562 pattern = PATTERN (insn);
3563
3564 if (GET_CODE (pattern) == PARALLEL)
3565 pattern = XVECEXP (pattern, 0, 0);
3566 if (GET_CODE (pattern) == SET)
3567 pattern = SET_SRC (pattern);
3568
3569 if (GET_CODE (pattern) != CALL
3570 || GET_CODE (XEXP (pattern, 0)) != MEM)
3571 continue;
3572
3573 reg = XEXP (XEXP (pattern, 0), 0);
3574 }
3575 else
3576 {
3577 reg = sfunc_uses_reg (insn);
3578 if (! reg)
3579 continue;
3580 }
3581
3582 if (GET_CODE (reg) != REG)
3583 continue;
3584
3585 /* This is a function call via REG. If the only uses of REG
3586 between the time that it is set and the time that it dies
3587 are in function calls, then we can associate all the
3588 function calls with the setting of REG. */
3589
3590 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
3591 {
3592 if (REG_NOTE_KIND (link) != 0)
3593 continue;
3594 set = single_set (XEXP (link, 0));
3595 if (set && rtx_equal_p (reg, SET_DEST (set)))
3596 {
3597 link = XEXP (link, 0);
3598 break;
3599 }
3600 }
3601
3602 if (! link)
3603 {
3604 /* ??? Sometimes global register allocation will have
3605 deleted the insn pointed to by LOG_LINKS. Try
3606 scanning backward to find where the register is set. */
3607 for (scan = PREV_INSN (insn);
3608 scan && GET_CODE (scan) != CODE_LABEL;
3609 scan = PREV_INSN (scan))
3610 {
3611 if (! INSN_P (scan))
3612 continue;
3613
3614 if (! reg_mentioned_p (reg, scan))
3615 continue;
3616
3617 if (noncall_uses_reg (reg, scan, &set))
3618 break;
3619
3620 if (set)
3621 {
3622 link = scan;
3623 break;
3624 }
3625 }
3626 }
3627
3628 if (! link)
3629 continue;
3630
3631 /* The register is set at LINK. */
3632
3633 /* We can only optimize the function call if the register is
3634 being set to a symbol. In theory, we could sometimes
3635 optimize calls to a constant location, but the assembler
3636 and linker do not support that at present. */
3637 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
3638 && GET_CODE (SET_SRC (set)) != LABEL_REF)
3639 continue;
3640
3641 /* Scan forward from LINK to the place where REG dies, and
3642 make sure that the only insns which use REG are
3643 themselves function calls. */
3644
3645 /* ??? This doesn't work for call targets that were allocated
3646 by reload, since there may not be a REG_DEAD note for the
3647 register. */
3648
3649 dies = NULL_RTX;
3650 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
3651 {
3652 rtx scanset;
3653
3654 /* Don't try to trace forward past a CODE_LABEL if we haven't
3655 seen INSN yet. Ordinarily, we will only find the setting insn
3656 in LOG_LINKS if it is in the same basic block. However,
3657 cross-jumping can insert code labels in between the load and
3658 the call, and can result in situations where a single call
3659 insn may have two targets depending on where we came from. */
3660
3661 if (GET_CODE (scan) == CODE_LABEL && ! foundinsn)
3662 break;
3663
3664 if (! INSN_P (scan))
3665 continue;
3666
3667 /* Don't try to trace forward past a JUMP. To optimize
3668 safely, we would have to check that all the
3669 instructions at the jump destination did not use REG. */
3670
3671 if (GET_CODE (scan) == JUMP_INSN)
3672 break;
3673
3674 if (! reg_mentioned_p (reg, scan))
3675 continue;
3676
3677 if (noncall_uses_reg (reg, scan, &scanset))
3678 break;
3679
3680 if (scan == insn)
3681 foundinsn = 1;
3682
3683 if (scan != insn
3684 && (GET_CODE (scan) == CALL_INSN || sfunc_uses_reg (scan)))
3685 {
3686 /* There is a function call to this register other
3687 than the one we are checking. If we optimize
3688 this call, we need to rescan again below. */
3689 rescan = 1;
3690 }
3691
3692 /* ??? We shouldn't have to worry about SCANSET here.
3693 We should just be able to check for a REG_DEAD note
3694 on a function call. However, the REG_DEAD notes are
3695 apparently not dependable around libcalls; c-torture
3696 execute/920501-2 is a test case. If SCANSET is set,
3697 then this insn sets the register, so it must have
3698 died earlier. Unfortunately, this will only handle
3699 the cases in which the register is, in fact, set in a
3700 later insn. */
3701
3702 /* ??? We shouldn't have to use FOUNDINSN here.
3703 However, the LOG_LINKS fields are apparently not
3704 entirely reliable around libcalls;
3705 newlib/libm/math/e_pow.c is a test case. Sometimes
3706 an insn will appear in LOG_LINKS even though it is
3707 not the most recent insn which sets the register. */
3708
3709 if (foundinsn
3710 && (scanset
3711 || find_reg_note (scan, REG_DEAD, reg)))
3712 {
3713 dies = scan;
3714 break;
3715 }
3716 }
3717
3718 if (! dies)
3719 {
3720 /* Either there was a branch, or some insn used REG
3721 other than as a function call address. */
3722 continue;
3723 }
3724
3725 /* Create a code label, and put it in a REG_LABEL note on
3726 the insn which sets the register, and on each call insn
3727 which uses the register. In final_prescan_insn we look
3728 for the REG_LABEL notes, and output the appropriate label
3729 or pseudo-op. */
3730
3731 label = gen_label_rtx ();
3732 REG_NOTES (link) = gen_rtx_INSN_LIST (REG_LABEL, label,
3733 REG_NOTES (link));
3734 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL, label,
3735 REG_NOTES (insn));
3736 if (rescan)
3737 {
3738 scan = link;
3739 do
3740 {
3741 rtx reg2;
3742
3743 scan = NEXT_INSN (scan);
3744 if (scan != insn
3745 && ((GET_CODE (scan) == CALL_INSN
3746 && reg_mentioned_p (reg, scan))
3747 || ((reg2 = sfunc_uses_reg (scan))
3748 && REGNO (reg2) == REGNO (reg))))
3749 REG_NOTES (scan)
3750 = gen_rtx_INSN_LIST (REG_LABEL, label, REG_NOTES (scan));
3751 }
3752 while (scan != dies);
3753 }
3754 }
3755 }
3756
3757 if (TARGET_SH2)
3758 fixup_addr_diff_vecs (first);
3759
3760 if (optimize)
3761 {
3762 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
3763 shorten_branches (first);
3764 }
3765 /* Scan the function looking for move instructions which have to be
3766 changed to pc-relative loads and insert the literal tables. */
3767
3768 mdep_reorg_phase = SH_FIXUP_PCLOAD;
3769 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
3770 {
3771 if (mova_p (insn))
3772 {
3773 if (! num_mova++)
3774 mova = insn;
3775 }
3776 else if (GET_CODE (insn) == JUMP_INSN
3777 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3778 && num_mova)
3779 {
3780 rtx scan;
3781 int total;
3782
3783 num_mova--;
3784
3785 /* Some code might have been inserted between the mova and
3786 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3787 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
3788 total += get_attr_length (scan);
3789
3790 /* range of mova is 1020, add 4 because pc counts from address of
3791 second instruction after this one, subtract 2 in case pc is 2
3792 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3793 cancels out with alignment effects of the mova itself. */
3794 if (total > 1022)
3795 {
3796 /* Change the mova into a load, and restart scanning
3797 there. broken_move will then return true for mova. */
3798 SET_SRC (PATTERN (mova))
3799 = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
3800 INSN_CODE (mova) = -1;
3801 insn = mova;
3802 }
3803 }
3804 if (broken_move (insn))
3805 {
3806 rtx scan;
3807 /* Scan ahead looking for a barrier to stick the constant table
3808 behind. */
3809 rtx barrier = find_barrier (num_mova, mova, insn);
3810 rtx last_float_move = NULL_RTX, last_float = 0, *last_float_addr = NULL;
3811
3812 if (num_mova && ! mova_p (mova))
3813 {
3814 /* find_barrier had to change the first mova into a
3815 pcload; thus, we have to start with this new pcload. */
3816 insn = mova;
3817 num_mova = 0;
3818 }
3819 /* Now find all the moves between the points and modify them. */
3820 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
3821 {
3822 if (GET_CODE (scan) == CODE_LABEL)
3823 last_float = 0;
3824 if (broken_move (scan))
3825 {
3826 rtx *patp = &PATTERN (scan), pat = *patp;
3827 rtx src, dst;
3828 rtx lab;
3829 rtx newsrc;
3830 enum machine_mode mode;
3831
3832 if (GET_CODE (pat) == PARALLEL)
3833 patp = &XVECEXP (pat, 0, 0), pat = *patp;
3834 src = SET_SRC (pat);
3835 dst = SET_DEST (pat);
3836 mode = GET_MODE (dst);
3837
3838 if (mode == SImode && hi_const (src)
3839 && REGNO (dst) != FPUL_REG)
3840 {
3841 int offset = 0;
3842
3843 mode = HImode;
3844 while (GET_CODE (dst) == SUBREG)
3845 {
3846 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
3847 GET_MODE (SUBREG_REG (dst)),
3848 SUBREG_BYTE (dst),
3849 GET_MODE (dst));
3850 dst = SUBREG_REG (dst);
3851 }
3852 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
3853 }
3854
3855 if (GET_CODE (dst) == REG && FP_ANY_REGISTER_P (REGNO (dst)))
3856 {
3857 /* This must be an insn that clobbers r0. */
3858 rtx clobber = XVECEXP (PATTERN (scan), 0,
3859 XVECLEN (PATTERN (scan), 0) - 1);
3860
3861 if (GET_CODE (clobber) != CLOBBER
3862 || ! rtx_equal_p (XEXP (clobber, 0), r0_rtx))
3863 abort ();
3864
3865 if (last_float
3866 && reg_set_between_p (r0_rtx, last_float_move, scan))
3867 last_float = 0;
3868 if (last_float
3869 && TARGET_SHCOMPACT
3870 && GET_MODE_SIZE (mode) != 4
3871 && GET_MODE_SIZE (GET_MODE (last_float)) == 4)
3872 last_float = 0;
3873 lab = add_constant (src, mode, last_float);
3874 if (lab)
3875 emit_insn_before (gen_mova (lab), scan);
3876 else
3877 {
3878 /* There will be a REG_UNUSED note for r0 on
3879 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3880 lest reorg:mark_target_live_regs will not
3881 consider r0 to be used, and we end up with delay
3882 slot insn in front of SCAN that clobbers r0. */
3883 rtx note
3884 = find_regno_note (last_float_move, REG_UNUSED, 0);
3885
3886 /* If we are not optimizing, then there may not be
3887 a note. */
3888 if (note)
3889 PUT_MODE (note, REG_INC);
3890
3891 *last_float_addr = r0_inc_rtx;
3892 }
3893 last_float_move = scan;
3894 last_float = src;
3895 newsrc = gen_rtx (MEM, mode,
3896 (((TARGET_SH4 && ! TARGET_FMOVD)
3897 || REGNO (dst) == FPUL_REG)
3898 ? r0_inc_rtx
3899 : r0_rtx));
3900 last_float_addr = &XEXP (newsrc, 0);
3901
3902 /* Remove the clobber of r0. */
3903 XEXP (clobber, 0) = gen_rtx_SCRATCH (Pmode);
3904 RTX_UNCHANGING_P (newsrc) = 1;
3905 }
3906 /* This is a mova needing a label. Create it. */
3907 else if (GET_CODE (src) == UNSPEC
3908 && XINT (src, 1) == UNSPEC_MOVA
3909 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
3910 {
3911 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
3912 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
3913 newsrc = gen_rtx_UNSPEC (SImode,
3914 gen_rtvec (1, newsrc),
3915 UNSPEC_MOVA);
3916 }
3917 else
3918 {
3919 lab = add_constant (src, mode, 0);
3920 newsrc = gen_rtx_MEM (mode,
3921 gen_rtx_LABEL_REF (VOIDmode, lab));
3922 RTX_UNCHANGING_P (newsrc) = 1;
3923 }
3924 *patp = gen_rtx_SET (VOIDmode, dst, newsrc);
3925 INSN_CODE (scan) = -1;
3926 }
3927 }
3928 dump_table (barrier);
3929 insn = barrier;
3930 }
3931 }
3932
3933 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
3934 INSN_ADDRESSES_FREE ();
3935 split_branches (first);
3936
3937 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3938 also has an effect on the register that holds the address of the sfunc.
3939 Insert an extra dummy insn in front of each sfunc that pretends to
3940 use this register. */
3941 if (flag_delayed_branch)
3942 {
3943 for (insn = first; insn; insn = NEXT_INSN (insn))
3944 {
3945 rtx reg = sfunc_uses_reg (insn);
3946
3947 if (! reg)
3948 continue;
3949 emit_insn_before (gen_use_sfunc_addr (reg), insn);
3950 }
3951 }
3952 #if 0
3953 /* fpscr is not actually a user variable, but we pretend it is for the
3954 sake of the previous optimization passes, since we want it handled like
3955 one. However, we don't have any debugging information for it, so turn
3956 it into a non-user variable now. */
3957 if (TARGET_SH4)
3958 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3959 #endif
3960 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
3961 }
3962
3963 int
get_dest_uid(label,max_uid)3964 get_dest_uid (label, max_uid)
3965 rtx label;
3966 int max_uid;
3967 {
3968 rtx dest = next_real_insn (label);
3969 int dest_uid;
3970 if (! dest)
3971 /* This can happen for an undefined label. */
3972 return 0;
3973 dest_uid = INSN_UID (dest);
3974 /* If this is a newly created branch redirection blocking instruction,
3975 we cannot index the branch_uid or insn_addresses arrays with its
3976 uid. But then, we won't need to, because the actual destination is
3977 the following branch. */
3978 while (dest_uid >= max_uid)
3979 {
3980 dest = NEXT_INSN (dest);
3981 dest_uid = INSN_UID (dest);
3982 }
3983 if (GET_CODE (dest) == JUMP_INSN && GET_CODE (PATTERN (dest)) == RETURN)
3984 return 0;
3985 return dest_uid;
3986 }
3987
3988 /* Split condbranches that are out of range. Also add clobbers for
3989 scratch registers that are needed in far jumps.
3990 We do this before delay slot scheduling, so that it can take our
3991 newly created instructions into account. It also allows us to
3992 find branches with common targets more easily. */
3993
3994 static void
split_branches(first)3995 split_branches (first)
3996 rtx first;
3997 {
3998 rtx insn;
3999 struct far_branch **uid_branch, *far_branch_list = 0;
4000 int max_uid = get_max_uid ();
4001
4002 /* Find out which branches are out of range. */
4003 shorten_branches (first);
4004
4005 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
4006 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
4007
4008 for (insn = first; insn; insn = NEXT_INSN (insn))
4009 if (! INSN_P (insn))
4010 continue;
4011 else if (INSN_DELETED_P (insn))
4012 {
4013 /* Shorten_branches would split this instruction again,
4014 so transform it into a note. */
4015 PUT_CODE (insn, NOTE);
4016 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
4017 NOTE_SOURCE_FILE (insn) = 0;
4018 }
4019 else if (GET_CODE (insn) == JUMP_INSN
4020 /* Don't mess with ADDR_DIFF_VEC */
4021 && (GET_CODE (PATTERN (insn)) == SET
4022 || GET_CODE (PATTERN (insn)) == RETURN))
4023 {
4024 enum attr_type type = get_attr_type (insn);
4025 if (type == TYPE_CBRANCH)
4026 {
4027 rtx next, beyond;
4028
4029 if (get_attr_length (insn) > 4)
4030 {
4031 rtx src = SET_SRC (PATTERN (insn));
4032 rtx olabel = XEXP (XEXP (src, 1), 0);
4033 int addr = INSN_ADDRESSES (INSN_UID (insn));
4034 rtx label = 0;
4035 int dest_uid = get_dest_uid (olabel, max_uid);
4036 struct far_branch *bp = uid_branch[dest_uid];
4037
4038 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4039 the label if the LABEL_NUSES count drops to zero. There is
4040 always a jump_optimize pass that sets these values, but it
4041 proceeds to delete unreferenced code, and then if not
4042 optimizing, to un-delete the deleted instructions, thus
4043 leaving labels with too low uses counts. */
4044 if (! optimize)
4045 {
4046 JUMP_LABEL (insn) = olabel;
4047 LABEL_NUSES (olabel)++;
4048 }
4049 if (! bp)
4050 {
4051 bp = (struct far_branch *) alloca (sizeof *bp);
4052 uid_branch[dest_uid] = bp;
4053 bp->prev = far_branch_list;
4054 far_branch_list = bp;
4055 bp->far_label
4056 = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
4057 LABEL_NUSES (bp->far_label)++;
4058 }
4059 else
4060 {
4061 label = bp->near_label;
4062 if (! label && bp->address - addr >= CONDJUMP_MIN)
4063 {
4064 rtx block = bp->insert_place;
4065
4066 if (GET_CODE (PATTERN (block)) == RETURN)
4067 block = PREV_INSN (block);
4068 else
4069 block = gen_block_redirect (block,
4070 bp->address, 2);
4071 label = emit_label_after (gen_label_rtx (),
4072 PREV_INSN (block));
4073 bp->near_label = label;
4074 }
4075 else if (label && ! NEXT_INSN (label))
4076 {
4077 if (addr + 2 - bp->address <= CONDJUMP_MAX)
4078 bp->insert_place = insn;
4079 else
4080 gen_far_branch (bp);
4081 }
4082 }
4083 if (! label
4084 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
4085 {
4086 bp->near_label = label = gen_label_rtx ();
4087 bp->insert_place = insn;
4088 bp->address = addr;
4089 }
4090 if (! redirect_jump (insn, label, 1))
4091 abort ();
4092 }
4093 else
4094 {
4095 /* get_attr_length (insn) == 2 */
4096 /* Check if we have a pattern where reorg wants to redirect
4097 the branch to a label from an unconditional branch that
4098 is too far away. */
4099 /* We can't use JUMP_LABEL here because it might be undefined
4100 when not optimizing. */
4101 /* A syntax error might cause beyond to be NULL_RTX. */
4102 beyond
4103 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
4104 0));
4105
4106 if (beyond
4107 && (GET_CODE (beyond) == JUMP_INSN
4108 || ((beyond = next_active_insn (beyond))
4109 && GET_CODE (beyond) == JUMP_INSN))
4110 && GET_CODE (PATTERN (beyond)) == SET
4111 && recog_memoized (beyond) == CODE_FOR_jump_compact
4112 && ((INSN_ADDRESSES
4113 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
4114 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4115 > 252 + 258 + 2))
4116 gen_block_redirect (beyond,
4117 INSN_ADDRESSES (INSN_UID (beyond)), 1);
4118 }
4119
4120 next = next_active_insn (insn);
4121
4122 if ((GET_CODE (next) == JUMP_INSN
4123 || GET_CODE (next = next_active_insn (next)) == JUMP_INSN)
4124 && GET_CODE (PATTERN (next)) == SET
4125 && recog_memoized (next) == CODE_FOR_jump_compact
4126 && ((INSN_ADDRESSES
4127 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
4128 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
4129 > 252 + 258 + 2))
4130 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
4131 }
4132 else if (type == TYPE_JUMP || type == TYPE_RETURN)
4133 {
4134 int addr = INSN_ADDRESSES (INSN_UID (insn));
4135 rtx far_label = 0;
4136 int dest_uid = 0;
4137 struct far_branch *bp;
4138
4139 if (type == TYPE_JUMP)
4140 {
4141 far_label = XEXP (SET_SRC (PATTERN (insn)), 0);
4142 dest_uid = get_dest_uid (far_label, max_uid);
4143 if (! dest_uid)
4144 {
4145 /* Parse errors can lead to labels outside
4146 the insn stream. */
4147 if (! NEXT_INSN (far_label))
4148 continue;
4149
4150 if (! optimize)
4151 {
4152 JUMP_LABEL (insn) = far_label;
4153 LABEL_NUSES (far_label)++;
4154 }
4155 redirect_jump (insn, NULL_RTX, 1);
4156 far_label = 0;
4157 }
4158 }
4159 bp = uid_branch[dest_uid];
4160 if (! bp)
4161 {
4162 bp = (struct far_branch *) alloca (sizeof *bp);
4163 uid_branch[dest_uid] = bp;
4164 bp->prev = far_branch_list;
4165 far_branch_list = bp;
4166 bp->near_label = 0;
4167 bp->far_label = far_label;
4168 if (far_label)
4169 LABEL_NUSES (far_label)++;
4170 }
4171 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
4172 if (addr - bp->address <= CONDJUMP_MAX)
4173 emit_label_after (bp->near_label, PREV_INSN (insn));
4174 else
4175 {
4176 gen_far_branch (bp);
4177 bp->near_label = 0;
4178 }
4179 else
4180 bp->near_label = 0;
4181 bp->address = addr;
4182 bp->insert_place = insn;
4183 if (! far_label)
4184 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
4185 else
4186 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
4187 }
4188 }
4189 /* Generate all pending far branches,
4190 and free our references to the far labels. */
4191 while (far_branch_list)
4192 {
4193 if (far_branch_list->near_label
4194 && ! NEXT_INSN (far_branch_list->near_label))
4195 gen_far_branch (far_branch_list);
4196 if (optimize
4197 && far_branch_list->far_label
4198 && ! --LABEL_NUSES (far_branch_list->far_label))
4199 delete_insn (far_branch_list->far_label);
4200 far_branch_list = far_branch_list->prev;
4201 }
4202
4203 /* Instruction length information is no longer valid due to the new
4204 instructions that have been generated. */
4205 init_insn_lengths ();
4206 }
4207
4208 /* Dump out instruction addresses, which is useful for debugging the
4209 constant pool table stuff.
4210
4211 If relaxing, output the label and pseudo-ops used to link together
4212 calls and the instruction which set the registers. */
4213
4214 /* ??? The addresses printed by this routine for insns are nonsense for
4215 insns which are inside of a sequence where none of the inner insns have
4216 variable length. This is because the second pass of shorten_branches
4217 does not bother to update them. */
4218
4219 void
final_prescan_insn(insn,opvec,noperands)4220 final_prescan_insn (insn, opvec, noperands)
4221 rtx insn;
4222 rtx *opvec ATTRIBUTE_UNUSED;
4223 int noperands ATTRIBUTE_UNUSED;
4224 {
4225 if (TARGET_DUMPISIZE)
4226 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
4227
4228 if (TARGET_RELAX)
4229 {
4230 rtx note;
4231
4232 note = find_reg_note (insn, REG_LABEL, NULL_RTX);
4233 if (note)
4234 {
4235 rtx pattern;
4236
4237 pattern = PATTERN (insn);
4238 if (GET_CODE (pattern) == PARALLEL)
4239 pattern = XVECEXP (pattern, 0, 0);
4240 if (GET_CODE (pattern) == CALL
4241 || (GET_CODE (pattern) == SET
4242 && (GET_CODE (SET_SRC (pattern)) == CALL
4243 || get_attr_type (insn) == TYPE_SFUNC)))
4244 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
4245 CODE_LABEL_NUMBER (XEXP (note, 0)));
4246 else if (GET_CODE (pattern) == SET)
4247 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4248 CODE_LABEL_NUMBER (XEXP (note, 0)));
4249 else
4250 abort ();
4251 }
4252 }
4253 }
4254
4255 /* Dump out any constants accumulated in the final pass. These will
4256 only be labels. */
4257
4258 const char *
output_jump_label_table()4259 output_jump_label_table ()
4260 {
4261 int i;
4262
4263 if (pool_size)
4264 {
4265 fprintf (asm_out_file, "\t.align 2\n");
4266 for (i = 0; i < pool_size; i++)
4267 {
4268 pool_node *p = &pool_vector[i];
4269
4270 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4271 CODE_LABEL_NUMBER (p->label));
4272 output_asm_insn (".long %O0", &p->value);
4273 }
4274 pool_size = 0;
4275 }
4276
4277 return "";
4278 }
4279
4280 /* A full frame looks like:
4281
4282 arg-5
4283 arg-4
4284 [ if current_function_anonymous_args
4285 arg-3
4286 arg-2
4287 arg-1
4288 arg-0 ]
4289 saved-fp
4290 saved-r10
4291 saved-r11
4292 saved-r12
4293 saved-pr
4294 local-n
4295 ..
4296 local-1
4297 local-0 <- fp points here. */
4298
4299 /* Number of bytes pushed for anonymous args, used to pass information
4300 between expand_prologue and expand_epilogue. */
4301
4302 static int extra_push;
4303
4304 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4305 to be adjusted, and TEMP, if nonnegative, holds the register number
4306 of a general register that we may clobber. */
4307
4308 static void
output_stack_adjust(size,reg,temp,emit_fn)4309 output_stack_adjust (size, reg, temp, emit_fn)
4310 int size;
4311 rtx reg;
4312 int temp;
4313 rtx (*emit_fn) PARAMS ((rtx));
4314 {
4315 if (size)
4316 {
4317 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4318
4319 if (size % align)
4320 abort ();
4321
4322 if (CONST_OK_FOR_ADD (size))
4323 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
4324 /* Try to do it with two partial adjustments; however, we must make
4325 sure that the stack is properly aligned at all times, in case
4326 an interrupt occurs between the two partial adjustments. */
4327 else if (CONST_OK_FOR_ADD (size / 2 & -align)
4328 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
4329 {
4330 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
4331 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
4332 }
4333 else
4334 {
4335 rtx const_reg;
4336 rtx insn;
4337
4338 /* If TEMP is invalid, we could temporarily save a general
4339 register to MACL. However, there is currently no need
4340 to handle this case, so just abort when we see it. */
4341 if (temp < 0)
4342 {
4343 /* If we reached here, the most likely case is the (sibcall)
4344 epilogue for non SHmedia. Put a special push/pop sequence
4345 for such case as the last resort. This looks lengthy but
4346 would not be problem because it seems to be very rare. */
4347 if (! TARGET_SHMEDIA && (emit_fn != frame_insn))
4348 {
4349 rtx adj_reg, tmp_reg, mem;
4350
4351 /* ??? There is still the slight possibility that r4 or r5
4352 have been reserved as fixed registers or assigned as
4353 global registers, and they change during an interrupt.
4354 There are possible ways to handle this:
4355 - If we are adjusting the frame pointer (r14), we can do
4356 with a single temp register and an ordinary push / pop
4357 on the stack.
4358 - Grab any call-used or call-saved registers (i.e. not
4359 fixed or globals) for the temps we need. We might
4360 also grab r14 if we are adjusting the stack pointer.
4361 If we can't find enough available registers, issue
4362 a diagnostic and abort - the user must have reserved
4363 way too many registers.
4364 But since all this is rather unlikely to happen and
4365 would require extra testing, we just abort if r4 / r5
4366 are not available. */
4367 if (fixed_regs[4] || fixed_regs[5]
4368 || global_regs[4] || global_regs[5])
4369 abort ();
4370
4371 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
4372 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
4373 emit_move_insn (gen_rtx_MEM (Pmode, reg), adj_reg);
4374 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
4375 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
4376 mem = gen_rtx_MEM (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
4377 emit_move_insn (mem, tmp_reg);
4378 emit_move_insn (tmp_reg, gen_rtx_MEM (Pmode, reg));
4379 mem = gen_rtx_MEM (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
4380 emit_move_insn (mem, tmp_reg);
4381 emit_move_insn (reg, adj_reg);
4382 mem = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, reg));
4383 emit_move_insn (adj_reg, mem);
4384 mem = gen_rtx_MEM (Pmode, gen_rtx_POST_INC (Pmode, reg));
4385 emit_move_insn (tmp_reg, mem);
4386 return;
4387 }
4388 else
4389 abort ();
4390 }
4391 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
4392
4393 /* If SIZE is negative, subtract the positive value.
4394 This sometimes allows a constant pool entry to be shared
4395 between prologue and epilogue code. */
4396 if (size < 0)
4397 {
4398 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
4399 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
4400 }
4401 else
4402 {
4403 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
4404 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
4405 }
4406 if (emit_fn == frame_insn)
4407 REG_NOTES (insn)
4408 = (gen_rtx_EXPR_LIST
4409 (REG_FRAME_RELATED_EXPR,
4410 gen_rtx_SET (VOIDmode, reg,
4411 gen_rtx_PLUS (SImode, reg, GEN_INT (size))),
4412 REG_NOTES (insn)));
4413 }
4414 }
4415 }
4416
4417 static rtx
frame_insn(x)4418 frame_insn (x)
4419 rtx x;
4420 {
4421 x = emit_insn (x);
4422 RTX_FRAME_RELATED_P (x) = 1;
4423 return x;
4424 }
4425
4426 /* Output RTL to push register RN onto the stack. */
4427
4428 static rtx
push(rn)4429 push (rn)
4430 int rn;
4431 {
4432 rtx x;
4433 if (rn == FPUL_REG)
4434 x = gen_push_fpul ();
4435 else if (rn == FPSCR_REG)
4436 x = gen_push_fpscr ();
4437 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4438 && FP_OR_XD_REGISTER_P (rn))
4439 {
4440 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4441 return NULL_RTX;
4442 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
4443 }
4444 else if (TARGET_SH3E && FP_REGISTER_P (rn))
4445 x = gen_push_e (gen_rtx_REG (SFmode, rn));
4446 else
4447 x = gen_push (gen_rtx_REG (SImode, rn));
4448
4449 x = frame_insn (x);
4450 REG_NOTES (x)
4451 = gen_rtx_EXPR_LIST (REG_INC,
4452 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4453 return x;
4454 }
4455
4456 /* Output RTL to pop register RN from the stack. */
4457
4458 static void
pop(rn)4459 pop (rn)
4460 int rn;
4461 {
4462 rtx x;
4463 if (rn == FPUL_REG)
4464 x = gen_pop_fpul ();
4465 else if (rn == FPSCR_REG)
4466 x = gen_pop_fpscr ();
4467 else if (TARGET_SH4 && TARGET_FMOVD && ! TARGET_FPU_SINGLE
4468 && FP_OR_XD_REGISTER_P (rn))
4469 {
4470 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
4471 return;
4472 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
4473 }
4474 else if (TARGET_SH3E && FP_REGISTER_P (rn))
4475 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
4476 else
4477 x = gen_pop (gen_rtx_REG (SImode, rn));
4478
4479 x = emit_insn (x);
4480 REG_NOTES (x)
4481 = gen_rtx_EXPR_LIST (REG_INC,
4482 gen_rtx_REG (SImode, STACK_POINTER_REGNUM), 0);
4483 }
4484
4485 /* Generate code to push the regs specified in the mask. */
4486
4487 static void
push_regs(mask)4488 push_regs (mask)
4489 HOST_WIDE_INT *mask;
4490 {
4491 int i;
4492
4493 /* Push PR last; this gives better latencies after the prologue, and
4494 candidates for the return delay slot when there are no general
4495 registers pushed. */
4496 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4497 if (i != PR_REG && mask[i / 32] & (1 << (i % 32)))
4498 push (i);
4499 if (mask[PR_REG / 32] & (1 << (PR_REG % 32)))
4500 push (PR_REG);
4501 }
4502
4503 /* Work out the registers which need to be saved, both as a mask and a
4504 count of saved words.
4505
4506 If doing a pragma interrupt function, then push all regs used by the
4507 function, and if we call another function (we can tell by looking at PR),
4508 make sure that all the regs it clobbers are safe too. */
4509
4510 static void
calc_live_regs(count_ptr,live_regs_mask)4511 calc_live_regs (count_ptr, live_regs_mask)
4512 int *count_ptr;
4513 HOST_WIDE_INT *live_regs_mask;
4514 {
4515 int reg;
4516 int count;
4517 int interrupt_handler;
4518 int pr_live;
4519
4520 interrupt_handler = sh_cfun_interrupt_handler_p ();
4521
4522 for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++)
4523 live_regs_mask[count] = 0;
4524 /* If we can save a lot of saves by switching to double mode, do that. */
4525 if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
4526 for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
4527 if (regs_ever_live[reg] && regs_ever_live[reg+1]
4528 && (! call_used_regs[reg] || (interrupt_handler && ! pragma_trapa))
4529 && ++count > 2)
4530 {
4531 target_flags &= ~FPU_SINGLE_BIT;
4532 break;
4533 }
4534 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4535 knows how to use it. That means the pseudo originally allocated for
4536 the initial value can become the PR_MEDIA_REG hard register, as seen for
4537 execute/20010122-1.c:test9. */
4538 if (TARGET_SHMEDIA)
4539 pr_live = regs_ever_live[PR_MEDIA_REG];
4540 else
4541 {
4542 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
4543 pr_live = (pr_initial
4544 ? REGNO (pr_initial) != (PR_REG) : regs_ever_live[PR_REG]);
4545 }
4546 /* Force PR to be live if the prologue has to call the SHmedia
4547 argument decoder or register saver. */
4548 if (TARGET_SHCOMPACT
4549 && ((current_function_args_info.call_cookie
4550 & ~ CALL_COOKIE_RET_TRAMP (1))
4551 || current_function_has_nonlocal_label))
4552 pr_live = 1;
4553 for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
4554 {
4555 if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
4556 ? pr_live
4557 : (interrupt_handler && ! pragma_trapa)
4558 ? (/* Need to save all the regs ever live. */
4559 (regs_ever_live[reg]
4560 || (call_used_regs[reg]
4561 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
4562 && pr_live))
4563 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
4564 && reg != RETURN_ADDRESS_POINTER_REGNUM
4565 && reg != T_REG && reg != GBR_REG
4566 /* Push fpscr only on targets which have FPU */
4567 && (reg != FPSCR_REG || TARGET_FPU_ANY))
4568 : (/* Only push those regs which are used and need to be saved. */
4569 (TARGET_SHCOMPACT
4570 && flag_pic
4571 && current_function_args_info.call_cookie
4572 && reg == PIC_OFFSET_TABLE_REGNUM)
4573 || (regs_ever_live[reg] && ! call_used_regs[reg])))
4574 {
4575 live_regs_mask[reg / 32] |= 1 << (reg % 32);
4576 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
4577
4578 if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
4579 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
4580 {
4581 if (FP_REGISTER_P (reg))
4582 {
4583 if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
4584 {
4585 live_regs_mask[(reg ^ 1) / 32] |= 1 << ((reg ^ 1) % 32);
4586 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
4587 }
4588 }
4589 else if (XD_REGISTER_P (reg))
4590 {
4591 /* Must switch to double mode to access these registers. */
4592 target_flags &= ~FPU_SINGLE_BIT;
4593 }
4594 }
4595 }
4596 }
4597
4598 *count_ptr = count;
4599 }
4600
4601 /* Code to generate prologue and epilogue sequences */
4602
4603 /* PUSHED is the number of bytes that are bing pushed on the
4604 stack for register saves. Return the frame size, padded
4605 appropriately so that the stack stays properly aligned. */
4606 static HOST_WIDE_INT
rounded_frame_size(pushed)4607 rounded_frame_size (pushed)
4608 int pushed;
4609 {
4610 HOST_WIDE_INT size = get_frame_size ();
4611 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
4612
4613 return ((size + pushed + align - 1) & -align) - pushed;
4614 }
4615
4616 /* Choose a call-clobbered target-branch register that remains
4617 unchanged along the whole function. We set it up as the return
4618 value in the prologue. */
4619 int
sh_media_register_for_return()4620 sh_media_register_for_return ()
4621 {
4622 int regno;
4623 int tr0_used;
4624
4625 if (! current_function_is_leaf)
4626 return -1;
4627
4628 tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
4629
4630 for (regno = FIRST_TARGET_REG + tr0_used; regno <= LAST_TARGET_REG; regno++)
4631 if (call_used_regs[regno] && ! regs_ever_live[regno])
4632 return regno;
4633
4634 return -1;
4635 }
4636
4637 void
sh_expand_prologue()4638 sh_expand_prologue ()
4639 {
4640 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
4641 int d, i;
4642 int d_rounding = 0;
4643 int save_flags = target_flags;
4644 int size;
4645
4646 current_function_interrupt = sh_cfun_interrupt_handler_p ();
4647
4648 /* We have pretend args if we had an object sent partially in registers
4649 and partially on the stack, e.g. a large structure. */
4650 output_stack_adjust (-current_function_pretend_args_size
4651 - current_function_args_info.stack_regs * 8,
4652 stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
4653
4654 extra_push = 0;
4655
4656 if (TARGET_SHCOMPACT && flag_pic && current_function_args_info.call_cookie)
4657 /* We're going to use the PIC register to load the address of the
4658 incoming-argument decoder and/or of the return trampoline from
4659 the GOT, so make sure the PIC register is preserved and
4660 initialized. */
4661 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
4662
4663 if (TARGET_SHCOMPACT
4664 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
4665 {
4666 int reg;
4667
4668 /* First, make all registers with incoming arguments that will
4669 be pushed onto the stack live, so that register renaming
4670 doesn't overwrite them. */
4671 for (reg = 0; reg < NPARM_REGS (SImode); reg++)
4672 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info.call_cookie)
4673 >= NPARM_REGS (SImode) - reg)
4674 for (; reg < NPARM_REGS (SImode); reg++)
4675 emit_insn (gen_shcompact_preserve_incoming_args
4676 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4677 else if (CALL_COOKIE_INT_REG_GET
4678 (current_function_args_info.call_cookie, reg) == 1)
4679 emit_insn (gen_shcompact_preserve_incoming_args
4680 (gen_rtx_REG (SImode, FIRST_PARM_REG + reg)));
4681
4682 emit_move_insn (gen_rtx_REG (Pmode, MACL_REG),
4683 stack_pointer_rtx);
4684 emit_move_insn (gen_rtx_REG (SImode, R0_REG),
4685 GEN_INT (current_function_args_info.call_cookie));
4686 emit_move_insn (gen_rtx_REG (SImode, MACH_REG),
4687 gen_rtx_REG (SImode, R0_REG));
4688 }
4689 else if (TARGET_SHMEDIA)
4690 {
4691 int tr = sh_media_register_for_return ();
4692
4693 if (tr >= 0)
4694 {
4695 rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
4696 gen_rtx_REG (DImode, PR_MEDIA_REG));
4697
4698 /* If this function only exits with sibcalls, this copy
4699 will be flagged as dead. */
4700 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4701 const0_rtx,
4702 REG_NOTES (insn));
4703 }
4704 }
4705
4706 /* Emit the code for SETUP_VARARGS. */
4707 if (current_function_stdarg)
4708 {
4709 /* This is not used by the SH3E calling convention */
4710 if (TARGET_SH1 && ! TARGET_SH3E && ! TARGET_SH5 && ! TARGET_HITACHI)
4711 {
4712 /* Push arg regs as if they'd been provided by caller in stack. */
4713 for (i = 0; i < NPARM_REGS(SImode); i++)
4714 {
4715 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
4716 rtx insn;
4717
4718 if (i >= (NPARM_REGS(SImode)
4719 - current_function_args_info.arg_count[(int) SH_ARG_INT]
4720 ))
4721 break;
4722 insn = push (rn);
4723 RTX_FRAME_RELATED_P (insn) = 0;
4724 extra_push += 4;
4725 }
4726 }
4727 }
4728
4729 /* If we're supposed to switch stacks at function entry, do so now. */
4730 if (sp_switch)
4731 emit_insn (gen_sp_switch_1 ());
4732
4733 calc_live_regs (&d, live_regs_mask);
4734 /* ??? Maybe we could save some switching if we can move a mode switch
4735 that already happens to be at the function start into the prologue. */
4736 if (target_flags != save_flags)
4737 emit_insn (gen_toggle_sz ());
4738
4739 if (TARGET_SH5)
4740 {
4741 int i;
4742 int offset;
4743 int align;
4744 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
4745 int offset_in_r0 = -1;
4746 int sp_in_r0 = 0;
4747
4748 if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
4749 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
4750 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
4751
4752 offset = d + d_rounding;
4753 output_stack_adjust (-offset, stack_pointer_rtx, 1, frame_insn);
4754
4755 /* We loop twice: first, we save 8-byte aligned registers in the
4756 higher addresses, that are known to be aligned. Then, we
4757 proceed to saving 32-bit registers that don't need 8-byte
4758 alignment. */
4759 for (align = 1; align >= 0; align--)
4760 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
4761 if (live_regs_mask[i/32] & (1 << (i % 32)))
4762 {
4763 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
4764 int reg = i;
4765 rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
4766
4767 if (mode == SFmode && (i % 2) == 1
4768 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
4769 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
4770 {
4771 mode = DFmode;
4772 i--;
4773 reg--;
4774 }
4775
4776 /* If we're doing the aligned pass and this is not aligned,
4777 or we're doing the unaligned pass and this is aligned,
4778 skip it. */
4779 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
4780 == 0) != align)
4781 continue;
4782
4783 offset -= GET_MODE_SIZE (mode);
4784
4785 reg_rtx = gen_rtx_REG (mode, reg);
4786
4787 mem_rtx = gen_rtx_MEM (mode,
4788 gen_rtx_PLUS (Pmode,
4789 stack_pointer_rtx,
4790 GEN_INT (offset)));
4791
4792 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
4793
4794 mem_rtx = NULL_RTX;
4795
4796 try_pre_dec:
4797 do
4798 if (HAVE_PRE_DECREMENT
4799 && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
4800 || mem_rtx == NULL_RTX
4801 || i == PR_REG || SPECIAL_REGISTER_P (i)))
4802 {
4803 pre_dec = gen_rtx_MEM (mode,
4804 gen_rtx_PRE_DEC (Pmode, r0));
4805
4806 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
4807 pre_dec_ok);
4808
4809 pre_dec = NULL_RTX;
4810
4811 break;
4812
4813 pre_dec_ok:
4814 mem_rtx = NULL_RTX;
4815 offset += GET_MODE_SIZE (mode);
4816 }
4817 while (0);
4818
4819 if (mem_rtx != NULL_RTX)
4820 goto addr_ok;
4821
4822 if (offset_in_r0 == -1)
4823 {
4824 emit_move_insn (r0, GEN_INT (offset));
4825 offset_in_r0 = offset;
4826 }
4827 else if (offset != offset_in_r0)
4828 {
4829 emit_move_insn (r0,
4830 gen_rtx_PLUS
4831 (Pmode, r0,
4832 GEN_INT (offset - offset_in_r0)));
4833 offset_in_r0 += offset - offset_in_r0;
4834 }
4835
4836 if (pre_dec != NULL_RTX)
4837 {
4838 if (! sp_in_r0)
4839 {
4840 emit_move_insn (r0,
4841 gen_rtx_PLUS
4842 (Pmode, r0, stack_pointer_rtx));
4843 sp_in_r0 = 1;
4844 }
4845
4846 offset -= GET_MODE_SIZE (mode);
4847 offset_in_r0 -= GET_MODE_SIZE (mode);
4848
4849 mem_rtx = pre_dec;
4850 }
4851 else if (sp_in_r0)
4852 mem_rtx = gen_rtx_MEM (mode, r0);
4853 else
4854 mem_rtx = gen_rtx_MEM (mode,
4855 gen_rtx_PLUS (Pmode,
4856 stack_pointer_rtx,
4857 r0));
4858
4859 /* We must not use an r0-based address for target-branch
4860 registers or for special registers without pre-dec
4861 memory addresses, since we store their values in r0
4862 first. */
4863 if (TARGET_REGISTER_P (i)
4864 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
4865 && mem_rtx != pre_dec))
4866 abort ();
4867
4868 addr_ok:
4869 if (TARGET_REGISTER_P (i)
4870 || ((i == PR_REG || SPECIAL_REGISTER_P (i))
4871 && mem_rtx != pre_dec))
4872 {
4873 rtx r0mode = gen_rtx_REG (GET_MODE (reg_rtx), R0_REG);
4874
4875 emit_move_insn (r0mode, reg_rtx);
4876
4877 offset_in_r0 = -1;
4878 sp_in_r0 = 0;
4879
4880 reg_rtx = r0mode;
4881 }
4882
4883 emit_move_insn (mem_rtx, reg_rtx);
4884 }
4885
4886 if (offset != d_rounding)
4887 abort ();
4888 }
4889 else
4890 push_regs (live_regs_mask);
4891
4892 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
4893 {
4894 rtx insn = get_last_insn ();
4895 rtx last = emit_insn (gen_GOTaddr2picreg ());
4896
4897 /* Mark these insns as possibly dead. Sometimes, flow2 may
4898 delete all uses of the PIC register. In this case, let it
4899 delete the initialization too. */
4900 do
4901 {
4902 insn = NEXT_INSN (insn);
4903
4904 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4905 const0_rtx,
4906 REG_NOTES (insn));
4907 }
4908 while (insn != last);
4909 }
4910
4911 if (SHMEDIA_REGS_STACK_ADJUST ())
4912 {
4913 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
4914 gen_rtx_SYMBOL_REF (Pmode,
4915 TARGET_FPU_ANY
4916 ? "__GCC_push_shmedia_regs"
4917 : "__GCC_push_shmedia_regs_nofpu"));
4918 /* This must NOT go through the PLT, otherwise mach and macl
4919 may be clobbered. */
4920 emit_insn (gen_shmedia_save_restore_regs_compact
4921 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
4922 }
4923
4924 if (target_flags != save_flags)
4925 {
4926 rtx insn = emit_insn (gen_toggle_sz ());
4927
4928 /* If we're lucky, a mode switch in the function body will
4929 overwrite fpscr, turning this insn dead. Tell flow this
4930 insn is ok to delete. */
4931 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
4932 const0_rtx,
4933 REG_NOTES (insn));
4934 }
4935
4936 target_flags = save_flags;
4937
4938 size = rounded_frame_size (d);
4939
4940 if (warn_stack_larger_than && size > stack_larger_than_size)
4941 warning ("stack usage is %d bytes", size);
4942
4943 output_stack_adjust (-size + d_rounding,
4944 stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
4945
4946 if (frame_pointer_needed)
4947 frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
4948
4949 if (TARGET_SHCOMPACT
4950 && (current_function_args_info.call_cookie & ~ CALL_COOKIE_RET_TRAMP(1)))
4951 {
4952 /* This must NOT go through the PLT, otherwise mach and macl
4953 may be clobbered. */
4954 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
4955 gen_rtx_SYMBOL_REF (Pmode,
4956 "__GCC_shcompact_incoming_args"));
4957 emit_insn (gen_shcompact_incoming_args ());
4958 }
4959 }
4960
4961 void
sh_expand_epilogue(bool sibcall_p)4962 sh_expand_epilogue (bool sibcall_p)
4963 {
4964 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
4965 int d, i;
4966 int d_rounding = 0;
4967
4968 int save_flags = target_flags;
4969 int frame_size;
4970 int temp;
4971
4972 calc_live_regs (&d, live_regs_mask);
4973
4974 if (! sibcall_p)
4975 temp = 7;
4976 else if (TARGET_SHMEDIA)
4977 temp = 1;
4978 else
4979 {
4980 for (i = FIRST_GENERAL_REG; i <= LAST_GENERAL_REG; i++)
4981 if (TEST_HARD_REG_BIT (live_regs_mask, i))
4982 break;
4983 temp = (i <= LAST_GENERAL_REG) ? i : -1;
4984 }
4985
4986 if (TARGET_SH5 && d % (STACK_BOUNDARY / BITS_PER_UNIT))
4987 d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
4988 - d % (STACK_BOUNDARY / BITS_PER_UNIT));
4989
4990 frame_size = rounded_frame_size (d) - d_rounding;
4991
4992 if (frame_pointer_needed)
4993 {
4994 output_stack_adjust (frame_size, frame_pointer_rtx, temp, emit_insn);
4995
4996 /* We must avoid moving the stack pointer adjustment past code
4997 which reads from the local frame, else an interrupt could
4998 occur after the SP adjustment and clobber data in the local
4999 frame. */
5000 emit_insn (gen_blockage ());
5001 emit_insn (GEN_MOV (stack_pointer_rtx, frame_pointer_rtx));
5002 }
5003 else if (frame_size)
5004 {
5005 /* We must avoid moving the stack pointer adjustment past code
5006 which reads from the local frame, else an interrupt could
5007 occur after the SP adjustment and clobber data in the local
5008 frame. */
5009 emit_insn (gen_blockage ());
5010 output_stack_adjust (frame_size, stack_pointer_rtx, temp, emit_insn);
5011 }
5012
5013 if (SHMEDIA_REGS_STACK_ADJUST ())
5014 {
5015 emit_move_insn (gen_rtx_REG (Pmode, R0_REG),
5016 gen_rtx_SYMBOL_REF (Pmode,
5017 TARGET_FPU_ANY
5018 ? "__GCC_pop_shmedia_regs"
5019 : "__GCC_pop_shmedia_regs_nofpu"));
5020 /* This must NOT go through the PLT, otherwise mach and macl
5021 may be clobbered. */
5022 emit_insn (gen_shmedia_save_restore_regs_compact
5023 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5024 }
5025
5026 /* Pop all the registers. */
5027
5028 if (target_flags != save_flags)
5029 emit_insn (gen_toggle_sz ());
5030 if (TARGET_SH5)
5031 {
5032 int offset = d_rounding;
5033 int offset_in_r0 = -1;
5034 int sp_in_r0 = 0;
5035 int align;
5036 rtx r0 = gen_rtx_REG (Pmode, R0_REG);
5037
5038 /* We loop twice: first, we save 8-byte aligned registers in the
5039 higher addresses, that are known to be aligned. Then, we
5040 proceed to saving 32-bit registers that don't need 8-byte
5041 alignment. */
5042 for (align = 0; align <= 1; align++)
5043 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5044 if (live_regs_mask[i/32] & (1 << (i % 32)))
5045 {
5046 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5047 int reg = i;
5048 rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
5049
5050 if (mode == SFmode && (i % 2) == 0
5051 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5052 && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
5053 {
5054 mode = DFmode;
5055 i++;
5056 }
5057
5058 /* If we're doing the aligned pass and this is not aligned,
5059 or we're doing the unaligned pass and this is aligned,
5060 skip it. */
5061 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5062 == 0) != align)
5063 continue;
5064
5065 reg_rtx = gen_rtx_REG (mode, reg);
5066
5067 mem_rtx = gen_rtx_MEM (mode,
5068 gen_rtx_PLUS (Pmode,
5069 stack_pointer_rtx,
5070 GEN_INT (offset)));
5071
5072 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
5073
5074 mem_rtx = NULL_RTX;
5075
5076 try_post_inc:
5077 do
5078 if (HAVE_POST_INCREMENT
5079 && (offset == offset_in_r0
5080 || (offset + GET_MODE_SIZE (mode) != d + d_rounding
5081 && mem_rtx == NULL_RTX)
5082 || i == PR_REG || SPECIAL_REGISTER_P (i)))
5083 {
5084 post_inc = gen_rtx_MEM (mode,
5085 gen_rtx_POST_INC (Pmode, r0));
5086
5087 GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
5088 post_inc_ok);
5089
5090 post_inc = NULL_RTX;
5091
5092 break;
5093
5094 post_inc_ok:
5095 mem_rtx = NULL_RTX;
5096 }
5097 while (0);
5098
5099 if (mem_rtx != NULL_RTX)
5100 goto addr_ok;
5101
5102 if (offset_in_r0 == -1)
5103 {
5104 emit_move_insn (r0, GEN_INT (offset));
5105 offset_in_r0 = offset;
5106 }
5107 else if (offset != offset_in_r0)
5108 {
5109 emit_move_insn (r0,
5110 gen_rtx_PLUS
5111 (Pmode, r0,
5112 GEN_INT (offset - offset_in_r0)));
5113 offset_in_r0 += offset - offset_in_r0;
5114 }
5115
5116 if (post_inc != NULL_RTX)
5117 {
5118 if (! sp_in_r0)
5119 {
5120 emit_move_insn (r0,
5121 gen_rtx_PLUS
5122 (Pmode, r0, stack_pointer_rtx));
5123 sp_in_r0 = 1;
5124 }
5125
5126 mem_rtx = post_inc;
5127
5128 offset_in_r0 += GET_MODE_SIZE (mode);
5129 }
5130 else if (sp_in_r0)
5131 mem_rtx = gen_rtx_MEM (mode, r0);
5132 else
5133 mem_rtx = gen_rtx_MEM (mode,
5134 gen_rtx_PLUS (Pmode,
5135 stack_pointer_rtx,
5136 r0));
5137
5138 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
5139 && mem_rtx != post_inc)
5140 abort ();
5141
5142 addr_ok:
5143 if ((i == PR_REG || SPECIAL_REGISTER_P (i))
5144 && mem_rtx != post_inc)
5145 {
5146 insn = emit_move_insn (r0, mem_rtx);
5147 mem_rtx = r0;
5148 }
5149 else if (TARGET_REGISTER_P (i))
5150 {
5151 rtx r1 = gen_rtx_REG (mode, R1_REG);
5152
5153 insn = emit_move_insn (r1, mem_rtx);
5154 mem_rtx = r1;
5155 }
5156
5157 insn = emit_move_insn (reg_rtx, mem_rtx);
5158
5159 offset += GET_MODE_SIZE (mode);
5160 }
5161
5162 if (offset != d + d_rounding)
5163 abort ();
5164
5165 goto finish;
5166 }
5167 else
5168 d = 0;
5169 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
5170 pop (PR_REG);
5171 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5172 {
5173 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
5174
5175 if (j != PR_REG && live_regs_mask[j / 32] & (1 << (j % 32)))
5176 pop (j);
5177 }
5178 finish:
5179 if (target_flags != save_flags)
5180 emit_insn (gen_toggle_sz ());
5181 target_flags = save_flags;
5182
5183 output_stack_adjust (extra_push + current_function_pretend_args_size
5184 + d + d_rounding
5185 + current_function_args_info.stack_regs * 8,
5186 stack_pointer_rtx, (sibcall_p ? -1 : temp), emit_insn);
5187
5188 /* Switch back to the normal stack if necessary. */
5189 if (sp_switch)
5190 emit_insn (gen_sp_switch_2 ());
5191
5192 /* Tell flow the insn that pops PR isn't dead. */
5193 /* PR_REG will never be live in SHmedia mode, and we don't need to
5194 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5195 by the return pattern. */
5196 if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
5197 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
5198 }
5199
5200 static int sh_need_epilogue_known = 0;
5201
5202 int
sh_need_epilogue()5203 sh_need_epilogue ()
5204 {
5205 if (! sh_need_epilogue_known)
5206 {
5207 rtx epilogue;
5208
5209 start_sequence ();
5210 sh_expand_epilogue (0);
5211 epilogue = get_insns ();
5212 end_sequence ();
5213 sh_need_epilogue_known = (epilogue == NULL ? -1 : 1);
5214 }
5215 return sh_need_epilogue_known > 0;
5216 }
5217
5218 /* Clear variables at function end. */
5219
5220 static void
sh_output_function_epilogue(file,size)5221 sh_output_function_epilogue (file, size)
5222 FILE *file ATTRIBUTE_UNUSED;
5223 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
5224 {
5225 trap_exit = pragma_interrupt = pragma_trapa = pragma_nosave_low_regs = 0;
5226 sh_need_epilogue_known = 0;
5227 sp_switch = NULL_RTX;
5228 }
5229
5230 rtx
sh_builtin_saveregs()5231 sh_builtin_saveregs ()
5232 {
5233 /* First unnamed integer register. */
5234 int first_intreg = current_function_args_info.arg_count[(int) SH_ARG_INT];
5235 /* Number of integer registers we need to save. */
5236 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
5237 /* First unnamed SFmode float reg */
5238 int first_floatreg = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5239 /* Number of SFmode float regs to save. */
5240 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5241 rtx regbuf, fpregs;
5242 int bufsize, regno;
5243 HOST_WIDE_INT alias_set;
5244
5245 if (TARGET_SH5)
5246 {
5247 if (n_intregs)
5248 {
5249 int pushregs = n_intregs;
5250
5251 while (pushregs < NPARM_REGS (SImode) - 1
5252 && (CALL_COOKIE_INT_REG_GET
5253 (current_function_args_info.call_cookie,
5254 NPARM_REGS (SImode) - pushregs)
5255 == 1))
5256 {
5257 current_function_args_info.call_cookie
5258 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
5259 - pushregs, 1);
5260 pushregs++;
5261 }
5262
5263 if (pushregs == NPARM_REGS (SImode))
5264 current_function_args_info.call_cookie
5265 |= (CALL_COOKIE_INT_REG (0, 1)
5266 | CALL_COOKIE_STACKSEQ (pushregs - 1));
5267 else
5268 current_function_args_info.call_cookie
5269 |= CALL_COOKIE_STACKSEQ (pushregs);
5270
5271 current_function_pretend_args_size += 8 * n_intregs;
5272 }
5273 if (TARGET_SHCOMPACT)
5274 return const0_rtx;
5275 }
5276
5277 if (! TARGET_SH3E && ! TARGET_SH4 && ! TARGET_SH5)
5278 {
5279 error ("__builtin_saveregs not supported by this subtarget");
5280 return const0_rtx;
5281 }
5282
5283 if (TARGET_SHMEDIA)
5284 n_floatregs = 0;
5285
5286 /* Allocate block of memory for the regs. */
5287 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5288 Or can assign_stack_local accept a 0 SIZE argument? */
5289 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
5290
5291 if (TARGET_SHMEDIA)
5292 regbuf = gen_rtx_MEM (BLKmode,
5293 gen_rtx_REG (Pmode, ARG_POINTER_REGNUM));
5294 else if (n_floatregs & 1)
5295 {
5296 rtx addr;
5297
5298 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
5299 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
5300 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
5301 regbuf = change_address (regbuf, BLKmode, addr);
5302 }
5303 else
5304 regbuf = assign_stack_local (BLKmode, bufsize, 0);
5305 alias_set = get_varargs_alias_set ();
5306 set_mem_alias_set (regbuf, alias_set);
5307
5308 /* Save int args.
5309 This is optimized to only save the regs that are necessary. Explicitly
5310 named args need not be saved. */
5311 if (n_intregs > 0)
5312 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
5313 adjust_address (regbuf, BLKmode,
5314 n_floatregs * UNITS_PER_WORD),
5315 n_intregs, n_intregs * UNITS_PER_WORD);
5316
5317 if (TARGET_SHMEDIA)
5318 /* Return the address of the regbuf. */
5319 return XEXP (regbuf, 0);
5320
5321 /* Save float args.
5322 This is optimized to only save the regs that are necessary. Explicitly
5323 named args need not be saved.
5324 We explicitly build a pointer to the buffer because it halves the insn
5325 count when not optimizing (otherwise the pointer is built for each reg
5326 saved).
5327 We emit the moves in reverse order so that we can use predecrement. */
5328
5329 fpregs = gen_reg_rtx (Pmode);
5330 emit_move_insn (fpregs, XEXP (regbuf, 0));
5331 emit_insn (gen_addsi3 (fpregs, fpregs,
5332 GEN_INT (n_floatregs * UNITS_PER_WORD)));
5333 if (TARGET_SH4)
5334 {
5335 rtx mem;
5336 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
5337 {
5338 emit_insn (gen_addsi3 (fpregs, fpregs,
5339 GEN_INT (-2 * UNITS_PER_WORD)));
5340 mem = gen_rtx_MEM (DFmode, fpregs);
5341 set_mem_alias_set (mem, alias_set);
5342 emit_move_insn (mem,
5343 gen_rtx (REG, DFmode, BASE_ARG_REG (DFmode) + regno));
5344 }
5345 regno = first_floatreg;
5346 if (regno & 1)
5347 {
5348 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5349 mem = gen_rtx_MEM (SFmode, fpregs);
5350 set_mem_alias_set (mem, alias_set);
5351 emit_move_insn (mem,
5352 gen_rtx (REG, SFmode, BASE_ARG_REG (SFmode) + regno
5353 - (TARGET_LITTLE_ENDIAN != 0)));
5354 }
5355 }
5356 else
5357 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
5358 {
5359 rtx mem;
5360
5361 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (- UNITS_PER_WORD)));
5362 mem = gen_rtx_MEM (SFmode, fpregs);
5363 set_mem_alias_set (mem, alias_set);
5364 emit_move_insn (mem,
5365 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
5366 }
5367
5368 /* Return the address of the regbuf. */
5369 return XEXP (regbuf, 0);
5370 }
5371
5372 /* Define the `__builtin_va_list' type for the ABI. */
5373
5374 tree
sh_build_va_list()5375 sh_build_va_list ()
5376 {
5377 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5378 tree record;
5379
5380 if (TARGET_SH5 || (! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
5381 return ptr_type_node;
5382
5383 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5384
5385 f_next_o = build_decl (FIELD_DECL, get_identifier ("__va_next_o"),
5386 ptr_type_node);
5387 f_next_o_limit = build_decl (FIELD_DECL,
5388 get_identifier ("__va_next_o_limit"),
5389 ptr_type_node);
5390 f_next_fp = build_decl (FIELD_DECL, get_identifier ("__va_next_fp"),
5391 ptr_type_node);
5392 f_next_fp_limit = build_decl (FIELD_DECL,
5393 get_identifier ("__va_next_fp_limit"),
5394 ptr_type_node);
5395 f_next_stack = build_decl (FIELD_DECL, get_identifier ("__va_next_stack"),
5396 ptr_type_node);
5397
5398 DECL_FIELD_CONTEXT (f_next_o) = record;
5399 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
5400 DECL_FIELD_CONTEXT (f_next_fp) = record;
5401 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
5402 DECL_FIELD_CONTEXT (f_next_stack) = record;
5403
5404 TYPE_FIELDS (record) = f_next_o;
5405 TREE_CHAIN (f_next_o) = f_next_o_limit;
5406 TREE_CHAIN (f_next_o_limit) = f_next_fp;
5407 TREE_CHAIN (f_next_fp) = f_next_fp_limit;
5408 TREE_CHAIN (f_next_fp_limit) = f_next_stack;
5409
5410 layout_type (record);
5411
5412 return record;
5413 }
5414
5415 /* Implement `va_start' for varargs and stdarg. */
5416
5417 void
sh_va_start(valist,nextarg)5418 sh_va_start (valist, nextarg)
5419 tree valist;
5420 rtx nextarg;
5421 {
5422 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5423 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5424 tree t, u;
5425 int nfp, nint;
5426
5427 if (TARGET_SH5)
5428 {
5429 expand_builtin_saveregs ();
5430 std_expand_builtin_va_start (valist, nextarg);
5431 return;
5432 }
5433
5434 if ((! TARGET_SH3E && ! TARGET_SH4) || TARGET_HITACHI)
5435 {
5436 std_expand_builtin_va_start (valist, nextarg);
5437 return;
5438 }
5439
5440 f_next_o = TYPE_FIELDS (va_list_type_node);
5441 f_next_o_limit = TREE_CHAIN (f_next_o);
5442 f_next_fp = TREE_CHAIN (f_next_o_limit);
5443 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5444 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5445
5446 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5447 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5448 valist, f_next_o_limit);
5449 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp);
5450 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5451 valist, f_next_fp_limit);
5452 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5453 valist, f_next_stack);
5454
5455 /* Call __builtin_saveregs. */
5456 u = make_tree (ptr_type_node, expand_builtin_saveregs ());
5457 t = build (MODIFY_EXPR, ptr_type_node, next_fp, u);
5458 TREE_SIDE_EFFECTS (t) = 1;
5459 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5460
5461 nfp = current_function_args_info.arg_count[SH_ARG_FLOAT];
5462 if (nfp < 8)
5463 nfp = 8 - nfp;
5464 else
5465 nfp = 0;
5466 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5467 build_int_2 (UNITS_PER_WORD * nfp, 0)));
5468 t = build (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
5469 TREE_SIDE_EFFECTS (t) = 1;
5470 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5471
5472 t = build (MODIFY_EXPR, ptr_type_node, next_o, u);
5473 TREE_SIDE_EFFECTS (t) = 1;
5474 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5475
5476 nint = current_function_args_info.arg_count[SH_ARG_INT];
5477 if (nint < 4)
5478 nint = 4 - nint;
5479 else
5480 nint = 0;
5481 u = fold (build (PLUS_EXPR, ptr_type_node, u,
5482 build_int_2 (UNITS_PER_WORD * nint, 0)));
5483 t = build (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
5484 TREE_SIDE_EFFECTS (t) = 1;
5485 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5486
5487 u = make_tree (ptr_type_node, nextarg);
5488 t = build (MODIFY_EXPR, ptr_type_node, next_stack, u);
5489 TREE_SIDE_EFFECTS (t) = 1;
5490 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5491 }
5492
5493 /* Implement `va_arg'. */
5494
5495 rtx
sh_va_arg(valist,type)5496 sh_va_arg (valist, type)
5497 tree valist, type;
5498 {
5499 HOST_WIDE_INT size, rsize;
5500 tree tmp, pptr_type_node;
5501 rtx addr_rtx, r;
5502 rtx result;
5503 int pass_by_ref = MUST_PASS_IN_STACK (TYPE_MODE (type), type);
5504
5505 size = int_size_in_bytes (type);
5506 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5507 pptr_type_node = build_pointer_type (ptr_type_node);
5508
5509 if (pass_by_ref)
5510 type = build_pointer_type (type);
5511
5512 if (! TARGET_SH5 && (TARGET_SH3E || TARGET_SH4) && ! TARGET_HITACHI)
5513 {
5514 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
5515 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
5516 int pass_as_float;
5517 rtx lab_false, lab_over;
5518
5519 f_next_o = TYPE_FIELDS (va_list_type_node);
5520 f_next_o_limit = TREE_CHAIN (f_next_o);
5521 f_next_fp = TREE_CHAIN (f_next_o_limit);
5522 f_next_fp_limit = TREE_CHAIN (f_next_fp);
5523 f_next_stack = TREE_CHAIN (f_next_fp_limit);
5524
5525 next_o = build (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o);
5526 next_o_limit = build (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
5527 valist, f_next_o_limit);
5528 next_fp = build (COMPONENT_REF, TREE_TYPE (f_next_fp),
5529 valist, f_next_fp);
5530 next_fp_limit = build (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
5531 valist, f_next_fp_limit);
5532 next_stack = build (COMPONENT_REF, TREE_TYPE (f_next_stack),
5533 valist, f_next_stack);
5534
5535 if (TARGET_SH4)
5536 {
5537 pass_as_float = ((TREE_CODE (type) == REAL_TYPE && size <= 8)
5538 || (TREE_CODE (type) == COMPLEX_TYPE
5539 && TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
5540 && size <= 16));
5541 }
5542 else
5543 {
5544 pass_as_float = (TREE_CODE (type) == REAL_TYPE && size == 4);
5545 }
5546
5547 addr_rtx = gen_reg_rtx (Pmode);
5548 lab_false = gen_label_rtx ();
5549 lab_over = gen_label_rtx ();
5550
5551 if (pass_as_float)
5552 {
5553 int first_floatreg
5554 = current_function_args_info.arg_count[(int) SH_ARG_FLOAT];
5555 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
5556
5557 emit_cmp_and_jump_insns (expand_expr (next_fp, NULL_RTX, Pmode,
5558 EXPAND_NORMAL),
5559 expand_expr (next_fp_limit, NULL_RTX,
5560 Pmode, EXPAND_NORMAL),
5561 GE, const1_rtx, Pmode, 1, lab_false);
5562
5563 if (TYPE_ALIGN (type) > BITS_PER_WORD
5564 || (((TREE_CODE (type) == REAL_TYPE && size == 8) || size == 16)
5565 && (n_floatregs & 1)))
5566 {
5567 tmp = build (BIT_AND_EXPR, ptr_type_node, next_fp,
5568 build_int_2 (UNITS_PER_WORD, 0));
5569 tmp = build (PLUS_EXPR, ptr_type_node, next_fp, tmp);
5570 tmp = build (MODIFY_EXPR, ptr_type_node, next_fp, tmp);
5571 TREE_SIDE_EFFECTS (tmp) = 1;
5572 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5573 }
5574
5575 tmp = build1 (ADDR_EXPR, pptr_type_node, next_fp);
5576 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5577 if (r != addr_rtx)
5578 emit_move_insn (addr_rtx, r);
5579
5580 emit_jump_insn (gen_jump (lab_over));
5581 emit_barrier ();
5582 emit_label (lab_false);
5583
5584 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5585 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5586 if (r != addr_rtx)
5587 emit_move_insn (addr_rtx, r);
5588 }
5589 else
5590 {
5591 tmp = build (PLUS_EXPR, ptr_type_node, next_o,
5592 build_int_2 (rsize, 0));
5593
5594 emit_cmp_and_jump_insns (expand_expr (tmp, NULL_RTX, Pmode,
5595 EXPAND_NORMAL),
5596 expand_expr (next_o_limit, NULL_RTX,
5597 Pmode, EXPAND_NORMAL),
5598 GT, const1_rtx, Pmode, 1, lab_false);
5599
5600 tmp = build1 (ADDR_EXPR, pptr_type_node, next_o);
5601 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5602 if (r != addr_rtx)
5603 emit_move_insn (addr_rtx, r);
5604
5605 emit_jump_insn (gen_jump (lab_over));
5606 emit_barrier ();
5607 emit_label (lab_false);
5608
5609 if (size > 4 && ! TARGET_SH4)
5610 {
5611 tmp = build (MODIFY_EXPR, ptr_type_node, next_o, next_o_limit);
5612 TREE_SIDE_EFFECTS (tmp) = 1;
5613 expand_expr (tmp, const0_rtx, VOIDmode, EXPAND_NORMAL);
5614 }
5615
5616 tmp = build1 (ADDR_EXPR, pptr_type_node, next_stack);
5617 r = expand_expr (tmp, addr_rtx, Pmode, EXPAND_NORMAL);
5618 if (r != addr_rtx)
5619 emit_move_insn (addr_rtx, r);
5620 }
5621
5622 emit_label (lab_over);
5623
5624 tmp = make_tree (pptr_type_node, addr_rtx);
5625 valist = build1 (INDIRECT_REF, ptr_type_node, tmp);
5626 }
5627
5628 /* ??? In va-sh.h, there had been code to make values larger than
5629 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5630
5631 result = std_expand_builtin_va_arg (valist, type);
5632 if (pass_by_ref)
5633 {
5634 #ifdef POINTERS_EXTEND_UNSIGNED
5635 if (GET_MODE (addr) != Pmode)
5636 addr = convert_memory_address (Pmode, result);
5637 #endif
5638 result = gen_rtx_MEM (ptr_mode, force_reg (Pmode, result));
5639 set_mem_alias_set (result, get_varargs_alias_set ());
5640 }
5641 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
5642 argument to the varargs alias set. */
5643 return result;
5644 }
5645
5646 /* Define the offset between two registers, one to be eliminated, and
5647 the other its replacement, at the start of a routine. */
5648
5649 int
initial_elimination_offset(from,to)5650 initial_elimination_offset (from, to)
5651 int from;
5652 int to;
5653 {
5654 int regs_saved;
5655 int regs_saved_rounding = 0;
5656 int total_saved_regs_space;
5657 int total_auto_space;
5658 int save_flags = target_flags;
5659 int copy_flags;
5660
5661 HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
5662 calc_live_regs (®s_saved, live_regs_mask);
5663 regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
5664 if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
5665 regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
5666 - regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT));
5667
5668 total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
5669 copy_flags = target_flags;
5670 target_flags = save_flags;
5671
5672 total_saved_regs_space = regs_saved + regs_saved_rounding;
5673
5674 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
5675 return total_saved_regs_space + total_auto_space
5676 + current_function_args_info.byref_regs * 8;
5677
5678 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5679 return total_saved_regs_space + total_auto_space
5680 + current_function_args_info.byref_regs * 8;
5681
5682 /* Initial gap between fp and sp is 0. */
5683 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
5684 return 0;
5685
5686 if (from == RETURN_ADDRESS_POINTER_REGNUM
5687 && (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM))
5688 {
5689 if (TARGET_SH5)
5690 {
5691 int i, n = total_saved_regs_space;
5692 int align;
5693 int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
5694
5695 n += total_auto_space;
5696
5697 /* If it wasn't saved, there's not much we can do. */
5698 if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
5699 return n;
5700
5701 target_flags = copy_flags;
5702
5703 /* We loop twice: first, check 8-byte aligned registers,
5704 that are stored in the higher addresses, that are known
5705 to be aligned. Then, check 32-bit registers that don't
5706 need 8-byte alignment. */
5707 for (align = 1; align >= 0; align--)
5708 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
5709 if (live_regs_mask[i/32] & (1 << (i % 32)))
5710 {
5711 enum machine_mode mode = REGISTER_NATURAL_MODE (i);
5712
5713 if (mode == SFmode && (i % 2) == 1
5714 && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
5715 && (live_regs_mask[(i ^ 1) / 32]
5716 & (1 << ((i ^ 1) % 32))))
5717 {
5718 mode = DFmode;
5719 i--;
5720 }
5721
5722 /* If we're doing the aligned pass and this is not aligned,
5723 or we're doing the unaligned pass and this is aligned,
5724 skip it. */
5725 if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
5726 == 0) != align)
5727 continue;
5728
5729 n -= GET_MODE_SIZE (mode);
5730
5731 if (i == pr_reg)
5732 {
5733 target_flags = save_flags;
5734 return n;
5735 }
5736 }
5737
5738 abort ();
5739 }
5740 else
5741 return total_auto_space;
5742 }
5743
5744 abort ();
5745 }
5746
5747 /* Handle machine specific pragmas to be semi-compatible with Hitachi
5748 compiler. */
5749
5750 void
sh_pr_interrupt(pfile)5751 sh_pr_interrupt (pfile)
5752 cpp_reader *pfile ATTRIBUTE_UNUSED;
5753 {
5754 pragma_interrupt = 1;
5755 }
5756
5757 void
sh_pr_trapa(pfile)5758 sh_pr_trapa (pfile)
5759 cpp_reader *pfile ATTRIBUTE_UNUSED;
5760 {
5761 pragma_interrupt = pragma_trapa = 1;
5762 }
5763
5764 void
sh_pr_nosave_low_regs(pfile)5765 sh_pr_nosave_low_regs (pfile)
5766 cpp_reader *pfile ATTRIBUTE_UNUSED;
5767 {
5768 pragma_nosave_low_regs = 1;
5769 }
5770
5771 /* Generate 'handle_interrupt' attribute for decls */
5772
5773 static void
sh_insert_attributes(node,attributes)5774 sh_insert_attributes (node, attributes)
5775 tree node;
5776 tree * attributes;
5777 {
5778 if (! pragma_interrupt
5779 || TREE_CODE (node) != FUNCTION_DECL)
5780 return;
5781
5782 /* We are only interested in fields. */
5783 if (TREE_CODE_CLASS (TREE_CODE (node)) != 'd')
5784 return;
5785
5786 /* Add a 'handle_interrupt' attribute. */
5787 * attributes = tree_cons (get_identifier ("interrupt_handler"), NULL, * attributes);
5788
5789 return;
5790 }
5791
5792 /* Supported attributes:
5793
5794 interrupt_handler -- specifies this function is an interrupt handler.
5795
5796 sp_switch -- specifies an alternate stack for an interrupt handler
5797 to run on.
5798
5799 trap_exit -- use a trapa to exit an interrupt function instead of
5800 an rte instruction. */
5801
5802 const struct attribute_spec sh_attribute_table[] =
5803 {
5804 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5805 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute },
5806 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute },
5807 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute },
5808 { NULL, 0, 0, false, false, false, NULL }
5809 };
5810
5811 /* Handle an "interrupt_handler" attribute; arguments as in
5812 struct attribute_spec.handler. */
5813 static tree
sh_handle_interrupt_handler_attribute(node,name,args,flags,no_add_attrs)5814 sh_handle_interrupt_handler_attribute (node, name, args, flags, no_add_attrs)
5815 tree *node;
5816 tree name;
5817 tree args ATTRIBUTE_UNUSED;
5818 int flags ATTRIBUTE_UNUSED;
5819 bool *no_add_attrs;
5820 {
5821 if (TREE_CODE (*node) != FUNCTION_DECL)
5822 {
5823 warning ("`%s' attribute only applies to functions",
5824 IDENTIFIER_POINTER (name));
5825 *no_add_attrs = true;
5826 }
5827 else if (TARGET_SHCOMPACT)
5828 {
5829 error ("attribute interrupt_handler is not compatible with -m5-compact");
5830 *no_add_attrs = true;
5831 }
5832
5833 return NULL_TREE;
5834 }
5835
5836 /* Handle an "sp_switch" attribute; arguments as in
5837 struct attribute_spec.handler. */
5838 static tree
sh_handle_sp_switch_attribute(node,name,args,flags,no_add_attrs)5839 sh_handle_sp_switch_attribute (node, name, args, flags, no_add_attrs)
5840 tree *node;
5841 tree name;
5842 tree args;
5843 int flags ATTRIBUTE_UNUSED;
5844 bool *no_add_attrs;
5845 {
5846 if (TREE_CODE (*node) != FUNCTION_DECL)
5847 {
5848 warning ("`%s' attribute only applies to functions",
5849 IDENTIFIER_POINTER (name));
5850 *no_add_attrs = true;
5851 }
5852 else if (!pragma_interrupt)
5853 {
5854 /* The sp_switch attribute only has meaning for interrupt functions. */
5855 warning ("`%s' attribute only applies to interrupt functions",
5856 IDENTIFIER_POINTER (name));
5857 *no_add_attrs = true;
5858 }
5859 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
5860 {
5861 /* The argument must be a constant string. */
5862 warning ("`%s' attribute argument not a string constant",
5863 IDENTIFIER_POINTER (name));
5864 *no_add_attrs = true;
5865 }
5866 else
5867 {
5868 sp_switch = gen_rtx_SYMBOL_REF (VOIDmode,
5869 TREE_STRING_POINTER (TREE_VALUE (args)));
5870 }
5871
5872 return NULL_TREE;
5873 }
5874
5875 /* Handle an "trap_exit" attribute; arguments as in
5876 struct attribute_spec.handler. */
5877 static tree
sh_handle_trap_exit_attribute(node,name,args,flags,no_add_attrs)5878 sh_handle_trap_exit_attribute (node, name, args, flags, no_add_attrs)
5879 tree *node;
5880 tree name;
5881 tree args;
5882 int flags ATTRIBUTE_UNUSED;
5883 bool *no_add_attrs;
5884 {
5885 if (TREE_CODE (*node) != FUNCTION_DECL)
5886 {
5887 warning ("`%s' attribute only applies to functions",
5888 IDENTIFIER_POINTER (name));
5889 *no_add_attrs = true;
5890 }
5891 else if (!pragma_interrupt)
5892 {
5893 /* The trap_exit attribute only has meaning for interrupt functions. */
5894 warning ("`%s' attribute only applies to interrupt functions",
5895 IDENTIFIER_POINTER (name));
5896 *no_add_attrs = true;
5897 }
5898 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
5899 {
5900 /* The argument must be a constant integer. */
5901 warning ("`%s' attribute argument not an integer constant",
5902 IDENTIFIER_POINTER (name));
5903 *no_add_attrs = true;
5904 }
5905 else
5906 {
5907 trap_exit = TREE_INT_CST_LOW (TREE_VALUE (args));
5908 }
5909
5910 return NULL_TREE;
5911 }
5912
5913 int
sh_cfun_interrupt_handler_p()5914 sh_cfun_interrupt_handler_p ()
5915 {
5916 return (lookup_attribute ("interrupt_handler",
5917 DECL_ATTRIBUTES (current_function_decl))
5918 != NULL_TREE);
5919 }
5920
5921 /* Predicates used by the templates. */
5922
5923 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
5924 Used only in general_movsrc_operand. */
5925
5926 int
system_reg_operand(op,mode)5927 system_reg_operand (op, mode)
5928 rtx op;
5929 enum machine_mode mode ATTRIBUTE_UNUSED;
5930 {
5931 switch (REGNO (op))
5932 {
5933 case PR_REG:
5934 case MACL_REG:
5935 case MACH_REG:
5936 return 1;
5937 }
5938 return 0;
5939 }
5940
5941 /* Returns 1 if OP can be source of a simple move operation.
5942 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
5943 invalid as are subregs of system registers. */
5944
5945 int
general_movsrc_operand(op,mode)5946 general_movsrc_operand (op, mode)
5947 rtx op;
5948 enum machine_mode mode;
5949 {
5950 if (GET_CODE (op) == MEM)
5951 {
5952 rtx inside = XEXP (op, 0);
5953 if (GET_CODE (inside) == CONST)
5954 inside = XEXP (inside, 0);
5955
5956 if (GET_CODE (inside) == LABEL_REF)
5957 return 1;
5958
5959 if (GET_CODE (inside) == PLUS
5960 && GET_CODE (XEXP (inside, 0)) == LABEL_REF
5961 && GET_CODE (XEXP (inside, 1)) == CONST_INT)
5962 return 1;
5963
5964 /* Only post inc allowed. */
5965 if (GET_CODE (inside) == PRE_DEC)
5966 return 0;
5967 }
5968
5969 if ((mode == QImode || mode == HImode)
5970 && (GET_CODE (op) == SUBREG
5971 && GET_CODE (XEXP (op, 0)) == REG
5972 && system_reg_operand (XEXP (op, 0), mode)))
5973 return 0;
5974
5975 return general_operand (op, mode);
5976 }
5977
5978 /* Returns 1 if OP can be a destination of a move.
5979 Same as general_operand, but no preinc allowed. */
5980
5981 int
general_movdst_operand(op,mode)5982 general_movdst_operand (op, mode)
5983 rtx op;
5984 enum machine_mode mode;
5985 {
5986 /* Only pre dec allowed. */
5987 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == POST_INC)
5988 return 0;
5989
5990 return general_operand (op, mode);
5991 }
5992
5993 /* Returns 1 if OP is a normal arithmetic register. */
5994
5995 int
arith_reg_operand(op,mode)5996 arith_reg_operand (op, mode)
5997 rtx op;
5998 enum machine_mode mode;
5999 {
6000 if (register_operand (op, mode))
6001 {
6002 int regno;
6003
6004 if (GET_CODE (op) == REG)
6005 regno = REGNO (op);
6006 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
6007 regno = REGNO (SUBREG_REG (op));
6008 else
6009 return 1;
6010
6011 return (regno != T_REG && regno != PR_REG
6012 && ! TARGET_REGISTER_P (regno)
6013 && (regno != FPUL_REG || TARGET_SH4)
6014 && regno != MACH_REG && regno != MACL_REG);
6015 }
6016 return 0;
6017 }
6018
6019 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
6020 because this would lead to missing sign extensions when truncating from
6021 DImode to SImode. */
6022 int
arith_reg_dest(op,mode)6023 arith_reg_dest (op, mode)
6024 rtx op;
6025 enum machine_mode mode;
6026 {
6027 if (mode == DImode && GET_CODE (op) == SUBREG
6028 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
6029 return 0;
6030 return arith_reg_operand (op, mode);
6031 }
6032
6033 int
int_gpr_dest(op,mode)6034 int_gpr_dest (op, mode)
6035 rtx op;
6036 enum machine_mode mode ATTRIBUTE_UNUSED;
6037 {
6038 enum machine_mode op_mode = GET_MODE (op);
6039
6040 if (GET_MODE_CLASS (op_mode) != MODE_INT
6041 || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
6042 return 0;
6043 if (! reload_completed)
6044 return 0;
6045 return true_regnum (op) <= LAST_GENERAL_REG;
6046 }
6047
6048 int
fp_arith_reg_operand(op,mode)6049 fp_arith_reg_operand (op, mode)
6050 rtx op;
6051 enum machine_mode mode;
6052 {
6053 if (register_operand (op, mode))
6054 {
6055 int regno;
6056
6057 if (GET_CODE (op) == REG)
6058 regno = REGNO (op);
6059 else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
6060 regno = REGNO (SUBREG_REG (op));
6061 else
6062 return 1;
6063
6064 return (regno >= FIRST_PSEUDO_REGISTER
6065 || FP_REGISTER_P (regno));
6066 }
6067 return 0;
6068 }
6069
6070 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
6071
6072 int
arith_operand(op,mode)6073 arith_operand (op, mode)
6074 rtx op;
6075 enum machine_mode mode;
6076 {
6077 if (arith_reg_operand (op, mode))
6078 return 1;
6079
6080 if (TARGET_SHMEDIA)
6081 {
6082 /* FIXME: We should be checking whether the CONST_INT fits in a
6083 CONST_OK_FOR_J here, but this causes reload_cse to crash when
6084 attempting to transform a sequence of two 64-bit sets of the
6085 same register from literal constants into a set and an add,
6086 when the difference is too wide for an add. */
6087 if (GET_CODE (op) == CONST_INT
6088 || EXTRA_CONSTRAINT_S (op))
6089 return 1;
6090 else
6091 return 0;
6092 }
6093 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
6094 return 1;
6095
6096 return 0;
6097 }
6098
6099 /* Returns 1 if OP is a valid source operand for a compare insn. */
6100
6101 int
arith_reg_or_0_operand(op,mode)6102 arith_reg_or_0_operand (op, mode)
6103 rtx op;
6104 enum machine_mode mode;
6105 {
6106 if (arith_reg_operand (op, mode))
6107 return 1;
6108
6109 if (EXTRA_CONSTRAINT_U (op))
6110 return 1;
6111
6112 return 0;
6113 }
6114
6115 /* Return 1 if OP is a valid source operand for an SHmedia operation
6116 that takes either a register or a 6-bit immediate. */
6117
6118 int
shmedia_6bit_operand(op,mode)6119 shmedia_6bit_operand (op, mode)
6120 rtx op;
6121 enum machine_mode mode;
6122 {
6123 return (arith_reg_operand (op, mode)
6124 || (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op))));
6125 }
6126
6127 /* Returns 1 if OP is a valid source operand for a logical operation. */
6128
6129 int
logical_operand(op,mode)6130 logical_operand (op, mode)
6131 rtx op;
6132 enum machine_mode mode;
6133 {
6134 if (arith_reg_operand (op, mode))
6135 return 1;
6136
6137 if (TARGET_SHMEDIA)
6138 {
6139 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_P (INTVAL (op)))
6140 return 1;
6141 else
6142 return 0;
6143 }
6144 else if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
6145 return 1;
6146
6147 return 0;
6148 }
6149
6150 int
and_operand(op,mode)6151 and_operand (op, mode)
6152 rtx op;
6153 enum machine_mode mode;
6154 {
6155 if (logical_operand (op, mode))
6156 return 1;
6157
6158 /* Check mshflo.l / mshflhi.l opportunities. */
6159 if (TARGET_SHMEDIA
6160 && mode == DImode
6161 && GET_CODE (op) == CONST_INT
6162 && (INTVAL (op) == (unsigned) 0xffffffff
6163 || INTVAL (op) == (HOST_WIDE_INT) -1 << 32))
6164 return 1;
6165
6166 return 0;
6167 }
6168
6169 /* Nonzero if OP is a floating point value with value 0.0. */
6170
6171 int
fp_zero_operand(op)6172 fp_zero_operand (op)
6173 rtx op;
6174 {
6175 REAL_VALUE_TYPE r;
6176
6177 if (GET_MODE (op) != SFmode)
6178 return 0;
6179
6180 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6181 return REAL_VALUES_EQUAL (r, dconst0) && ! REAL_VALUE_MINUS_ZERO (r);
6182 }
6183
6184 /* Nonzero if OP is a floating point value with value 1.0. */
6185
6186 int
fp_one_operand(op)6187 fp_one_operand (op)
6188 rtx op;
6189 {
6190 REAL_VALUE_TYPE r;
6191
6192 if (GET_MODE (op) != SFmode)
6193 return 0;
6194
6195 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
6196 return REAL_VALUES_EQUAL (r, dconst1);
6197 }
6198
6199 /* For -m4 and -m4-single-only, mode switching is used. If we are
6200 compiling without -mfmovd, movsf_ie isn't taken into account for
6201 mode switching. We could check in machine_dependent_reorg for
6202 cases where we know we are in single precision mode, but there is
6203 interface to find that out during reload, so we must avoid
6204 choosing an fldi alternative during reload and thus failing to
6205 allocate a scratch register for the constant loading. */
6206 int
fldi_ok()6207 fldi_ok ()
6208 {
6209 return ! TARGET_SH4 || TARGET_FMOVD || reload_completed;
6210 }
6211
6212 int
tertiary_reload_operand(op,mode)6213 tertiary_reload_operand (op, mode)
6214 rtx op;
6215 enum machine_mode mode ATTRIBUTE_UNUSED;
6216 {
6217 enum rtx_code code = GET_CODE (op);
6218 return code == MEM || (TARGET_SH4 && code == CONST_DOUBLE);
6219 }
6220
6221 int
fpscr_operand(op,mode)6222 fpscr_operand (op, mode)
6223 rtx op;
6224 enum machine_mode mode ATTRIBUTE_UNUSED;
6225 {
6226 return (GET_CODE (op) == REG && REGNO (op) == FPSCR_REG
6227 && GET_MODE (op) == PSImode);
6228 }
6229
6230 int
fpul_operand(op,mode)6231 fpul_operand (op, mode)
6232 rtx op;
6233 enum machine_mode mode;
6234 {
6235 if (TARGET_SHMEDIA)
6236 return fp_arith_reg_operand (op, mode);
6237
6238 return (GET_CODE (op) == REG
6239 && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
6240 && GET_MODE (op) == mode);
6241 }
6242
6243 int
symbol_ref_operand(op,mode)6244 symbol_ref_operand (op, mode)
6245 rtx op;
6246 enum machine_mode mode ATTRIBUTE_UNUSED;
6247 {
6248 return (GET_CODE (op) == SYMBOL_REF);
6249 }
6250
6251 int
commutative_float_operator(op,mode)6252 commutative_float_operator (op, mode)
6253 rtx op;
6254 enum machine_mode mode;
6255 {
6256 if (GET_MODE (op) != mode)
6257 return 0;
6258 switch (GET_CODE (op))
6259 {
6260 case PLUS:
6261 case MULT:
6262 return 1;
6263 default:
6264 break;
6265 }
6266 return 0;
6267 }
6268
6269 int
noncommutative_float_operator(op,mode)6270 noncommutative_float_operator (op, mode)
6271 rtx op;
6272 enum machine_mode mode;
6273 {
6274 if (GET_MODE (op) != mode)
6275 return 0;
6276 switch (GET_CODE (op))
6277 {
6278 case MINUS:
6279 case DIV:
6280 return 1;
6281 default:
6282 break;
6283 }
6284 return 0;
6285 }
6286
6287 int
unary_float_operator(op,mode)6288 unary_float_operator (op, mode)
6289 rtx op;
6290 enum machine_mode mode;
6291 {
6292 if (GET_MODE (op) != mode)
6293 return 0;
6294 switch (GET_CODE (op))
6295 {
6296 case ABS:
6297 case NEG:
6298 case SQRT:
6299 return 1;
6300 default:
6301 break;
6302 }
6303 return 0;
6304 }
6305
6306 int
binary_float_operator(op,mode)6307 binary_float_operator (op, mode)
6308 rtx op;
6309 enum machine_mode mode;
6310 {
6311 if (GET_MODE (op) != mode)
6312 return 0;
6313 switch (GET_CODE (op))
6314 {
6315 case PLUS:
6316 case MINUS:
6317 case MULT:
6318 case DIV:
6319 return 1;
6320 default:
6321 break;
6322 }
6323 return 0;
6324 }
6325
6326 int
binary_logical_operator(op,mode)6327 binary_logical_operator (op, mode)
6328 rtx op;
6329 enum machine_mode mode;
6330 {
6331 if (GET_MODE (op) != mode)
6332 return 0;
6333 switch (GET_CODE (op))
6334 {
6335 case IOR:
6336 case AND:
6337 case XOR:
6338 return 1;
6339 default:
6340 break;
6341 }
6342 return 0;
6343 }
6344
6345 int
equality_comparison_operator(op,mode)6346 equality_comparison_operator (op, mode)
6347 rtx op;
6348 enum machine_mode mode;
6349 {
6350 return ((mode == VOIDmode || GET_MODE (op) == mode)
6351 && (GET_CODE (op) == EQ || GET_CODE (op) == NE));
6352 }
6353
greater_comparison_operator(op,mode)6354 int greater_comparison_operator (op, mode)
6355 rtx op;
6356 enum machine_mode mode;
6357 {
6358 if (mode != VOIDmode && GET_MODE (op) == mode)
6359 return 0;
6360 switch (GET_CODE (op))
6361 {
6362 case GT:
6363 case GE:
6364 case GTU:
6365 case GEU:
6366 return 1;
6367 default:
6368 return 0;
6369 }
6370 }
6371
less_comparison_operator(op,mode)6372 int less_comparison_operator (op, mode)
6373 rtx op;
6374 enum machine_mode mode;
6375 {
6376 if (mode != VOIDmode && GET_MODE (op) == mode)
6377 return 0;
6378 switch (GET_CODE (op))
6379 {
6380 case LT:
6381 case LE:
6382 case LTU:
6383 case LEU:
6384 return 1;
6385 default:
6386 return 0;
6387 }
6388 }
6389
6390 /* Accept pseudos and branch target registers. */
6391 int
target_reg_operand(op,mode)6392 target_reg_operand (op, mode)
6393 rtx op;
6394 enum machine_mode mode;
6395 {
6396 if (mode != DImode
6397 || GET_MODE (op) != DImode)
6398 return 0;
6399
6400 if (GET_CODE (op) == SUBREG)
6401 op = XEXP (op, 0);
6402
6403 if (GET_CODE (op) != REG)
6404 return 0;
6405
6406 /* We must protect ourselves from matching pseudos that are virtual
6407 register, because they will eventually be replaced with hardware
6408 registers that aren't branch-target registers. */
6409 if (REGNO (op) > LAST_VIRTUAL_REGISTER
6410 || TARGET_REGISTER_P (REGNO (op)))
6411 return 1;
6412
6413 return 0;
6414 }
6415
6416 /* Same as target_reg_operand, except that label_refs and symbol_refs
6417 are accepted before reload. */
6418 int
target_operand(op,mode)6419 target_operand (op, mode)
6420 rtx op;
6421 enum machine_mode mode;
6422 {
6423 if (mode != DImode)
6424 return 0;
6425
6426 if ((GET_MODE (op) == DImode || GET_MODE (op) == VOIDmode)
6427 && EXTRA_CONSTRAINT_T (op))
6428 return ! reload_completed;
6429
6430 return target_reg_operand (op, mode);
6431 }
6432
6433 int
mextr_bit_offset(op,mode)6434 mextr_bit_offset (op, mode)
6435 rtx op;
6436 enum machine_mode mode ATTRIBUTE_UNUSED;
6437 {
6438 HOST_WIDE_INT i;
6439
6440 if (GET_CODE (op) != CONST_INT)
6441 return 0;
6442 i = INTVAL (op);
6443 return i >= 1*8 && i <= 7*8 && (i & 7) == 0;
6444 }
6445
6446 int
extend_reg_operand(op,mode)6447 extend_reg_operand (op, mode)
6448 rtx op;
6449 enum machine_mode mode;
6450 {
6451 return (GET_CODE (op) == TRUNCATE
6452 ? arith_operand
6453 : arith_reg_operand) (op, mode);
6454 }
6455
6456 int
trunc_hi_operand(op,mode)6457 trunc_hi_operand (op, mode)
6458 rtx op;
6459 enum machine_mode mode;
6460 {
6461 enum machine_mode op_mode = GET_MODE (op);
6462
6463 if (op_mode != SImode && op_mode != DImode
6464 && op_mode != V4HImode && op_mode != V2SImode)
6465 return 0;
6466 return extend_reg_operand (op, mode);
6467 }
6468
6469 int
extend_reg_or_0_operand(op,mode)6470 extend_reg_or_0_operand (op, mode)
6471 rtx op;
6472 enum machine_mode mode;
6473 {
6474 return (GET_CODE (op) == TRUNCATE
6475 ? arith_operand
6476 : arith_reg_or_0_operand) (op, mode);
6477 }
6478
6479 int
general_extend_operand(op,mode)6480 general_extend_operand (op, mode)
6481 rtx op;
6482 enum machine_mode mode;
6483 {
6484 return (GET_CODE (op) == TRUNCATE
6485 ? arith_operand
6486 : nonimmediate_operand) (op, mode);
6487 }
6488
6489 int
inqhi_operand(op,mode)6490 inqhi_operand (op, mode)
6491 rtx op;
6492 enum machine_mode mode;
6493 {
6494 if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
6495 return 0;
6496 op = XEXP (op, 0);
6497 /* Can't use true_regnum here because copy_cost wants to know about
6498 SECONDARY_INPUT_RELOAD_CLASS. */
6499 return GET_CODE (op) == REG && FP_REGISTER_P (REGNO (op));
6500 }
6501
6502 int
sh_rep_vec(v,mode)6503 sh_rep_vec (v, mode)
6504 rtx v;
6505 enum machine_mode mode;
6506 {
6507 int i;
6508 rtx x, y;
6509
6510 if ((GET_CODE (v) != CONST_VECTOR && GET_CODE (v) != PARALLEL)
6511 || (GET_MODE (v) != mode && mode != VOIDmode))
6512 return 0;
6513 i = XVECLEN (v, 0) - 2;
6514 x = XVECEXP (v, 0, i + 1);
6515 if (GET_MODE_UNIT_SIZE (mode) == 1)
6516 {
6517 y = XVECEXP (v, 0, i);
6518 for (i -= 2 ; i >= 0; i -= 2)
6519 if (! rtx_equal_p (XVECEXP (v, 0, i + 1), x)
6520 || ! rtx_equal_p (XVECEXP (v, 0, i), y))
6521 return 0;
6522 }
6523 else
6524 for (; i >= 0; i--)
6525 if (XVECEXP (v, 0, i) != x)
6526 return 0;
6527 return 1;
6528 }
6529
6530 /* Determine if V is a constant vector matching MODE with only one element
6531 that is not a sign extension. Two byte-sized elements count as one. */
6532 int
sh_1el_vec(v,mode)6533 sh_1el_vec (v, mode)
6534 rtx v;
6535 enum machine_mode mode;
6536 {
6537 int unit_size;
6538 int i, last, least, sign_ix;
6539 rtx sign;
6540
6541 if (GET_CODE (v) != CONST_VECTOR
6542 || (GET_MODE (v) != mode && mode != VOIDmode))
6543 return 0;
6544 /* Determine numbers of last and of least significat elements. */
6545 last = XVECLEN (v, 0) - 1;
6546 least = TARGET_LITTLE_ENDIAN ? 0 : last;
6547 if (GET_CODE (XVECEXP (v, 0, least)) != CONST_INT)
6548 return 0;
6549 sign_ix = least;
6550 if (GET_MODE_UNIT_SIZE (mode) == 1)
6551 sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
6552 if (GET_CODE (XVECEXP (v, 0, sign_ix)) != CONST_INT)
6553 return 0;
6554 unit_size = GET_MODE_UNIT_SIZE (GET_MODE (v));
6555 sign = (INTVAL (XVECEXP (v, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
6556 ? constm1_rtx : const0_rtx);
6557 i = XVECLEN (v, 0) - 1;
6558 do
6559 if (i != least && i != sign_ix && XVECEXP (v, 0, i) != sign)
6560 return 0;
6561 while (--i);
6562 return 1;
6563 }
6564
6565 int
sh_const_vec(v,mode)6566 sh_const_vec (v, mode)
6567 rtx v;
6568 enum machine_mode mode;
6569 {
6570 int i;
6571
6572 if (GET_CODE (v) != CONST_VECTOR
6573 || (GET_MODE (v) != mode && mode != VOIDmode))
6574 return 0;
6575 i = XVECLEN (v, 0) - 1;
6576 for (; i >= 0; i--)
6577 if (GET_CODE (XVECEXP (v, 0, i)) != CONST_INT)
6578 return 0;
6579 return 1;
6580 }
6581
6582 /* Return the destination address of a branch. */
6583
6584 static int
branch_dest(branch)6585 branch_dest (branch)
6586 rtx branch;
6587 {
6588 rtx dest = SET_SRC (PATTERN (branch));
6589 int dest_uid;
6590
6591 if (GET_CODE (dest) == IF_THEN_ELSE)
6592 dest = XEXP (dest, 1);
6593 dest = XEXP (dest, 0);
6594 dest_uid = INSN_UID (dest);
6595 return INSN_ADDRESSES (dest_uid);
6596 }
6597
6598 /* Return nonzero if REG is not used after INSN.
6599 We assume REG is a reload reg, and therefore does
6600 not live past labels. It may live past calls or jumps though. */
6601 int
reg_unused_after(reg,insn)6602 reg_unused_after (reg, insn)
6603 rtx reg;
6604 rtx insn;
6605 {
6606 enum rtx_code code;
6607 rtx set;
6608
6609 /* If the reg is set by this instruction, then it is safe for our
6610 case. Disregard the case where this is a store to memory, since
6611 we are checking a register used in the store address. */
6612 set = single_set (insn);
6613 if (set && GET_CODE (SET_DEST (set)) != MEM
6614 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6615 return 1;
6616
6617 while ((insn = NEXT_INSN (insn)))
6618 {
6619 code = GET_CODE (insn);
6620
6621 #if 0
6622 /* If this is a label that existed before reload, then the register
6623 if dead here. However, if this is a label added by reorg, then
6624 the register may still be live here. We can't tell the difference,
6625 so we just ignore labels completely. */
6626 if (code == CODE_LABEL)
6627 return 1;
6628 /* else */
6629 #endif
6630
6631 if (code == JUMP_INSN)
6632 return 0;
6633
6634 /* If this is a sequence, we must handle them all at once.
6635 We could have for instance a call that sets the target register,
6636 and an insn in a delay slot that uses the register. In this case,
6637 we must return 0. */
6638 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
6639 {
6640 int i;
6641 int retval = 0;
6642
6643 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
6644 {
6645 rtx this_insn = XVECEXP (PATTERN (insn), 0, i);
6646 rtx set = single_set (this_insn);
6647
6648 if (GET_CODE (this_insn) == CALL_INSN)
6649 code = CALL_INSN;
6650 else if (GET_CODE (this_insn) == JUMP_INSN)
6651 {
6652 if (INSN_ANNULLED_BRANCH_P (this_insn))
6653 return 0;
6654 code = JUMP_INSN;
6655 }
6656
6657 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6658 return 0;
6659 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6660 {
6661 if (GET_CODE (SET_DEST (set)) != MEM)
6662 retval = 1;
6663 else
6664 return 0;
6665 }
6666 if (set == 0
6667 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
6668 return 0;
6669 }
6670 if (retval == 1)
6671 return 1;
6672 else if (code == JUMP_INSN)
6673 return 0;
6674 }
6675 else if (GET_RTX_CLASS (code) == 'i')
6676 {
6677 rtx set = single_set (insn);
6678
6679 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
6680 return 0;
6681 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
6682 return GET_CODE (SET_DEST (set)) != MEM;
6683 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
6684 return 0;
6685 }
6686
6687 if (code == CALL_INSN && call_used_regs[REGNO (reg)])
6688 return 1;
6689 }
6690 return 1;
6691 }
6692
6693 #include "ggc.h"
6694
6695 static GTY(()) rtx fpscr_rtx;
6696 rtx
get_fpscr_rtx()6697 get_fpscr_rtx ()
6698 {
6699 if (! fpscr_rtx)
6700 {
6701 fpscr_rtx = gen_rtx (REG, PSImode, FPSCR_REG);
6702 REG_USERVAR_P (fpscr_rtx) = 1;
6703 mark_user_reg (fpscr_rtx);
6704 }
6705 if (! reload_completed || mdep_reorg_phase != SH_AFTER_MDEP_REORG)
6706 mark_user_reg (fpscr_rtx);
6707 return fpscr_rtx;
6708 }
6709
6710 void
emit_sf_insn(pat)6711 emit_sf_insn (pat)
6712 rtx pat;
6713 {
6714 emit_insn (pat);
6715 }
6716
6717 void
emit_df_insn(pat)6718 emit_df_insn (pat)
6719 rtx pat;
6720 {
6721 emit_insn (pat);
6722 }
6723
6724 void
6725 expand_sf_unop (fun, operands)
6726 rtx (*fun) PARAMS ((rtx, rtx, rtx));
6727 rtx *operands;
6728 {
6729 emit_sf_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
6730 }
6731
6732 void
6733 expand_sf_binop (fun, operands)
6734 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
6735 rtx *operands;
6736 {
6737 emit_sf_insn ((*fun) (operands[0], operands[1], operands[2],
6738 get_fpscr_rtx ()));
6739 }
6740
6741 void
6742 expand_df_unop (fun, operands)
6743 rtx (*fun) PARAMS ((rtx, rtx, rtx));
6744 rtx *operands;
6745 {
6746 emit_df_insn ((*fun) (operands[0], operands[1], get_fpscr_rtx ()));
6747 }
6748
6749 void
6750 expand_df_binop (fun, operands)
6751 rtx (*fun) PARAMS ((rtx, rtx, rtx, rtx));
6752 rtx *operands;
6753 {
6754 emit_df_insn ((*fun) (operands[0], operands[1], operands[2],
6755 get_fpscr_rtx ()));
6756 }
6757
6758 /* ??? gcc does flow analysis strictly after common subexpression
6759 elimination. As a result, common subespression elimination fails
6760 when there are some intervening statements setting the same register.
6761 If we did nothing about this, this would hurt the precision switching
6762 for SH4 badly. There is some cse after reload, but it is unable to
6763 undo the extra register pressure from the unused instructions, and
6764 it cannot remove auto-increment loads.
6765
6766 A C code example that shows this flow/cse weakness for (at least) SH
6767 and sparc (as of gcc ss-970706) is this:
6768
6769 double
6770 f(double a)
6771 {
6772 double d;
6773 d = 0.1;
6774 a += d;
6775 d = 1.1;
6776 d = 0.1;
6777 a *= d;
6778 return a;
6779 }
6780
6781 So we add another pass before common subexpression elimination, to
6782 remove assignments that are dead due to a following assignment in the
6783 same basic block. */
6784
6785 static void
mark_use(x,reg_set_block)6786 mark_use (x, reg_set_block)
6787 rtx x, *reg_set_block;
6788 {
6789 enum rtx_code code;
6790
6791 if (! x)
6792 return;
6793 code = GET_CODE (x);
6794 switch (code)
6795 {
6796 case REG:
6797 {
6798 int regno = REGNO (x);
6799 int nregs = (regno < FIRST_PSEUDO_REGISTER
6800 ? HARD_REGNO_NREGS (regno, GET_MODE (x))
6801 : 1);
6802 do
6803 {
6804 reg_set_block[regno + nregs - 1] = 0;
6805 }
6806 while (--nregs);
6807 break;
6808 }
6809 case SET:
6810 {
6811 rtx dest = SET_DEST (x);
6812
6813 if (GET_CODE (dest) == SUBREG)
6814 dest = SUBREG_REG (dest);
6815 if (GET_CODE (dest) != REG)
6816 mark_use (dest, reg_set_block);
6817 mark_use (SET_SRC (x), reg_set_block);
6818 break;
6819 }
6820 case CLOBBER:
6821 break;
6822 default:
6823 {
6824 const char *fmt = GET_RTX_FORMAT (code);
6825 int i, j;
6826 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6827 {
6828 if (fmt[i] == 'e')
6829 mark_use (XEXP (x, i), reg_set_block);
6830 else if (fmt[i] == 'E')
6831 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6832 mark_use (XVECEXP (x, i, j), reg_set_block);
6833 }
6834 break;
6835 }
6836 }
6837 }
6838
6839 static rtx get_free_reg PARAMS ((HARD_REG_SET));
6840
6841 /* This function returns a register to use to load the address to load
6842 the fpscr from. Currently it always returns r1 or r7, but when we are
6843 able to use pseudo registers after combine, or have a better mechanism
6844 for choosing a register, it should be done here. */
6845 /* REGS_LIVE is the liveness information for the point for which we
6846 need this allocation. In some bare-bones exit blocks, r1 is live at the
6847 start. We can even have all of r0..r3 being live:
6848 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
6849 INSN before which new insns are placed with will clobber the register
6850 we return. If a basic block consists only of setting the return value
6851 register to a pseudo and using that register, the return value is not
6852 live before or after this block, yet we we'll insert our insns right in
6853 the middle. */
6854
6855 static rtx
get_free_reg(regs_live)6856 get_free_reg (regs_live)
6857 HARD_REG_SET regs_live;
6858 {
6859 if (! TEST_HARD_REG_BIT (regs_live, 1))
6860 return gen_rtx_REG (Pmode, 1);
6861
6862 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
6863 there shouldn't be anything but a jump before the function end. */
6864 if (! TEST_HARD_REG_BIT (regs_live, 7))
6865 return gen_rtx_REG (Pmode, 7);
6866
6867 abort ();
6868 }
6869
6870 /* This function will set the fpscr from memory.
6871 MODE is the mode we are setting it to. */
6872 void
fpscr_set_from_mem(mode,regs_live)6873 fpscr_set_from_mem (mode, regs_live)
6874 int mode;
6875 HARD_REG_SET regs_live;
6876 {
6877 enum attr_fp_mode fp_mode = mode;
6878 rtx addr_reg = get_free_reg (regs_live);
6879
6880 if (fp_mode == (enum attr_fp_mode) NORMAL_MODE (FP_MODE))
6881 emit_insn (gen_fpu_switch1 (addr_reg));
6882 else
6883 emit_insn (gen_fpu_switch0 (addr_reg));
6884 }
6885
6886 /* Is the given character a logical line separator for the assembler? */
6887 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
6888 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
6889 #endif
6890
6891 int
sh_insn_length_adjustment(insn)6892 sh_insn_length_adjustment (insn)
6893 rtx insn;
6894 {
6895 /* Instructions with unfilled delay slots take up an extra two bytes for
6896 the nop in the delay slot. */
6897 if (((GET_CODE (insn) == INSN
6898 && GET_CODE (PATTERN (insn)) != USE
6899 && GET_CODE (PATTERN (insn)) != CLOBBER)
6900 || GET_CODE (insn) == CALL_INSN
6901 || (GET_CODE (insn) == JUMP_INSN
6902 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
6903 && GET_CODE (PATTERN (insn)) != ADDR_VEC))
6904 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn)))) != SEQUENCE
6905 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
6906 return 2;
6907
6908 /* sh-dsp parallel processing insn take four bytes instead of two. */
6909
6910 if (GET_CODE (insn) == INSN)
6911 {
6912 int sum = 0;
6913 rtx body = PATTERN (insn);
6914 const char *template;
6915 char c;
6916 int maybe_label = 1;
6917
6918 if (GET_CODE (body) == ASM_INPUT)
6919 template = XSTR (body, 0);
6920 else if (asm_noperands (body) >= 0)
6921 template
6922 = decode_asm_operands (body, NULL, NULL, NULL, NULL);
6923 else
6924 return 0;
6925 do
6926 {
6927 int ppi_adjust = 0;
6928
6929 do
6930 c = *template++;
6931 while (c == ' ' || c == '\t');
6932 /* all sh-dsp parallel-processing insns start with p.
6933 The only non-ppi sh insn starting with p is pref.
6934 The only ppi starting with pr is prnd. */
6935 if ((c == 'p' || c == 'P') && strncasecmp ("re", template, 2))
6936 ppi_adjust = 2;
6937 /* The repeat pseudo-insn expands two three insns, a total of
6938 six bytes in size. */
6939 else if ((c == 'r' || c == 'R')
6940 && ! strncasecmp ("epeat", template, 5))
6941 ppi_adjust = 4;
6942 while (c && c != '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c))
6943 {
6944 /* If this is a label, it is obviously not a ppi insn. */
6945 if (c == ':' && maybe_label)
6946 {
6947 ppi_adjust = 0;
6948 break;
6949 }
6950 else if (c == '\'' || c == '"')
6951 maybe_label = 0;
6952 c = *template++;
6953 }
6954 sum += ppi_adjust;
6955 maybe_label = c != ':';
6956 }
6957 while (c);
6958 return sum;
6959 }
6960 return 0;
6961 }
6962
6963 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
6964 isn't protected by a PIC unspec. */
6965 int
nonpic_symbol_mentioned_p(x)6966 nonpic_symbol_mentioned_p (x)
6967 rtx x;
6968 {
6969 register const char *fmt;
6970 register int i;
6971
6972 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
6973 || GET_CODE (x) == PC)
6974 return 1;
6975
6976 /* We don't want to look into the possible MEM location of a
6977 CONST_DOUBLE, since we're not going to use it, in general. */
6978 if (GET_CODE (x) == CONST_DOUBLE)
6979 return 0;
6980
6981 if (GET_CODE (x) == UNSPEC
6982 && (XINT (x, 1) == UNSPEC_PIC
6983 || XINT (x, 1) == UNSPEC_GOT
6984 || XINT (x, 1) == UNSPEC_GOTOFF
6985 || XINT (x, 1) == UNSPEC_GOTPLT
6986 || XINT (x, 1) == UNSPEC_PLT))
6987 return 0;
6988
6989 fmt = GET_RTX_FORMAT (GET_CODE (x));
6990 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6991 {
6992 if (fmt[i] == 'E')
6993 {
6994 register int j;
6995
6996 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6997 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
6998 return 1;
6999 }
7000 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
7001 return 1;
7002 }
7003
7004 return 0;
7005 }
7006
7007 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
7008 @GOTOFF in `reg'. */
7009 rtx
legitimize_pic_address(orig,mode,reg)7010 legitimize_pic_address (orig, mode, reg)
7011 rtx orig;
7012 enum machine_mode mode ATTRIBUTE_UNUSED;
7013 rtx reg;
7014 {
7015 if (GET_CODE (orig) == LABEL_REF
7016 || (GET_CODE (orig) == SYMBOL_REF
7017 && (CONSTANT_POOL_ADDRESS_P (orig)
7018 /* SYMBOL_REF_FLAG is set on static symbols. */
7019 || SYMBOL_REF_FLAG (orig))))
7020 {
7021 if (reg == 0)
7022 reg = gen_reg_rtx (Pmode);
7023
7024 emit_insn (gen_symGOTOFF2reg (reg, orig));
7025 return reg;
7026 }
7027 else if (GET_CODE (orig) == SYMBOL_REF)
7028 {
7029 if (reg == 0)
7030 reg = gen_reg_rtx (Pmode);
7031
7032 emit_insn (gen_symGOT2reg (reg, orig));
7033 return reg;
7034 }
7035 return orig;
7036 }
7037
7038 /* Mark the use of a constant in the literal table. If the constant
7039 has multiple labels, make it unique. */
7040 static rtx
mark_constant_pool_use(x)7041 mark_constant_pool_use (x)
7042 rtx x;
7043 {
7044 rtx insn, lab, pattern;
7045
7046 if (x == NULL)
7047 return x;
7048
7049 switch (GET_CODE (x))
7050 {
7051 case LABEL_REF:
7052 x = XEXP (x, 0);
7053 case CODE_LABEL:
7054 break;
7055 default:
7056 return x;
7057 }
7058
7059 /* Get the first label in the list of labels for the same constant
7060 and delete another labels in the list. */
7061 lab = x;
7062 for (insn = PREV_INSN (x); insn; insn = PREV_INSN (insn))
7063 {
7064 if (GET_CODE (insn) != CODE_LABEL
7065 || LABEL_REFS (insn) != NEXT_INSN (insn))
7066 break;
7067 lab = insn;
7068 }
7069
7070 for (insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
7071 INSN_DELETED_P (insn) = 1;
7072
7073 /* Mark constants in a window. */
7074 for (insn = NEXT_INSN (x); insn; insn = NEXT_INSN (insn))
7075 {
7076 if (GET_CODE (insn) != INSN)
7077 continue;
7078
7079 pattern = PATTERN (insn);
7080 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
7081 continue;
7082
7083 switch (XINT (pattern, 1))
7084 {
7085 case UNSPECV_CONST2:
7086 case UNSPECV_CONST4:
7087 case UNSPECV_CONST8:
7088 XVECEXP (pattern, 0, 1) = const1_rtx;
7089 break;
7090 case UNSPECV_WINDOW_END:
7091 if (XVECEXP (pattern, 0, 0) == x)
7092 return lab;
7093 break;
7094 case UNSPECV_CONST_END:
7095 return lab;
7096 default:
7097 break;
7098 }
7099 }
7100
7101 return lab;
7102 }
7103
7104 /* Return true if it's possible to redirect BRANCH1 to the destination
7105 of an unconditional jump BRANCH2. We only want to do this if the
7106 resulting branch will have a short displacement. */
7107 int
sh_can_redirect_branch(branch1,branch2)7108 sh_can_redirect_branch (branch1, branch2)
7109 rtx branch1;
7110 rtx branch2;
7111 {
7112 if (flag_expensive_optimizations && simplejump_p (branch2))
7113 {
7114 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
7115 rtx insn;
7116 int distance;
7117
7118 for (distance = 0, insn = NEXT_INSN (branch1);
7119 insn && distance < 256;
7120 insn = PREV_INSN (insn))
7121 {
7122 if (insn == dest)
7123 return 1;
7124 else
7125 distance += get_attr_length (insn);
7126 }
7127 for (distance = 0, insn = NEXT_INSN (branch1);
7128 insn && distance < 256;
7129 insn = NEXT_INSN (insn))
7130 {
7131 if (insn == dest)
7132 return 1;
7133 else
7134 distance += get_attr_length (insn);
7135 }
7136 }
7137 return 0;
7138 }
7139
7140 /* Return nonzero if register old_reg can be renamed to register new_reg. */
7141 int
sh_hard_regno_rename_ok(old_reg,new_reg)7142 sh_hard_regno_rename_ok (old_reg, new_reg)
7143 unsigned int old_reg ATTRIBUTE_UNUSED;
7144 unsigned int new_reg;
7145 {
7146
7147 /* Interrupt functions can only use registers that have already been
7148 saved by the prologue, even if they would normally be
7149 call-clobbered. */
7150
7151 if (sh_cfun_interrupt_handler_p () && !regs_ever_live[new_reg])
7152 return 0;
7153
7154 return 1;
7155 }
7156
7157 /* Function to update the integer COST
7158 based on the relationship between INSN that is dependent on
7159 DEP_INSN through the dependence LINK. The default is to make no
7160 adjustment to COST. This can be used for example to specify to
7161 the scheduler that an output- or anti-dependence does not incur
7162 the same cost as a data-dependence. The return value should be
7163 the new value for COST. */
7164 static int
sh_adjust_cost(insn,link,dep_insn,cost)7165 sh_adjust_cost (insn, link, dep_insn, cost)
7166 rtx insn;
7167 rtx link ATTRIBUTE_UNUSED;
7168 rtx dep_insn;
7169 int cost;
7170 {
7171 rtx reg, use_pat;
7172
7173 if (TARGET_SHMEDIA)
7174 {
7175 /* On SHmedia, if the dependence is an anti-dependence or
7176 output-dependence, there is no cost. */
7177 if (REG_NOTE_KIND (link) != 0)
7178 cost = 0;
7179
7180 if (get_attr_is_mac_media (insn)
7181 && get_attr_is_mac_media (dep_insn))
7182 cost = 1;
7183 }
7184 else if (REG_NOTE_KIND (link) == 0)
7185 {
7186 enum attr_type dep_type, type;
7187
7188 if (recog_memoized (insn) < 0
7189 || recog_memoized (dep_insn) < 0)
7190 return cost;
7191
7192 dep_type = get_attr_type (dep_insn);
7193 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
7194 cost--;
7195 if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
7196 && (type = get_attr_type (insn)) != TYPE_CALL
7197 && type != TYPE_SFUNC)
7198 cost--;
7199
7200 /* The only input for a call that is timing-critical is the
7201 function's address. */
7202 if (GET_CODE(insn) == CALL_INSN)
7203 {
7204 rtx call = PATTERN (insn);
7205
7206 if (GET_CODE (call) == PARALLEL)
7207 call = XVECEXP (call, 0 ,0);
7208 if (GET_CODE (call) == SET)
7209 call = SET_SRC (call);
7210 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM
7211 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn))
7212 cost = 0;
7213 }
7214 /* Likewise, the most timing critical input for an sfuncs call
7215 is the function address. However, sfuncs typically start
7216 using their arguments pretty quickly.
7217 Assume a four cycle delay before they are needed. */
7218 /* All sfunc calls are parallels with at least four components.
7219 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
7220 else if (GET_CODE (PATTERN (insn)) == PARALLEL
7221 && XVECLEN (PATTERN (insn), 0) >= 4
7222 && (reg = sfunc_uses_reg (insn)))
7223 {
7224 if (! reg_set_p (reg, dep_insn))
7225 cost -= 4;
7226 }
7227 /* When the preceding instruction loads the shift amount of
7228 the following SHAD/SHLD, the latency of the load is increased
7229 by 1 cycle. */
7230 else if (TARGET_SH4
7231 && get_attr_type (insn) == TYPE_DYN_SHIFT
7232 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
7233 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn)),
7234 XEXP (SET_SRC (single_set(insn)),
7235 1)))
7236 cost++;
7237 /* When an LS group instruction with a latency of less than
7238 3 cycles is followed by a double-precision floating-point
7239 instruction, FIPR, or FTRV, the latency of the first
7240 instruction is increased to 3 cycles. */
7241 else if (cost < 3
7242 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
7243 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
7244 cost = 3;
7245 /* The lsw register of a double-precision computation is ready one
7246 cycle earlier. */
7247 else if (reload_completed
7248 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
7249 && (use_pat = single_set (insn))
7250 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
7251 SET_SRC (use_pat)))
7252 cost -= 1;
7253
7254 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
7255 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
7256 cost -= 1;
7257 }
7258 /* An anti-dependence penalty of two applies if the first insn is a double
7259 precision fadd / fsub / fmul. */
7260 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI
7261 && recog_memoized (dep_insn) >= 0
7262 && get_attr_type (dep_insn) == TYPE_DFP_ARITH
7263 /* A lot of alleged anti-flow dependences are fake,
7264 so check this one is real. */
7265 && flow_dependent_p (dep_insn, insn))
7266 cost = 2;
7267
7268
7269 return cost;
7270 }
7271
7272 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
7273 if DEP_INSN is anti-flow dependent on INSN. */
7274 static int
flow_dependent_p(insn,dep_insn)7275 flow_dependent_p (insn, dep_insn)
7276 rtx insn, dep_insn;
7277 {
7278 rtx tmp = PATTERN (insn);
7279
7280 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
7281 return tmp == NULL_RTX;
7282 }
7283
7284 /* A helper function for flow_dependent_p called through note_stores. */
7285 static void
flow_dependent_p_1(x,pat,data)7286 flow_dependent_p_1 (x, pat, data)
7287 rtx x;
7288 rtx pat ATTRIBUTE_UNUSED;
7289 void *data;
7290 {
7291 rtx * pinsn = (rtx *) data;
7292
7293 if (*pinsn && reg_referenced_p (x, *pinsn))
7294 *pinsn = NULL_RTX;
7295 }
7296
7297 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
7298 'special function' patterns (type sfunc) that clobber pr, but that
7299 do not look like function calls to leaf_function_p. Hence we must
7300 do this extra check. */
7301 int
sh_pr_n_sets()7302 sh_pr_n_sets ()
7303 {
7304 return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
7305 }
7306
7307 /* This Function returns nonzero if the DFA based scheduler interface
7308 is to be used. At present this is supported for the SH4 only. */
7309 static int
sh_use_dfa_interface()7310 sh_use_dfa_interface()
7311 {
7312 if (TARGET_HARD_SH4)
7313 return 1;
7314 else
7315 return 0;
7316 }
7317
7318 /* This function returns "2" to indicate dual issue for the SH4
7319 processor. To be used by the DFA pipeline description. */
7320 static int
sh_issue_rate()7321 sh_issue_rate()
7322 {
7323 if (TARGET_SUPERSCALAR)
7324 return 2;
7325 else
7326 return 1;
7327 }
7328
7329 /* SHmedia requires registers for branches, so we can't generate new
7330 branches past reload. */
7331 static bool
sh_cannot_modify_jumps_p()7332 sh_cannot_modify_jumps_p ()
7333 {
7334 return (TARGET_SHMEDIA && (reload_in_progress || reload_completed));
7335 }
7336
7337 static bool
sh_ms_bitfield_layout_p(record_type)7338 sh_ms_bitfield_layout_p (record_type)
7339 tree record_type ATTRIBUTE_UNUSED;
7340 {
7341 return TARGET_SH5;
7342 }
7343
7344 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
7345 may access it using GOTOFF instead of GOT. */
7346
7347 static void
sh_encode_section_info(decl,first)7348 sh_encode_section_info (decl, first)
7349 tree decl;
7350 int first;
7351 {
7352 rtx rtl, symbol;
7353
7354 if (DECL_P (decl))
7355 rtl = DECL_RTL (decl);
7356 else
7357 rtl = TREE_CST_RTL (decl);
7358 if (GET_CODE (rtl) != MEM)
7359 return;
7360 symbol = XEXP (rtl, 0);
7361 if (GET_CODE (symbol) != SYMBOL_REF)
7362 return;
7363
7364 if (flag_pic)
7365 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
7366
7367 if (TARGET_SH5 && first && TREE_CODE (decl) != FUNCTION_DECL)
7368 XEXP (rtl, 0) = gen_datalabel_ref (symbol);
7369 }
7370
7371 /* Undo the effects of the above. */
7372
7373 static const char *
sh_strip_name_encoding(str)7374 sh_strip_name_encoding (str)
7375 const char *str;
7376 {
7377 STRIP_DATALABEL_ENCODING (str, str);
7378 str += *str == '*';
7379 return str;
7380 }
7381
7382
7383 /*
7384 On the SH1..SH4, the trampoline looks like
7385 2 0002 D202 mov.l l2,r2
7386 1 0000 D301 mov.l l1,r3
7387 3 0004 422B jmp @r2
7388 4 0006 0009 nop
7389 5 0008 00000000 l1: .long area
7390 6 000c 00000000 l2: .long function
7391
7392 SH5 (compact) uses r1 instead of r3 for the static chain. */
7393
7394
7395 /* Emit RTL insns to initialize the variable parts of a trampoline.
7396 FNADDR is an RTX for the address of the function's pure code.
7397 CXT is an RTX for the static chain value for the function. */
7398
7399 void
sh_initialize_trampoline(tramp,fnaddr,cxt)7400 sh_initialize_trampoline (tramp, fnaddr, cxt)
7401 rtx tramp, fnaddr, cxt;
7402 {
7403 if (TARGET_SHMEDIA64)
7404 {
7405 rtx tramp_templ;
7406 int fixed_len;
7407
7408 rtx movi1 = GEN_INT (0xcc000010);
7409 rtx shori1 = GEN_INT (0xc8000010);
7410 rtx src, dst;
7411
7412 /* The following trampoline works within a +- 128 KB range for cxt:
7413 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
7414 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
7415 gettr tr1,r1; blink tr0,r63 */
7416 /* Address rounding makes it hard to compute the exact bounds of the
7417 offset for this trampoline, but we have a rather generous offset
7418 range, so frame_offset should do fine as an upper bound. */
7419 if (cxt == virtual_stack_vars_rtx && frame_offset < 0x20000)
7420 {
7421 /* ??? could optimize this trampoline initialization
7422 by writing DImode words with two insns each. */
7423 rtx mask = force_reg (DImode, GEN_INT (0x3fffc00));
7424 rtx insn = gen_rtx_MINUS (DImode, cxt, tramp);
7425 insn = gen_rtx_ASHIFT (DImode, insn, GEN_INT (10-2));
7426 insn = gen_rtx_AND (DImode, insn, mask);
7427 /* Or in ptb/u .,tr1 pattern */
7428 insn = gen_rtx_IOR (DImode, insn, gen_int_mode (0xec000010, SImode));
7429 insn = force_operand (insn, NULL_RTX);
7430 insn = gen_lowpart (SImode, insn);
7431 emit_move_insn (gen_rtx_MEM (SImode, tramp), insn);
7432 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (38));
7433 insn = gen_rtx_AND (DImode, insn, mask);
7434 insn = force_operand (gen_rtx_IOR (DImode, movi1, insn), NULL_RTX);
7435 insn = gen_lowpart (SImode, insn);
7436 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)), insn);
7437 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (22));
7438 insn = gen_rtx_AND (DImode, insn, mask);
7439 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7440 insn = gen_lowpart (SImode, insn);
7441 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)), insn);
7442 insn = gen_rtx_LSHIFTRT (DImode, fnaddr, GEN_INT (6));
7443 insn = gen_rtx_AND (DImode, insn, mask);
7444 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7445 insn = gen_lowpart (SImode, insn);
7446 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7447 insn);
7448 insn = gen_rtx_ASHIFT (DImode, fnaddr, GEN_INT (10));
7449 insn = gen_rtx_AND (DImode, insn, mask);
7450 insn = force_operand (gen_rtx_IOR (DImode, shori1, insn), NULL_RTX);
7451 insn = gen_lowpart (SImode, insn);
7452 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 16)),
7453 insn);
7454 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 20)),
7455 GEN_INT (0x6bf10600));
7456 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 24)),
7457 GEN_INT (0x4415fc10));
7458 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 28)),
7459 GEN_INT (0x4401fff0));
7460 emit_insn (gen_ic_invalidate_line (tramp));
7461 return;
7462 }
7463 tramp_templ = gen_rtx_SYMBOL_REF (Pmode,"__GCC_nested_trampoline");
7464 fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode);
7465
7466 tramp_templ = gen_datalabel_ref (tramp_templ);
7467 dst = gen_rtx_MEM (BLKmode, tramp);
7468 src = gen_rtx_MEM (BLKmode, tramp_templ);
7469 set_mem_align (dst, 256);
7470 set_mem_align (src, 64);
7471 emit_block_move (dst, src, GEN_INT (fixed_len), BLOCK_OP_NORMAL);
7472
7473 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant (tramp, fixed_len)),
7474 fnaddr);
7475 emit_move_insn (gen_rtx_MEM (Pmode,
7476 plus_constant (tramp,
7477 fixed_len
7478 + GET_MODE_SIZE (Pmode))),
7479 cxt);
7480 emit_insn (gen_ic_invalidate_line (tramp));
7481 return;
7482 }
7483 else if (TARGET_SHMEDIA)
7484 {
7485 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
7486 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
7487 rtx quad0 = gen_reg_rtx (DImode), cxtload = gen_reg_rtx (DImode);
7488 rtx quad1 = gen_reg_rtx (DImode), quad2 = gen_reg_rtx (DImode);
7489 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
7490 rotated 10 right, and higer 16 bit of every 32 selected. */
7491 rtx movishori
7492 = force_reg (V2HImode, (simplify_gen_subreg
7493 (V2HImode, GEN_INT (0x4330432), SImode, 0)));
7494 rtx ptabs = force_reg (DImode, GEN_INT (0x6bf10600));
7495 rtx blink = force_reg (DImode, GEN_INT (0x4401fff0));
7496
7497 tramp = force_reg (Pmode, tramp);
7498 fnaddr = force_reg (SImode, fnaddr);
7499 cxt = force_reg (SImode, cxt);
7500 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, quad0, 0),
7501 gen_rtx_SUBREG (V2HImode, fnaddr, 0),
7502 movishori));
7503 emit_insn (gen_rotrdi3_mextr (quad0, quad0,
7504 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
7505 emit_insn (gen_ashldi3_media (quad0, quad0, GEN_INT (2)));
7506 emit_move_insn (gen_rtx_MEM (DImode, tramp), quad0);
7507 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode, cxtload, 0),
7508 gen_rtx_SUBREG (V2HImode, cxt, 0),
7509 movishori));
7510 emit_insn (gen_rotrdi3_mextr (cxtload, cxtload,
7511 GEN_INT (TARGET_LITTLE_ENDIAN ? 24 : 56)));
7512 emit_insn (gen_ashldi3_media (cxtload, cxtload, GEN_INT (2)));
7513 if (TARGET_LITTLE_ENDIAN)
7514 {
7515 emit_insn (gen_mshflo_l_di (quad1, ptabs, cxtload));
7516 emit_insn (gen_mextr4 (quad2, cxtload, blink));
7517 }
7518 else
7519 {
7520 emit_insn (gen_mextr4 (quad1, cxtload, ptabs));
7521 emit_insn (gen_mshflo_l_di (quad2, blink, cxtload));
7522 }
7523 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 8)), quad1);
7524 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), quad2);
7525 emit_insn (gen_ic_invalidate_line (tramp));
7526 return;
7527 }
7528 else if (TARGET_SHCOMPACT)
7529 {
7530 emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
7531 return;
7532 }
7533 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7534 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
7535 SImode));
7536 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7537 gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
7538 SImode));
7539 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7540 cxt);
7541 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7542 fnaddr);
7543 if (TARGET_HARVARD)
7544 {
7545 if (TARGET_USERMODE)
7546 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__ic_invalidate"),
7547 0, VOIDmode, 1, tramp, SImode);
7548 else
7549 emit_insn (gen_ic_invalidate_line (tramp));
7550 }
7551 }
7552
7553
7554 /* Machine specific built-in functions. */
7555
7556 struct builtin_description
7557 {
7558 const enum insn_code icode;
7559 const char *const name;
7560 int signature;
7561 };
7562
7563 /* describe number and signedness of arguments; arg[0] == result
7564 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
7565 static const char signature_args[][4] =
7566 {
7567 #define SH_BLTIN_V2SI2 0
7568 { 4, 4 },
7569 #define SH_BLTIN_V4HI2 1
7570 { 4, 4 },
7571 #define SH_BLTIN_V2SI3 2
7572 { 4, 4, 4 },
7573 #define SH_BLTIN_V4HI3 3
7574 { 4, 4, 4 },
7575 #define SH_BLTIN_V8QI3 4
7576 { 4, 4, 4 },
7577 #define SH_BLTIN_MAC_HISI 5
7578 { 1, 4, 4, 1 },
7579 #define SH_BLTIN_SH_HI 6
7580 { 4, 4, 1 },
7581 #define SH_BLTIN_SH_SI 7
7582 { 4, 4, 1 },
7583 #define SH_BLTIN_V4HI2V2SI 8
7584 { 4, 4, 4 },
7585 #define SH_BLTIN_V4HI2V8QI 9
7586 { 4, 4, 4 },
7587 #define SH_BLTIN_SISF 10
7588 { 4, 2 },
7589 #define SH_BLTIN_LDUA_L 11
7590 { 2, 8 },
7591 #define SH_BLTIN_LDUA_Q 12
7592 { 1, 8 },
7593 #define SH_BLTIN_STUA_L 13
7594 { 0, 8, 2 },
7595 #define SH_BLTIN_STUA_Q 14
7596 { 0, 8, 1 },
7597 #define SH_BLTIN_UDI 15
7598 { 0, 8, 1 },
7599 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
7600 #define SH_BLTIN_2 16
7601 #define SH_BLTIN_SU 16
7602 { 1, 2 },
7603 #define SH_BLTIN_3 17
7604 #define SH_BLTIN_SUS 17
7605 { 2, 2, 1 },
7606 #define SH_BLTIN_PSSV 18
7607 { 0, 8, 2, 2 },
7608 #define SH_BLTIN_XXUU 19
7609 #define SH_BLTIN_UUUU 19
7610 { 1, 1, 1, 1 },
7611 #define SH_BLTIN_PV 20
7612 { 0, 8 },
7613 };
7614 /* mcmv: operands considered unsigned. */
7615 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
7616 /* mperm: control value considered unsigned int. */
7617 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
7618 /* mshards_q: returns signed short. */
7619 /* nsb: takes long long arg, returns unsigned char. */
7620 static const struct builtin_description bdesc[] =
7621 {
7622 { CODE_FOR_absv2si2, "__builtin_absv2si2", SH_BLTIN_V2SI2 },
7623 { CODE_FOR_absv4hi2, "__builtin_absv4hi2", SH_BLTIN_V4HI2 },
7624 { CODE_FOR_addv2si3, "__builtin_addv2si3", SH_BLTIN_V2SI3 },
7625 { CODE_FOR_addv4hi3, "__builtin_addv4hi3", SH_BLTIN_V4HI3 },
7626 { CODE_FOR_ssaddv2si3,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3 },
7627 { CODE_FOR_usaddv8qi3,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3 },
7628 { CODE_FOR_ssaddv4hi3,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3 },
7629 #if 0
7630 { CODE_FOR_alloco32, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
7631 { CODE_FOR_alloco64, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV },
7632 #endif
7633 { CODE_FOR_negcmpeqv8qi,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3 },
7634 { CODE_FOR_negcmpeqv2si,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3 },
7635 { CODE_FOR_negcmpeqv4hi,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3 },
7636 { CODE_FOR_negcmpgtuv8qi,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3 },
7637 { CODE_FOR_negcmpgtv2si,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3 },
7638 { CODE_FOR_negcmpgtv4hi,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3 },
7639 { CODE_FOR_mcmv, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU },
7640 { CODE_FOR_mcnvs_lw, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3 },
7641 { CODE_FOR_mcnvs_wb, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI },
7642 { CODE_FOR_mcnvs_wub, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI },
7643 { CODE_FOR_mextr1, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI },
7644 { CODE_FOR_mextr2, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI },
7645 { CODE_FOR_mextr3, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI },
7646 { CODE_FOR_mextr4, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI },
7647 { CODE_FOR_mextr5, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI },
7648 { CODE_FOR_mextr6, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI },
7649 { CODE_FOR_mextr7, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI },
7650 { CODE_FOR_mmacfx_wl, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI },
7651 { CODE_FOR_mmacnfx_wl,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI },
7652 { CODE_FOR_mulv2si3, "__builtin_mulv2si3", SH_BLTIN_V2SI3, },
7653 { CODE_FOR_mulv4hi3, "__builtin_mulv4hi3", SH_BLTIN_V4HI3 },
7654 { CODE_FOR_mmulfx_l, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3 },
7655 { CODE_FOR_mmulfx_w, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3 },
7656 { CODE_FOR_mmulfxrp_w,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3 },
7657 { CODE_FOR_mmulhi_wl, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI },
7658 { CODE_FOR_mmullo_wl, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI },
7659 { CODE_FOR_mmulsum_wq,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU },
7660 { CODE_FOR_mperm_w, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI },
7661 { CODE_FOR_msad_ubq, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU },
7662 { CODE_FOR_mshalds_l, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI },
7663 { CODE_FOR_mshalds_w, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI },
7664 { CODE_FOR_ashrv2si3, "__builtin_ashrv2si3", SH_BLTIN_SH_SI },
7665 { CODE_FOR_ashrv4hi3, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI },
7666 { CODE_FOR_mshards_q, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS },
7667 { CODE_FOR_mshfhi_b, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3 },
7668 { CODE_FOR_mshfhi_l, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3 },
7669 { CODE_FOR_mshfhi_w, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3 },
7670 { CODE_FOR_mshflo_b, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3 },
7671 { CODE_FOR_mshflo_l, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3 },
7672 { CODE_FOR_mshflo_w, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3 },
7673 { CODE_FOR_ashlv2si3, "__builtin_ashlv2si3", SH_BLTIN_SH_SI },
7674 { CODE_FOR_ashlv4hi3, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI },
7675 { CODE_FOR_lshrv2si3, "__builtin_lshrv2si3", SH_BLTIN_SH_SI },
7676 { CODE_FOR_lshrv4hi3, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI },
7677 { CODE_FOR_subv2si3, "__builtin_subv2si3", SH_BLTIN_V2SI3 },
7678 { CODE_FOR_subv4hi3, "__builtin_subv4hi3", SH_BLTIN_V4HI3 },
7679 { CODE_FOR_sssubv2si3,"__builtin_sssubv2si3", SH_BLTIN_V2SI3 },
7680 { CODE_FOR_ussubv8qi3,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3 },
7681 { CODE_FOR_sssubv4hi3,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3 },
7682 { CODE_FOR_fcosa_s, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF },
7683 { CODE_FOR_fsina_s, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF },
7684 { CODE_FOR_fipr, "__builtin_sh_media_FIPR_S", SH_BLTIN_3 },
7685 { CODE_FOR_ftrv, "__builtin_sh_media_FTRV_S", SH_BLTIN_3 },
7686 { CODE_FOR_fsrra_s, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2 },
7687 #if 0
7688 { CODE_FOR_ldhi_l, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
7689 { CODE_FOR_ldhi_q, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
7690 { CODE_FOR_ldlo_l, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
7691 { CODE_FOR_ldlo_q, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
7692 { CODE_FOR_sthi_l, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
7693 { CODE_FOR_sthi_q, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
7694 { CODE_FOR_stlo_l, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
7695 { CODE_FOR_stlo_q, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
7696 { CODE_FOR_ldhi_l64, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L },
7697 { CODE_FOR_ldhi_q64, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q },
7698 { CODE_FOR_ldlo_l64, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L },
7699 { CODE_FOR_ldlo_q64, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q },
7700 { CODE_FOR_sthi_l64, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L },
7701 { CODE_FOR_sthi_q64, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q },
7702 { CODE_FOR_stlo_l64, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L },
7703 { CODE_FOR_stlo_q64, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q },
7704 #endif
7705 { CODE_FOR_nsb, "__builtin_sh_media_NSB", SH_BLTIN_SU },
7706 { CODE_FOR_byterev, "__builtin_sh_media_BYTEREV", SH_BLTIN_2 },
7707 #if 0
7708 { CODE_FOR_prefetch32,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV },
7709 { CODE_FOR_prefetch64,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV }
7710 #endif
7711 };
7712
7713 static void
sh_media_init_builtins()7714 sh_media_init_builtins ()
7715 {
7716 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
7717 const struct builtin_description *d;
7718
7719 memset (shared, 0, sizeof shared);
7720 for (d = bdesc; d - bdesc < (int) (sizeof bdesc / sizeof bdesc[0]); d++)
7721 {
7722 tree type, arg_type;
7723 int signature = d->signature;
7724 int i;
7725
7726 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
7727 type = shared[signature];
7728 else
7729 {
7730 int has_result = signature_args[signature][0] != 0;
7731
7732 if (signature_args[signature][1] == 8
7733 && (insn_data[d->icode].operand[has_result].mode != Pmode))
7734 continue;
7735 if (! TARGET_FPU_ANY
7736 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
7737 continue;
7738 type = void_list_node;
7739 for (i = 3; ; i--)
7740 {
7741 int arg = signature_args[signature][i];
7742 int opno = i - 1 + has_result;
7743
7744 if (arg == 8)
7745 arg_type = ptr_type_node;
7746 else if (arg)
7747 arg_type = ((*lang_hooks.types.type_for_mode)
7748 (insn_data[d->icode].operand[opno].mode,
7749 (arg & 1)));
7750 else if (i)
7751 continue;
7752 else
7753 arg_type = void_type_node;
7754 if (i == 0)
7755 break;
7756 type = tree_cons (NULL_TREE, arg_type, type);
7757 }
7758 type = build_function_type (arg_type, type);
7759 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
7760 shared[signature] = type;
7761 }
7762 builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
7763 NULL, NULL_TREE);
7764 }
7765 }
7766
7767 static void
sh_init_builtins()7768 sh_init_builtins ()
7769 {
7770 if (TARGET_SHMEDIA)
7771 sh_media_init_builtins ();
7772 }
7773
7774 /* Expand an expression EXP that calls a built-in function,
7775 with result going to TARGET if that's convenient
7776 (and in mode MODE if that's convenient).
7777 SUBTARGET may be used as the target for computing one of EXP's operands.
7778 IGNORE is nonzero if the value is to be ignored. */
7779
7780 static rtx
sh_expand_builtin(exp,target,subtarget,mode,ignore)7781 sh_expand_builtin (exp, target, subtarget, mode, ignore)
7782 tree exp;
7783 rtx target;
7784 rtx subtarget ATTRIBUTE_UNUSED;
7785 enum machine_mode mode ATTRIBUTE_UNUSED;
7786 int ignore;
7787 {
7788 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7789 tree arglist = TREE_OPERAND (exp, 1);
7790 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7791 const struct builtin_description *d = &bdesc[fcode];
7792 enum insn_code icode = d->icode;
7793 int signature = d->signature;
7794 enum machine_mode tmode = VOIDmode;
7795 int nop = 0, i;
7796 rtx op[4];
7797 rtx pat;
7798
7799 if (signature_args[signature][0])
7800 {
7801 if (ignore)
7802 return 0;
7803
7804 tmode = insn_data[icode].operand[0].mode;
7805 if (! target
7806 || GET_MODE (target) != tmode
7807 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7808 target = gen_reg_rtx (tmode);
7809 op[nop++] = target;
7810 }
7811 else
7812 target = 0;
7813
7814 for (i = 1; i <= 3; i++, nop++)
7815 {
7816 tree arg;
7817 enum machine_mode opmode, argmode;
7818
7819 if (! signature_args[signature][i])
7820 break;
7821 arg = TREE_VALUE (arglist);
7822 if (arg == error_mark_node)
7823 return const0_rtx;
7824 arglist = TREE_CHAIN (arglist);
7825 opmode = insn_data[icode].operand[nop].mode;
7826 argmode = TYPE_MODE (TREE_TYPE (arg));
7827 if (argmode != opmode)
7828 arg = build1 (NOP_EXPR,
7829 (*lang_hooks.types.type_for_mode) (opmode, 0), arg);
7830 op[nop] = expand_expr (arg, NULL_RTX, opmode, 0);
7831 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
7832 op[nop] = copy_to_mode_reg (opmode, op[nop]);
7833 }
7834
7835 switch (nop)
7836 {
7837 case 1:
7838 pat = (*insn_data[d->icode].genfun) (op[0]);
7839 break;
7840 case 2:
7841 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
7842 break;
7843 case 3:
7844 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
7845 break;
7846 case 4:
7847 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
7848 break;
7849 default:
7850 abort ();
7851 }
7852 if (! pat)
7853 return 0;
7854 emit_insn (pat);
7855 return target;
7856 }
7857
7858 void
sh_expand_unop_v2sf(code,op0,op1)7859 sh_expand_unop_v2sf (code, op0, op1)
7860 enum rtx_code code;
7861 rtx op0, op1;
7862 {
7863 rtx sel0 = const0_rtx;
7864 rtx sel1 = const1_rtx;
7865 rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx)) = gen_unary_sf_op;
7866 rtx op = gen_rtx_fmt_e (code, SFmode, op1);
7867
7868 emit_insn ((*fn) (op0, op1, op, sel0, sel0));
7869 emit_insn ((*fn) (op0, op1, op, sel1, sel1));
7870 }
7871
7872 void
sh_expand_binop_v2sf(code,op0,op1,op2)7873 sh_expand_binop_v2sf (code, op0, op1, op2)
7874 enum rtx_code code;
7875 rtx op0, op1, op2;
7876 {
7877 rtx sel0 = const0_rtx;
7878 rtx sel1 = const1_rtx;
7879 rtx (*fn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx, rtx)) = gen_binary_sf_op;
7880 rtx op = gen_rtx_fmt_ee (code, SFmode, op1, op2);
7881
7882 emit_insn ((*fn) (op0, op1, op2, op, sel0, sel0, sel0));
7883 emit_insn ((*fn) (op0, op1, op2, op, sel1, sel1, sel1));
7884 }
7885
7886 /* Return the class of registers for which a mode change from FROM to TO
7887 is invalid. */
7888 bool
sh_cannot_change_mode_class(from,to,class)7889 sh_cannot_change_mode_class (from, to, class)
7890 enum machine_mode from, to;
7891 enum reg_class class;
7892 {
7893 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7894 {
7895 if (TARGET_LITTLE_ENDIAN)
7896 {
7897 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
7898 return reg_classes_intersect_p (DF_REGS, class);
7899 }
7900 else
7901 {
7902 if (GET_MODE_SIZE (from) < 8)
7903 return reg_classes_intersect_p (DF_HI_REGS, class);
7904 }
7905 }
7906 return 0;
7907 }
7908
7909
7910 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
7911 that label is used. */
7912
7913 void
sh_mark_label(address,nuses)7914 sh_mark_label (address, nuses)
7915 rtx address;
7916 int nuses;
7917 {
7918 if (GOTOFF_P (address))
7919 {
7920 /* Extract the label or symbol. */
7921 address = XEXP (address, 0);
7922 if (GET_CODE (address) == PLUS)
7923 address = XEXP (address, 0);
7924 address = XVECEXP (address, 0, 0);
7925 }
7926 if (GET_CODE (address) == LABEL_REF
7927 && GET_CODE (XEXP (address, 0)) == CODE_LABEL)
7928 LABEL_NUSES (XEXP (address, 0)) += nuses;
7929 }
7930
7931 /* Compute extra cost of moving data between one register class
7932 and another. */
7933
7934 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
7935 uses this information. Hence, the general register <-> floating point
7936 register information here is not used for SFmode. */
7937
7938 int
sh_register_move_cost(mode,srcclass,dstclass)7939 sh_register_move_cost (mode, srcclass, dstclass)
7940 enum machine_mode mode;
7941 enum reg_class srcclass, dstclass;
7942 {
7943 if (dstclass == T_REGS || dstclass == PR_REGS)
7944 return 10;
7945
7946 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
7947 return 4;
7948
7949 if (mode == SImode && ! TARGET_SHMEDIA && TARGET_FMOVD
7950 && REGCLASS_HAS_FP_REG (srcclass)
7951 && REGCLASS_HAS_FP_REG (dstclass))
7952 return 4;
7953
7954 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
7955 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
7956
7957 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
7958 || (dstclass== MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
7959 return 9;
7960
7961 if ((REGCLASS_HAS_FP_REG (dstclass)
7962 && REGCLASS_HAS_GENERAL_REG (srcclass))
7963 || (REGCLASS_HAS_GENERAL_REG (dstclass)
7964 && REGCLASS_HAS_FP_REG (srcclass)))
7965 return ((TARGET_SHMEDIA ? 4 : TARGET_FMOVD ? 8 : 12)
7966 * ((GET_MODE_SIZE (mode) + 7) / 8U));
7967
7968 if ((dstclass == FPUL_REGS
7969 && REGCLASS_HAS_GENERAL_REG (srcclass))
7970 || (srcclass == FPUL_REGS
7971 && REGCLASS_HAS_GENERAL_REG (dstclass)))
7972 return 5;
7973
7974 if ((dstclass == FPUL_REGS
7975 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
7976 || (srcclass == FPUL_REGS
7977 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
7978 return 7;
7979
7980 if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
7981 || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
7982 return 20;
7983
7984 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
7985 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
7986 return 4;
7987
7988 if (TARGET_SHMEDIA
7989 || (TARGET_FMOVD
7990 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
7991 && ! REGCLASS_HAS_GENERAL_REG (dstclass)))
7992 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
7993
7994 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
7995 }
7996
7997 /* Like register_operand, but take into account that SHMEDIA can use
7998 the constant zero like a general register. */
7999 int
sh_register_operand(op,mode)8000 sh_register_operand (op, mode)
8001 rtx op;
8002 enum machine_mode mode;
8003 {
8004 if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
8005 return 1;
8006 return register_operand (op, mode);
8007 }
8008
8009 int
cmpsi_operand(rtx op,enum machine_mode mode)8010 cmpsi_operand (rtx op, enum machine_mode mode)
8011 {
8012 if (GET_CODE (op) == REG && REGNO (op) == T_REG
8013 && GET_MODE (op) == SImode)
8014 return 1;
8015 return arith_operand (op, mode);
8016 }
8017
8018 rtx
sh_get_pr_initial_val(void)8019 sh_get_pr_initial_val (void)
8020 {
8021 return
8022 get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
8023 }
8024
8025 /* INSN is an sfunc; return the rtx that describes the address used. */
8026 static rtx
extract_sfunc_addr(rtx insn)8027 extract_sfunc_addr (rtx insn)
8028 {
8029 rtx pattern, part = NULL_RTX;
8030 int len, i;
8031
8032 pattern = PATTERN (insn);
8033 len = XVECLEN (pattern, 0);
8034 for (i = 0; i < len; i++)
8035 {
8036 part = XVECEXP (pattern, 0, i);
8037 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
8038 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
8039 return XEXP (part, 0);
8040 }
8041 if (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE)
8042 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
8043 abort ();
8044 }
8045
8046 /* Verify that the register in use_sfunc_addr still agrees with the address
8047 used in the sfunc. This prevents fill_slots_from_thread from changing
8048 use_sfunc_addr.
8049 INSN is the use_sfunc_addr instruction, and REG is the register it
8050 guards. */
8051 int
check_use_sfunc_addr(rtx insn,rtx reg)8052 check_use_sfunc_addr (rtx insn, rtx reg)
8053 {
8054 /* Search for the sfunc. It should really come right after INSN. */
8055 while ((insn = NEXT_INSN (insn)))
8056 {
8057 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN)
8058 break;
8059 if (! INSN_P (insn))
8060 continue;
8061
8062 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8063 insn = XVECEXP (PATTERN (insn), 0, 0);
8064 if (GET_CODE (PATTERN (insn)) != PARALLEL
8065 || get_attr_type (insn) != TYPE_SFUNC)
8066 continue;
8067 return rtx_equal_p (extract_sfunc_addr (insn), reg);
8068 }
8069 abort ();
8070 }
8071
8072 int
sh_expand_t_scc(enum rtx_code code,rtx target)8073 sh_expand_t_scc (enum rtx_code code, rtx target)
8074 {
8075 rtx result = target;
8076 HOST_WIDE_INT val;
8077
8078 if (GET_CODE (sh_compare_op0) != REG || REGNO (sh_compare_op0) != T_REG
8079 || GET_CODE (sh_compare_op1) != CONST_INT)
8080 return 0;
8081 if (GET_CODE (result) != REG)
8082 result = gen_reg_rtx (SImode);
8083 val = INTVAL (sh_compare_op1);
8084 if ((code == EQ && val == 1) || (code == NE && val == 0))
8085 emit_insn (gen_movt (result));
8086 else if ((code == EQ && val == 0) || (code == NE && val == 1))
8087 {
8088 emit_insn (gen_rtx_CLOBBER (VOIDmode, result));
8089 emit_insn (gen_subc (result, result, result));
8090 emit_insn (gen_addsi3 (result, result, GEN_INT (1)));
8091 }
8092 else if (code == EQ || code == NE)
8093 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
8094 else
8095 return 0;
8096 if (result != target)
8097 emit_move_insn (target, result);
8098 return 1;
8099 }
8100
8101 #include "gt-sh.h"
8102
8103 void
sh_override_options(void)8104 sh_override_options (void)
8105 {
8106 int regno;
8107
8108 #if defined(OPENBSD_NATIVE) || defined(OPENBSD_CROSS)
8109 /* disable stack protection for now */
8110 flag_propolice_protection = 0;
8111
8112 /* -fregmove is known to produce bad code on SuperH */
8113 flag_regmove = 0;
8114 #endif
8115
8116 sh_cpu = CPU_SH1;
8117 assembler_dialect = 0;
8118 if (TARGET_SH2)
8119 sh_cpu = CPU_SH2;
8120 if (TARGET_SH3)
8121 sh_cpu = CPU_SH3;
8122 if (TARGET_SH3E)
8123 sh_cpu = CPU_SH3E;
8124 if (TARGET_SH4)
8125 {
8126 assembler_dialect = 1;
8127 sh_cpu = CPU_SH4;
8128 }
8129 if (TARGET_SH5)
8130 {
8131 sh_cpu = CPU_SH5;
8132 target_flags |= DALIGN_BIT;
8133 if (TARGET_FPU_ANY
8134 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN))
8135 target_flags |= FMOVD_BIT;
8136 if (TARGET_SHMEDIA)
8137 {
8138 /* There are no delay slots on SHmedia. */
8139 flag_delayed_branch = 0;
8140 /* Relaxation isn't yet supported for SHmedia */
8141 target_flags &= ~RELAX_BIT;
8142 }
8143 if (profile_flag || profile_arc_flag)
8144 {
8145 warning ("Profiling is not supported on this target.");
8146 profile_flag = profile_arc_flag = 0;
8147 }
8148 }
8149 else
8150 {
8151 /* Only the sh64-elf assembler fully supports .quad properly. */
8152 targetm.asm_out.aligned_op.di = NULL;
8153 targetm.asm_out.unaligned_op.di = NULL;
8154 }
8155 if (TARGET_FMOVD)
8156 reg_class_from_letter['e'] = NO_REGS;
8157
8158 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8159 if (! VALID_REGISTER_P (regno))
8160 sh_register_names[regno][0] = '0'; \
8161
8162 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
8163 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
8164 sh_additional_register_names[regno][0] = '0'; \
8165
8166 if (flag_omit_frame_pointer < 0)
8167 {
8168 /* The debugging information is sufficient,
8169 but gdb doesn't implement this yet */
8170 if (0)
8171 flag_omit_frame_pointer
8172 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG
8173 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG);
8174 else
8175 flag_omit_frame_pointer = 0;
8176 }
8177
8178 if (flag_pic && ! TARGET_PREFERGOT)
8179 flag_no_function_cse = 1;
8180
8181 /* Never run scheduling before reload, since that can
8182 break global alloc, and generates slower code anyway due
8183 to the pressure on R0. */
8184 flag_schedule_insns = 0;
8185
8186 if (align_loops == 0)
8187 align_loops = 1 << (TARGET_SH5 ? 3 : 2);
8188 #if defined(OPENBSD_NATIVE) || defined(OPENBSD_CROSS)
8189 /* Do not align jump targets to cache line boundaries at -O2 */
8190 if (align_jumps == 0)
8191 align_jumps = 2;
8192 #else
8193 if (align_jumps == 0)
8194 align_jumps = 1 << CACHE_LOG;
8195 #endif
8196 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2))
8197 align_jumps = TARGET_SHMEDIA ? 4 : 2;
8198
8199 /* Allocation boundary (in *bytes*) for the code of a function.
8200 SH1: 32 bit alignment is faster, because instructions are always
8201 fetched as a pair from a longword boundary.
8202 SH2 .. SH5 : align to cache line start. */
8203 if (align_functions == 0)
8204 align_functions
8205 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG);
8206 /* The linker relaxation code breaks when a function contains
8207 alignments that are larger than that at the start of a
8208 compilation unit. */
8209 if (TARGET_RELAX)
8210 {
8211 int min_align
8212 = align_loops > align_jumps ? align_loops : align_jumps;
8213
8214 /* Also take possible .long constants / mova tables int account. */
8215 if (min_align < 4)
8216 min_align = 4;
8217 if (align_functions < min_align)
8218 align_functions = min_align;
8219 }
8220 }
8221