1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/slab.h> /* fault-inject.h is not standalone! */ 7 8 #include <linux/fault-inject.h> 9 #include <linux/sched/mm.h> 10 11 #include <drm/drm_cache.h> 12 13 #include "gem/i915_gem_internal.h" 14 #include "gem/i915_gem_lmem.h" 15 #include "i915_reg.h" 16 #include "i915_trace.h" 17 #include "i915_utils.h" 18 #include "intel_gt.h" 19 #include "intel_gt_mcr.h" 20 #include "intel_gt_print.h" 21 #include "intel_gt_regs.h" 22 #include "intel_gtt.h" 23 24 bool i915_ggtt_require_binder(struct drm_i915_private *i915) 25 { 26 /* Wa_13010847436 & Wa_14019519902 */ 27 return !i915_direct_stolen_access(i915) && 28 MEDIA_VER_FULL(i915) == IP_VER(13, 0); 29 } 30 31 static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915) 32 { 33 return IS_BROXTON(i915) && i915_vtd_active(i915); 34 } 35 36 bool intel_vm_no_concurrent_access_wa(struct drm_i915_private *i915) 37 { 38 return IS_CHERRYVIEW(i915) || intel_ggtt_update_needs_vtd_wa(i915); 39 } 40 41 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz) 42 { 43 struct drm_i915_gem_object *obj; 44 45 /* 46 * To avoid severe over-allocation when dealing with min_page_size 47 * restrictions, we override that behaviour here by allowing an object 48 * size and page layout which can be smaller. In practice this should be 49 * totally fine, since GTT paging structures are not typically inserted 50 * into the GTT. 51 * 52 * Note that we also hit this path for the scratch page, and for this 53 * case it might need to be 64K, but that should work fine here since we 54 * used the passed in size for the page size, which should ensure it 55 * also has the same alignment. 56 */ 57 obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 58 vm->lmem_pt_obj_flags); 59 /* 60 * Ensure all paging structures for this vm share the same dma-resv 61 * object underneath, with the idea that one object_lock() will lock 62 * them all at once. 63 */ 64 if (!IS_ERR(obj)) { 65 obj->base.resv = i915_vm_resv_get(vm); 66 obj->shares_resv_from = vm; 67 } 68 69 return obj; 70 } 71 72 struct drm_i915_gem_object *alloc_pt_dma(struct i915_address_space *vm, int sz) 73 { 74 struct drm_i915_gem_object *obj; 75 76 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1))) 77 i915_gem_shrink_all(vm->i915); 78 79 obj = i915_gem_object_create_internal(vm->i915, sz); 80 /* 81 * Ensure all paging structures for this vm share the same dma-resv 82 * object underneath, with the idea that one object_lock() will lock 83 * them all at once. 84 */ 85 if (!IS_ERR(obj)) { 86 obj->base.resv = i915_vm_resv_get(vm); 87 obj->shares_resv_from = vm; 88 } 89 90 return obj; 91 } 92 93 int map_pt_dma(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 94 { 95 enum i915_map_type type; 96 void *vaddr; 97 98 type = intel_gt_coherent_map_type(vm->gt, obj, true); 99 vaddr = i915_gem_object_pin_map_unlocked(obj, type); 100 if (IS_ERR(vaddr)) 101 return PTR_ERR(vaddr); 102 103 i915_gem_object_make_unshrinkable(obj); 104 return 0; 105 } 106 107 int map_pt_dma_locked(struct i915_address_space *vm, struct drm_i915_gem_object *obj) 108 { 109 enum i915_map_type type; 110 void *vaddr; 111 112 type = intel_gt_coherent_map_type(vm->gt, obj, true); 113 vaddr = i915_gem_object_pin_map(obj, type); 114 if (IS_ERR(vaddr)) 115 return PTR_ERR(vaddr); 116 117 i915_gem_object_make_unshrinkable(obj); 118 return 0; 119 } 120 121 static void clear_vm_list(struct list_head *list) 122 { 123 struct i915_vma *vma, *vn; 124 125 list_for_each_entry_safe(vma, vn, list, vm_link) { 126 struct drm_i915_gem_object *obj = vma->obj; 127 128 if (!i915_gem_object_get_rcu(obj)) { 129 /* 130 * Object is dying, but has not yet cleared its 131 * vma list. 132 * Unbind the dying vma to ensure our list 133 * is completely drained. We leave the destruction to 134 * the object destructor to avoid the vma 135 * disappearing under it. 136 */ 137 atomic_and(~I915_VMA_PIN_MASK, &vma->flags); 138 WARN_ON(__i915_vma_unbind(vma)); 139 140 /* Remove from the unbound list */ 141 list_del_init(&vma->vm_link); 142 143 /* 144 * Delay the vm and vm mutex freeing until the 145 * object is done with destruction. 146 */ 147 i915_vm_resv_get(vma->vm); 148 vma->vm_ddestroy = true; 149 } else { 150 i915_vma_destroy_locked(vma); 151 i915_gem_object_put(obj); 152 } 153 154 } 155 } 156 157 static void __i915_vm_close(struct i915_address_space *vm) 158 { 159 mutex_lock(&vm->mutex); 160 161 clear_vm_list(&vm->bound_list); 162 clear_vm_list(&vm->unbound_list); 163 164 /* Check for must-fix unanticipated side-effects */ 165 GEM_BUG_ON(!list_empty(&vm->bound_list)); 166 GEM_BUG_ON(!list_empty(&vm->unbound_list)); 167 168 mutex_unlock(&vm->mutex); 169 } 170 171 /* lock the vm into the current ww, if we lock one, we lock all */ 172 int i915_vm_lock_objects(struct i915_address_space *vm, 173 struct i915_gem_ww_ctx *ww) 174 { 175 if (vm->scratch[0]->base.resv == &vm->_resv) { 176 return i915_gem_object_lock(vm->scratch[0], ww); 177 } else { 178 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); 179 180 /* We borrowed the scratch page from ggtt, take the top level object */ 181 return i915_gem_object_lock(ppgtt->pd->pt.base, ww); 182 } 183 } 184 185 void i915_address_space_fini(struct i915_address_space *vm) 186 { 187 drm_mm_takedown(&vm->mm); 188 } 189 190 /** 191 * i915_vm_resv_release - Final struct i915_address_space destructor 192 * @kref: Pointer to the &i915_address_space.resv_ref member. 193 * 194 * This function is called when the last lock sharer no longer shares the 195 * &i915_address_space._resv lock, and also if we raced when 196 * destroying a vma by the vma destruction 197 */ 198 void i915_vm_resv_release(struct kref *kref) 199 { 200 struct i915_address_space *vm = 201 container_of(kref, typeof(*vm), resv_ref); 202 203 dma_resv_fini(&vm->_resv); 204 mutex_destroy(&vm->mutex); 205 206 kfree(vm); 207 } 208 209 static void __i915_vm_release(struct work_struct *work) 210 { 211 struct i915_address_space *vm = 212 container_of(work, struct i915_address_space, release_work); 213 214 __i915_vm_close(vm); 215 216 /* Synchronize async unbinds. */ 217 i915_vma_resource_bind_dep_sync_all(vm); 218 219 vm->cleanup(vm); 220 i915_address_space_fini(vm); 221 222 i915_vm_resv_put(vm); 223 } 224 225 void i915_vm_release(struct kref *kref) 226 { 227 struct i915_address_space *vm = 228 container_of(kref, struct i915_address_space, ref); 229 230 GEM_BUG_ON(i915_is_ggtt(vm)); 231 trace_i915_ppgtt_release(vm); 232 233 queue_work(vm->i915->wq, &vm->release_work); 234 } 235 236 void i915_address_space_init(struct i915_address_space *vm, int subclass) 237 { 238 kref_init(&vm->ref); 239 240 /* 241 * Special case for GGTT that has already done an early 242 * kref_init here. 243 */ 244 if (!kref_read(&vm->resv_ref)) 245 kref_init(&vm->resv_ref); 246 247 vm->pending_unbind = RB_ROOT_CACHED; 248 INIT_WORK(&vm->release_work, __i915_vm_release); 249 250 /* 251 * The vm->mutex must be reclaim safe (for use in the shrinker). 252 * Do a dummy acquire now under fs_reclaim so that any allocation 253 * attempt holding the lock is immediately reported by lockdep. 254 */ 255 rw_init(&vm->mutex, "vmlk"); 256 lockdep_set_subclass(&vm->mutex, subclass); 257 258 if (!intel_vm_no_concurrent_access_wa(vm->i915)) { 259 i915_gem_shrinker_taints_mutex(vm->i915, &vm->mutex); 260 } else { 261 /* 262 * CHV + BXT VTD workaround use stop_machine(), 263 * which is allowed to allocate memory. This means &vm->mutex 264 * is the outer lock, and in theory we can allocate memory inside 265 * it through stop_machine(). 266 * 267 * Add the annotation for this, we use trylock in shrinker. 268 */ 269 mutex_acquire(&vm->mutex.dep_map, 0, 0, _THIS_IP_); 270 might_alloc(GFP_KERNEL); 271 mutex_release(&vm->mutex.dep_map, _THIS_IP_); 272 } 273 dma_resv_init(&vm->_resv); 274 275 GEM_BUG_ON(!vm->total); 276 drm_mm_init(&vm->mm, 0, vm->total); 277 278 memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT, 279 ARRAY_SIZE(vm->min_alignment)); 280 281 if (HAS_64K_PAGES(vm->i915)) { 282 vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_64K; 283 vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_64K; 284 } 285 286 vm->mm.head_node.color = I915_COLOR_UNEVICTABLE; 287 288 INIT_LIST_HEAD(&vm->bound_list); 289 INIT_LIST_HEAD(&vm->unbound_list); 290 } 291 292 void *__px_vaddr(struct drm_i915_gem_object *p) 293 { 294 enum i915_map_type type; 295 296 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 297 return page_unpack_bits(p->mm.mapping, &type); 298 } 299 300 dma_addr_t __px_dma(struct drm_i915_gem_object *p) 301 { 302 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 303 return sg_dma_address(p->mm.pages->sgl); 304 } 305 306 struct vm_page *__px_page(struct drm_i915_gem_object *p) 307 { 308 GEM_BUG_ON(!i915_gem_object_has_pages(p)); 309 return sg_page(p->mm.pages->sgl); 310 } 311 312 void 313 fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) 314 { 315 void *vaddr = __px_vaddr(p); 316 317 memset64(vaddr, val, count); 318 drm_clflush_virt_range(vaddr, PAGE_SIZE); 319 } 320 321 static void poison_scratch_page(struct drm_i915_gem_object *scratch) 322 { 323 void *vaddr = __px_vaddr(scratch); 324 u8 val; 325 326 val = 0; 327 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) 328 val = POISON_FREE; 329 330 memset(vaddr, val, scratch->base.size); 331 drm_clflush_virt_range(vaddr, scratch->base.size); 332 } 333 334 int setup_scratch_page(struct i915_address_space *vm) 335 { 336 unsigned long size; 337 338 /* 339 * In order to utilize 64K pages for an object with a size < 2M, we will 340 * need to support a 64K scratch page, given that every 16th entry for a 341 * page-table operating in 64K mode must point to a properly aligned 64K 342 * region, including any PTEs which happen to point to scratch. 343 * 344 * This is only relevant for the 48b PPGTT where we support 345 * huge-gtt-pages, see also i915_vma_insert(). However, as we share the 346 * scratch (read-only) between all vm, we create one 64k scratch page 347 * for all. 348 */ 349 size = I915_GTT_PAGE_SIZE_4K; 350 if (i915_vm_is_4lvl(vm) && 351 HAS_PAGE_SIZES(vm->i915, I915_GTT_PAGE_SIZE_64K) && 352 !HAS_64K_PAGES(vm->i915)) 353 size = I915_GTT_PAGE_SIZE_64K; 354 355 do { 356 struct drm_i915_gem_object *obj; 357 358 obj = vm->alloc_scratch_dma(vm, size); 359 if (IS_ERR(obj)) 360 goto skip; 361 362 if (map_pt_dma(vm, obj)) 363 goto skip_obj; 364 365 /* We need a single contiguous page for our scratch */ 366 if (obj->mm.page_sizes.sg < size) 367 goto skip_obj; 368 369 /* And it needs to be correspondingly aligned */ 370 if (__px_dma(obj) & (size - 1)) 371 goto skip_obj; 372 373 /* 374 * Use a non-zero scratch page for debugging. 375 * 376 * We want a value that should be reasonably obvious 377 * to spot in the error state, while also causing a GPU hang 378 * if executed. We prefer using a clear page in production, so 379 * should it ever be accidentally used, the effect should be 380 * fairly benign. 381 */ 382 poison_scratch_page(obj); 383 384 vm->scratch[0] = obj; 385 vm->scratch_order = get_order(size); 386 return 0; 387 388 skip_obj: 389 i915_gem_object_put(obj); 390 skip: 391 if (size == I915_GTT_PAGE_SIZE_4K) 392 return -ENOMEM; 393 394 size = I915_GTT_PAGE_SIZE_4K; 395 } while (1); 396 } 397 398 void free_scratch(struct i915_address_space *vm) 399 { 400 int i; 401 402 if (!vm->scratch[0]) 403 return; 404 405 for (i = 0; i <= vm->top; i++) 406 i915_gem_object_put(vm->scratch[i]); 407 } 408 409 void gtt_write_workarounds(struct intel_gt *gt) 410 { 411 struct drm_i915_private *i915 = gt->i915; 412 struct intel_uncore *uncore = gt->uncore; 413 414 /* 415 * This function is for gtt related workarounds. This function is 416 * called on driver load and after a GPU reset, so you can place 417 * workarounds here even if they get overwritten by GPU reset. 418 */ 419 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */ 420 if (IS_BROADWELL(i915)) 421 intel_uncore_write(uncore, 422 GEN8_L3_LRA_1_GPGPU, 423 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); 424 else if (IS_CHERRYVIEW(i915)) 425 intel_uncore_write(uncore, 426 GEN8_L3_LRA_1_GPGPU, 427 GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); 428 else if (IS_GEN9_LP(i915)) 429 intel_uncore_write(uncore, 430 GEN8_L3_LRA_1_GPGPU, 431 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); 432 else if (GRAPHICS_VER(i915) >= 9 && GRAPHICS_VER(i915) <= 11) 433 intel_uncore_write(uncore, 434 GEN8_L3_LRA_1_GPGPU, 435 GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); 436 437 /* 438 * To support 64K PTEs we need to first enable the use of the 439 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical 440 * mmio, otherwise the page-walker will simply ignore the IPS bit. This 441 * shouldn't be needed after GEN10. 442 * 443 * 64K pages were first introduced from BDW+, although technically they 444 * only *work* from gen9+. For pre-BDW we instead have the option for 445 * 32K pages, but we don't currently have any support for it in our 446 * driver. 447 */ 448 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_64K) && 449 GRAPHICS_VER(i915) <= 10) 450 intel_uncore_rmw(uncore, 451 GEN8_GAMW_ECO_DEV_RW_IA, 452 0, 453 GAMW_ECO_ENABLE_64K_IPS_FIELD); 454 455 if (IS_GRAPHICS_VER(i915, 8, 11)) { 456 bool can_use_gtt_cache = true; 457 458 /* 459 * According to the BSpec if we use 2M/1G pages then we also 460 * need to disable the GTT cache. At least on BDW we can see 461 * visual corruption when using 2M pages, and not disabling the 462 * GTT cache. 463 */ 464 if (HAS_PAGE_SIZES(i915, I915_GTT_PAGE_SIZE_2M)) 465 can_use_gtt_cache = false; 466 467 /* WaGttCachingOffByDefault */ 468 intel_uncore_write(uncore, 469 HSW_GTT_CACHE_EN, 470 can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); 471 gt_WARN_ON_ONCE(gt, can_use_gtt_cache && 472 intel_uncore_read(uncore, 473 HSW_GTT_CACHE_EN) == 0); 474 } 475 } 476 477 static void xelpmp_setup_private_ppat(struct intel_uncore *uncore) 478 { 479 intel_uncore_write(uncore, XELPMP_PAT_INDEX(0), 480 MTL_PPAT_L4_0_WB); 481 intel_uncore_write(uncore, XELPMP_PAT_INDEX(1), 482 MTL_PPAT_L4_1_WT); 483 intel_uncore_write(uncore, XELPMP_PAT_INDEX(2), 484 MTL_PPAT_L4_3_UC); 485 intel_uncore_write(uncore, XELPMP_PAT_INDEX(3), 486 MTL_PPAT_L4_0_WB | MTL_2_COH_1W); 487 intel_uncore_write(uncore, XELPMP_PAT_INDEX(4), 488 MTL_PPAT_L4_0_WB | MTL_3_COH_2W); 489 490 /* 491 * Remaining PAT entries are left at the hardware-default 492 * fully-cached setting 493 */ 494 } 495 496 static void xelpg_setup_private_ppat(struct intel_gt *gt) 497 { 498 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0), 499 MTL_PPAT_L4_0_WB); 500 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1), 501 MTL_PPAT_L4_1_WT); 502 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2), 503 MTL_PPAT_L4_3_UC); 504 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3), 505 MTL_PPAT_L4_0_WB | MTL_2_COH_1W); 506 intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4), 507 MTL_PPAT_L4_0_WB | MTL_3_COH_2W); 508 509 /* 510 * Remaining PAT entries are left at the hardware-default 511 * fully-cached setting 512 */ 513 } 514 515 static void tgl_setup_private_ppat(struct intel_uncore *uncore) 516 { 517 /* TGL doesn't support LLC or AGE settings */ 518 intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB); 519 intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC); 520 intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT); 521 intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC); 522 intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB); 523 intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB); 524 intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB); 525 intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB); 526 } 527 528 static void xehp_setup_private_ppat(struct intel_gt *gt) 529 { 530 enum forcewake_domains fw; 531 unsigned long flags; 532 533 fw = intel_uncore_forcewake_for_reg(gt->uncore, _MMIO(XEHP_PAT_INDEX(0).reg), 534 FW_REG_WRITE); 535 intel_uncore_forcewake_get(gt->uncore, fw); 536 537 intel_gt_mcr_lock(gt, &flags); 538 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(0), GEN8_PPAT_WB); 539 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(1), GEN8_PPAT_WC); 540 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(2), GEN8_PPAT_WT); 541 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(3), GEN8_PPAT_UC); 542 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(4), GEN8_PPAT_WB); 543 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(5), GEN8_PPAT_WB); 544 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(6), GEN8_PPAT_WB); 545 intel_gt_mcr_multicast_write_fw(gt, XEHP_PAT_INDEX(7), GEN8_PPAT_WB); 546 intel_gt_mcr_unlock(gt, flags); 547 548 intel_uncore_forcewake_put(gt->uncore, fw); 549 } 550 551 static void icl_setup_private_ppat(struct intel_uncore *uncore) 552 { 553 intel_uncore_write(uncore, 554 GEN10_PAT_INDEX(0), 555 GEN8_PPAT_WB | GEN8_PPAT_LLC); 556 intel_uncore_write(uncore, 557 GEN10_PAT_INDEX(1), 558 GEN8_PPAT_WC | GEN8_PPAT_LLCELLC); 559 intel_uncore_write(uncore, 560 GEN10_PAT_INDEX(2), 561 GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 562 intel_uncore_write(uncore, 563 GEN10_PAT_INDEX(3), 564 GEN8_PPAT_UC); 565 intel_uncore_write(uncore, 566 GEN10_PAT_INDEX(4), 567 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)); 568 intel_uncore_write(uncore, 569 GEN10_PAT_INDEX(5), 570 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)); 571 intel_uncore_write(uncore, 572 GEN10_PAT_INDEX(6), 573 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)); 574 intel_uncore_write(uncore, 575 GEN10_PAT_INDEX(7), 576 GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 577 } 578 579 /* 580 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability 581 * bits. When using advanced contexts each context stores its own PAT, but 582 * writing this data shouldn't be harmful even in those cases. 583 */ 584 static void bdw_setup_private_ppat(struct intel_uncore *uncore) 585 { 586 struct drm_i915_private *i915 = uncore->i915; 587 u64 pat; 588 589 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ 590 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ 591 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ 592 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | 593 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | 594 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | 595 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 596 597 /* for scanout with eLLC */ 598 if (GRAPHICS_VER(i915) >= 9) 599 pat |= GEN8_PPAT(2, GEN8_PPAT_WB | GEN8_PPAT_ELLC_OVERRIDE); 600 else 601 pat |= GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC); 602 603 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 604 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 605 } 606 607 static void chv_setup_private_ppat(struct intel_uncore *uncore) 608 { 609 u64 pat; 610 611 /* 612 * Map WB on BDW to snooped on CHV. 613 * 614 * Only the snoop bit has meaning for CHV, the rest is 615 * ignored. 616 * 617 * The hardware will never snoop for certain types of accesses: 618 * - CPU GTT (GMADR->GGTT->no snoop->memory) 619 * - PPGTT page tables 620 * - some other special cycles 621 * 622 * As with BDW, we also need to consider the following for GT accesses: 623 * "For GGTT, there is NO pat_sel[2:0] from the entry, 624 * so RTL will always use the value corresponding to 625 * pat_sel = 000". 626 * Which means we must set the snoop bit in PAT entry 0 627 * in order to keep the global status page working. 628 */ 629 630 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | 631 GEN8_PPAT(1, 0) | 632 GEN8_PPAT(2, 0) | 633 GEN8_PPAT(3, 0) | 634 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 635 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 636 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 637 GEN8_PPAT(7, CHV_PPAT_SNOOP); 638 639 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_LO, lower_32_bits(pat)); 640 intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat)); 641 } 642 643 void setup_private_pat(struct intel_gt *gt) 644 { 645 struct intel_uncore *uncore = gt->uncore; 646 struct drm_i915_private *i915 = gt->i915; 647 648 GEM_BUG_ON(GRAPHICS_VER(i915) < 8); 649 650 if (gt->type == GT_MEDIA) { 651 xelpmp_setup_private_ppat(gt->uncore); 652 return; 653 } 654 655 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 656 xelpg_setup_private_ppat(gt); 657 else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) 658 xehp_setup_private_ppat(gt); 659 else if (GRAPHICS_VER(i915) >= 12) 660 tgl_setup_private_ppat(uncore); 661 else if (GRAPHICS_VER(i915) >= 11) 662 icl_setup_private_ppat(uncore); 663 else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915)) 664 chv_setup_private_ppat(uncore); 665 else 666 bdw_setup_private_ppat(uncore); 667 } 668 669 struct i915_vma * 670 __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size) 671 { 672 struct drm_i915_gem_object *obj; 673 struct i915_vma *vma; 674 675 obj = i915_gem_object_create_internal(vm->i915, PAGE_ALIGN(size)); 676 if (IS_ERR(obj)) 677 return ERR_CAST(obj); 678 679 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC); 680 681 vma = i915_vma_instance(obj, vm, NULL); 682 if (IS_ERR(vma)) { 683 i915_gem_object_put(obj); 684 return vma; 685 } 686 687 return vma; 688 } 689 690 struct i915_vma * 691 __vm_create_scratch_for_read_pinned(struct i915_address_space *vm, unsigned long size) 692 { 693 struct i915_vma *vma; 694 int err; 695 696 vma = __vm_create_scratch_for_read(vm, size); 697 if (IS_ERR(vma)) 698 return vma; 699 700 err = i915_vma_pin(vma, 0, 0, 701 i915_vma_is_ggtt(vma) ? PIN_GLOBAL : PIN_USER); 702 if (err) { 703 i915_vma_put(vma); 704 return ERR_PTR(err); 705 } 706 707 return vma; 708 } 709 710 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 711 #include "selftests/mock_gtt.c" 712 #endif 713