1 /* $NetBSD: radeon_rv730_dpm.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2011 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: radeon_rv730_dpm.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
29
30 #include "radeon.h"
31 #include "rv730d.h"
32 #include "r600_dpm.h"
33 #include "rv770_dpm.h"
34 #include "atom.h"
35
36 #define MC_CG_ARB_FREQ_F0 0x0a
37 #define MC_CG_ARB_FREQ_F1 0x0b
38 #define MC_CG_ARB_FREQ_F2 0x0c
39 #define MC_CG_ARB_FREQ_F3 0x0d
40
41 struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
42 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
43
rv730_populate_sclk_value(struct radeon_device * rdev,u32 engine_clock,RV770_SMC_SCLK_VALUE * sclk)44 int rv730_populate_sclk_value(struct radeon_device *rdev,
45 u32 engine_clock,
46 RV770_SMC_SCLK_VALUE *sclk)
47 {
48 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
49 struct atom_clock_dividers dividers;
50 u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
51 u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
52 u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
53 u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum;
54 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2;
55 u64 tmp;
56 u32 reference_clock = rdev->clock.spll.reference_freq;
57 u32 reference_divider, post_divider;
58 u32 fbdiv;
59 int ret;
60
61 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
62 engine_clock, false, ÷rs);
63 if (ret)
64 return ret;
65
66 reference_divider = 1 + dividers.ref_div;
67
68 if (dividers.enable_post_div)
69 post_divider = ((dividers.post_div >> 4) & 0xf) +
70 (dividers.post_div & 0xf) + 2;
71 else
72 post_divider = 1;
73
74 tmp = (u64) engine_clock * reference_divider * post_divider * 16384;
75 do_div(tmp, reference_clock);
76 fbdiv = (u32) tmp;
77
78 /* set up registers */
79 if (dividers.enable_post_div)
80 spll_func_cntl |= SPLL_DIVEN;
81 else
82 spll_func_cntl &= ~SPLL_DIVEN;
83 spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK);
84 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
85 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf);
86 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf);
87
88 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
89 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
90
91 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
92 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
93 spll_func_cntl_3 |= SPLL_DITHEN;
94
95 if (pi->sclk_ss) {
96 struct radeon_atom_ss ss;
97 u32 vco_freq = engine_clock * post_divider;
98
99 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
100 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
101 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
102 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000);
103
104 cg_spll_spread_spectrum &= ~CLK_S_MASK;
105 cg_spll_spread_spectrum |= CLK_S(clk_s);
106 cg_spll_spread_spectrum |= SSEN;
107
108 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
109 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
110 }
111 }
112
113 sclk->sclk_value = cpu_to_be32(engine_clock);
114 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
115 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
116 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
117 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
118 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
119
120 return 0;
121 }
122
rv730_populate_mclk_value(struct radeon_device * rdev,u32 engine_clock,u32 memory_clock,LPRV7XX_SMC_MCLK_VALUE mclk)123 int rv730_populate_mclk_value(struct radeon_device *rdev,
124 u32 engine_clock, u32 memory_clock,
125 LPRV7XX_SMC_MCLK_VALUE mclk)
126 {
127 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
128 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl;
129 u32 dll_cntl = pi->clk_regs.rv730.dll_cntl;
130 u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
131 u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
132 u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
133 u32 mpll_ss = pi->clk_regs.rv730.mpll_ss;
134 u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2;
135 struct atom_clock_dividers dividers;
136 u32 post_divider, reference_divider;
137 int ret;
138
139 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
140 memory_clock, false, ÷rs);
141 if (ret)
142 return ret;
143
144 reference_divider = dividers.ref_div + 1;
145
146 if (dividers.enable_post_div)
147 post_divider = ((dividers.post_div >> 4) & 0xf) +
148 (dividers.post_div & 0xf) + 2;
149 else
150 post_divider = 1;
151
152 /* setup the registers */
153 if (dividers.enable_post_div)
154 mpll_func_cntl |= MPLL_DIVEN;
155 else
156 mpll_func_cntl &= ~MPLL_DIVEN;
157
158 mpll_func_cntl &= ~(MPLL_REF_DIV_MASK | MPLL_HILEN_MASK | MPLL_LOLEN_MASK);
159 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div);
160 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf);
161 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf);
162
163 mpll_func_cntl_3 &= ~MPLL_FB_DIV_MASK;
164 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div);
165 if (dividers.enable_dithen)
166 mpll_func_cntl_3 |= MPLL_DITHEN;
167 else
168 mpll_func_cntl_3 &= ~MPLL_DITHEN;
169
170 if (pi->mclk_ss) {
171 struct radeon_atom_ss ss;
172 u32 vco_freq = memory_clock * post_divider;
173
174 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
175 ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
176 u32 reference_clock = rdev->clock.mpll.reference_freq;
177 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
178 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000);
179
180 mpll_ss &= ~CLK_S_MASK;
181 mpll_ss |= CLK_S(clk_s);
182 mpll_ss |= SSEN;
183
184 mpll_ss2 &= ~CLK_V_MASK;
185 mpll_ss |= CLK_V(clk_v);
186 }
187 }
188
189
190 mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
191 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
192 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock);
193 mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
194 mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
195 mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
196 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss);
197 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
198
199 return 0;
200 }
201
rv730_read_clock_registers(struct radeon_device * rdev)202 void rv730_read_clock_registers(struct radeon_device *rdev)
203 {
204 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
205
206 pi->clk_regs.rv730.cg_spll_func_cntl =
207 RREG32(CG_SPLL_FUNC_CNTL);
208 pi->clk_regs.rv730.cg_spll_func_cntl_2 =
209 RREG32(CG_SPLL_FUNC_CNTL_2);
210 pi->clk_regs.rv730.cg_spll_func_cntl_3 =
211 RREG32(CG_SPLL_FUNC_CNTL_3);
212 pi->clk_regs.rv730.cg_spll_spread_spectrum =
213 RREG32(CG_SPLL_SPREAD_SPECTRUM);
214 pi->clk_regs.rv730.cg_spll_spread_spectrum_2 =
215 RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
216
217 pi->clk_regs.rv730.mclk_pwrmgt_cntl =
218 RREG32(TCI_MCLK_PWRMGT_CNTL);
219 pi->clk_regs.rv730.dll_cntl =
220 RREG32(TCI_DLL_CNTL);
221 pi->clk_regs.rv730.mpll_func_cntl =
222 RREG32(CG_MPLL_FUNC_CNTL);
223 pi->clk_regs.rv730.mpll_func_cntl2 =
224 RREG32(CG_MPLL_FUNC_CNTL_2);
225 pi->clk_regs.rv730.mpll_func_cntl3 =
226 RREG32(CG_MPLL_FUNC_CNTL_3);
227 pi->clk_regs.rv730.mpll_ss =
228 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);
229 pi->clk_regs.rv730.mpll_ss2 =
230 RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);
231 }
232
rv730_populate_smc_acpi_state(struct radeon_device * rdev,RV770_SMC_STATETABLE * table)233 int rv730_populate_smc_acpi_state(struct radeon_device *rdev,
234 RV770_SMC_STATETABLE *table)
235 {
236 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
237 u32 mpll_func_cntl = 0;
238 u32 mpll_func_cntl_2 = 0 ;
239 u32 mpll_func_cntl_3 = 0;
240 u32 mclk_pwrmgt_cntl;
241 u32 dll_cntl;
242 u32 spll_func_cntl;
243 u32 spll_func_cntl_2;
244 u32 spll_func_cntl_3;
245
246 table->ACPIState = table->initialState;
247 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
248
249 if (pi->acpi_vddc) {
250 rv770_populate_vddc_value(rdev, pi->acpi_vddc,
251 &table->ACPIState.levels[0].vddc);
252 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?
253 pi->acpi_pcie_gen2 : 0;
254 table->ACPIState.levels[0].gen2XSP =
255 pi->acpi_pcie_gen2;
256 } else {
257 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
258 &table->ACPIState.levels[0].vddc);
259 table->ACPIState.levels[0].gen2PCIE = 0;
260 }
261
262 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;
263 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;
264 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;
265
266 mpll_func_cntl |= MPLL_RESET | MPLL_BYPASS_EN;
267 mpll_func_cntl &= ~MPLL_SLEEP;
268
269 mpll_func_cntl_2 &= ~MCLK_MUX_SEL_MASK;
270 mpll_func_cntl_2 |= MCLK_MUX_SEL(1);
271
272 mclk_pwrmgt_cntl = (MRDCKA_RESET |
273 MRDCKB_RESET |
274 MRDCKC_RESET |
275 MRDCKD_RESET |
276 MRDCKE_RESET |
277 MRDCKF_RESET |
278 MRDCKG_RESET |
279 MRDCKH_RESET |
280 MRDCKA_SLEEP |
281 MRDCKB_SLEEP |
282 MRDCKC_SLEEP |
283 MRDCKD_SLEEP |
284 MRDCKE_SLEEP |
285 MRDCKF_SLEEP |
286 MRDCKG_SLEEP |
287 MRDCKH_SLEEP);
288
289 dll_cntl = 0xff000000;
290
291 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;
292 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;
293 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;
294
295 spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN;
296 spll_func_cntl &= ~SPLL_SLEEP;
297
298 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
299 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
300
301 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
302 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2);
303 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3);
304 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
305 table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl);
306
307 table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0;
308
309 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
310 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
311 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
312
313 table->ACPIState.levels[0].sclk.sclk_value = 0;
314
315 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
316
317 table->ACPIState.levels[1] = table->ACPIState.levels[0];
318 table->ACPIState.levels[2] = table->ACPIState.levels[0];
319
320 return 0;
321 }
322
rv730_populate_smc_initial_state(struct radeon_device * rdev,struct radeon_ps * radeon_state,RV770_SMC_STATETABLE * table)323 int rv730_populate_smc_initial_state(struct radeon_device *rdev,
324 struct radeon_ps *radeon_state,
325 RV770_SMC_STATETABLE *table)
326 {
327 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state);
328 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
329 u32 a_t;
330
331 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL =
332 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl);
333 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 =
334 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2);
335 table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 =
336 cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3);
337 table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL =
338 cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl);
339 table->initialState.levels[0].mclk.mclk730.vDLL_CNTL =
340 cpu_to_be32(pi->clk_regs.rv730.dll_cntl);
341 table->initialState.levels[0].mclk.mclk730.vMPLL_SS =
342 cpu_to_be32(pi->clk_regs.rv730.mpll_ss);
343 table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
344 cpu_to_be32(pi->clk_regs.rv730.mpll_ss2);
345
346 table->initialState.levels[0].mclk.mclk730.mclk_value =
347 cpu_to_be32(initial_state->low.mclk);
348
349 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
350 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl);
351 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
352 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2);
353 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
354 cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3);
355 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
356 cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum);
357 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
358 cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2);
359
360 table->initialState.levels[0].sclk.sclk_value =
361 cpu_to_be32(initial_state->low.sclk);
362
363 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
364
365 table->initialState.levels[0].seqValue =
366 rv770_get_seq_value(rdev, &initial_state->low);
367
368 rv770_populate_vddc_value(rdev,
369 initial_state->low.vddc,
370 &table->initialState.levels[0].vddc);
371 rv770_populate_initial_mvdd_value(rdev,
372 &table->initialState.levels[0].mvdd);
373
374 a_t = CG_R(0xffff) | CG_L(0);
375
376 table->initialState.levels[0].aT = cpu_to_be32(a_t);
377
378 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
379
380 if (pi->boot_in_gen2)
381 table->initialState.levels[0].gen2PCIE = 1;
382 else
383 table->initialState.levels[0].gen2PCIE = 0;
384 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
385 table->initialState.levels[0].gen2XSP = 1;
386 else
387 table->initialState.levels[0].gen2XSP = 0;
388
389 table->initialState.levels[1] = table->initialState.levels[0];
390 table->initialState.levels[2] = table->initialState.levels[0];
391
392 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
393
394 return 0;
395 }
396
rv730_program_memory_timing_parameters(struct radeon_device * rdev,struct radeon_ps * radeon_state)397 void rv730_program_memory_timing_parameters(struct radeon_device *rdev,
398 struct radeon_ps *radeon_state)
399 {
400 struct rv7xx_ps *state = rv770_get_ps(radeon_state);
401 u32 arb_refresh_rate = 0;
402 u32 dram_timing = 0;
403 u32 dram_timing2 = 0;
404 u32 old_dram_timing = 0;
405 u32 old_dram_timing2 = 0;
406
407 arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &
408 ~(POWERMODE1_MASK | POWERMODE2_MASK | POWERMODE3_MASK);
409 arb_refresh_rate |=
410 (POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) |
411 POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) |
412 POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk)));
413 WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);
414
415 /* save the boot dram timings */
416 old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
417 old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
418
419 radeon_atom_set_engine_dram_timings(rdev,
420 state->high.sclk,
421 state->high.mclk);
422
423 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
424 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
425
426 WREG32(MC_ARB_DRAM_TIMING_3, dram_timing);
427 WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2);
428
429 radeon_atom_set_engine_dram_timings(rdev,
430 state->medium.sclk,
431 state->medium.mclk);
432
433 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
434 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
435
436 WREG32(MC_ARB_DRAM_TIMING_2, dram_timing);
437 WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2);
438
439 radeon_atom_set_engine_dram_timings(rdev,
440 state->low.sclk,
441 state->low.mclk);
442
443 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
444 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
445
446 WREG32(MC_ARB_DRAM_TIMING_1, dram_timing);
447 WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2);
448
449 /* restore the boot dram timings */
450 WREG32(MC_ARB_DRAM_TIMING, old_dram_timing);
451 WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2);
452
453 }
454
rv730_start_dpm(struct radeon_device * rdev)455 void rv730_start_dpm(struct radeon_device *rdev)
456 {
457 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
458
459 WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
460
461 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
462 }
463
rv730_stop_dpm(struct radeon_device * rdev)464 void rv730_stop_dpm(struct radeon_device *rdev)
465 {
466 PPSMC_Result result;
467
468 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
469
470 if (result != PPSMC_Result_OK)
471 DRM_DEBUG("Could not force DPM to low\n");
472
473 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
474
475 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
476
477 WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
478 }
479
rv730_program_dcodt(struct radeon_device * rdev,bool use_dcodt)480 void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt)
481 {
482 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
483 u32 i = use_dcodt ? 0 : 1;
484 u32 mc4_io_pad_cntl;
485
486 mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
487 mc4_io_pad_cntl &= 0xFFFFFF00;
488 mc4_io_pad_cntl |= pi->odt_value_0[i];
489 WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
490 WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
491
492 mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
493 mc4_io_pad_cntl &= 0xFFFFFF00;
494 mc4_io_pad_cntl |= pi->odt_value_1[i];
495 WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl);
496 WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl);
497 }
498
rv730_get_odt_values(struct radeon_device * rdev)499 void rv730_get_odt_values(struct radeon_device *rdev)
500 {
501 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
502 u32 mc4_io_pad_cntl;
503
504 pi->odt_value_0[0] = (u8)0;
505 pi->odt_value_1[0] = (u8)0x80;
506
507 mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
508 pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff);
509
510 mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
511 pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff);
512 }
513