1 /* $NetBSD: rtsx.c,v 1.7 2023/08/11 07:05:39 mrg Exp $ */
2 /* $OpenBSD: rtsx.c,v 1.10 2014/08/19 17:55:03 phessler Exp $ */
3
4 /*
5 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
6 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 /*
22 * Realtek RTS5209/RTS5227/RTS5229/RTL8402/RTL8411/RTL8411B Card Reader driver.
23 */
24
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: rtsx.c,v 1.7 2023/08/11 07:05:39 mrg Exp $");
27
28 #include <sys/param.h>
29 #include <sys/device.h>
30 #include <sys/kernel.h>
31 #include <sys/systm.h>
32 #include <sys/proc.h>
33 #include <sys/mutex.h>
34
35 #include <dev/ic/rtsxreg.h>
36 #include <dev/ic/rtsxvar.h>
37
38 #include <dev/sdmmc/sdmmcvar.h>
39 #include <dev/sdmmc/sdmmc_ioreg.h>
40
41 /*
42 * We use two DMA buffers, a command buffer and a data buffer.
43 *
44 * The command buffer contains a command queue for the host controller,
45 * which describes SD/MMC commands to run, and other parameters. The chip
46 * runs the command queue when a special bit in the RTSX_HCBAR register is set
47 * and signals completion with the TRANS_OK interrupt.
48 * Each command is encoded as a 4 byte sequence containing command number
49 * (read, write, or check a host controller register), a register address,
50 * and a data bit-mask and value.
51 *
52 * The data buffer is used to transfer data sectors to or from the SD card.
53 * Data transfer is controlled via the RTSX_HDBAR register. Completion is
54 * also signalled by the TRANS_OK interrupt.
55 *
56 * The chip is unable to perform DMA above 4GB.
57 *
58 * SD/MMC commands which do not transfer any data from/to the card only use
59 * the command buffer.
60 */
61
62 #define RTSX_DMA_MAX_SEGSIZE 0x80000
63 #define RTSX_HOSTCMD_MAX 256
64 #define RTSX_HOSTCMD_BUFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX)
65 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS
66
67 #define READ4(sc, reg) \
68 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
69 #define WRITE4(sc, reg, val) \
70 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
71
72 #define RTSX_READ(sc, reg, val) \
73 do { \
74 int err = rtsx_read((sc), (reg), (val)); \
75 if (err) \
76 return err; \
77 } while (/*CONSTCOND*/0)
78
79 #define RTSX_WRITE(sc, reg, val) \
80 do { \
81 int err = rtsx_write((sc), (reg), 0xff, (val)); \
82 if (err) \
83 return err; \
84 } while (/*CONSTCOND*/0)
85
86 #define RTSX_CLR(sc, reg, bits) \
87 do { \
88 int err = rtsx_write((sc), (reg), (bits), 0); \
89 if (err) \
90 return err; \
91 } while (/*CONSTCOND*/0)
92
93 #define RTSX_SET(sc, reg, bits) \
94 do { \
95 int err = rtsx_write((sc), (reg), (bits), 0xff);\
96 if (err) \
97 return err; \
98 } while (/*CONSTCOND*/0)
99
100 #define RTSX_BITOP(sc, reg, mask, bits) \
101 do { \
102 int err = rtsx_write((sc), (reg), (mask), (bits));\
103 if (err) \
104 return err; \
105 } while (/*CONSTCOND*/0)
106
107 static int rtsx_host_reset(sdmmc_chipset_handle_t);
108 static uint32_t rtsx_host_ocr(sdmmc_chipset_handle_t);
109 static int rtsx_host_maxblklen(sdmmc_chipset_handle_t);
110 static int rtsx_card_detect(sdmmc_chipset_handle_t);
111 static int rtsx_write_protect(sdmmc_chipset_handle_t);
112 static int rtsx_bus_power(sdmmc_chipset_handle_t, uint32_t);
113 static int rtsx_bus_clock(sdmmc_chipset_handle_t, int);
114 static int rtsx_bus_width(sdmmc_chipset_handle_t, int);
115 static int rtsx_bus_rod(sdmmc_chipset_handle_t, int);
116 static void rtsx_exec_command(sdmmc_chipset_handle_t,
117 struct sdmmc_command *);
118 static int rtsx_init(struct rtsx_softc *, int);
119 static void rtsx_soft_reset(struct rtsx_softc *);
120 static int rtsx_bus_power_off(struct rtsx_softc *);
121 static int rtsx_bus_power_on(struct rtsx_softc *);
122 static int rtsx_set_bus_width(struct rtsx_softc *, int);
123 static int rtsx_stop_sd_clock(struct rtsx_softc *);
124 static int rtsx_switch_sd_clock(struct rtsx_softc *, uint8_t, int, int);
125 static int rtsx_wait_intr(struct rtsx_softc *, int, int);
126 static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *);
127 static int rtsx_write(struct rtsx_softc *, uint16_t, uint8_t, uint8_t);
128 #ifdef notyet
129 static int rtsx_read_phy(struct rtsx_softc *, uint8_t, uint16_t *);
130 #endif
131 static int rtsx_write_phy(struct rtsx_softc *, uint8_t, uint16_t);
132 static int rtsx_read_cfg(struct rtsx_softc *, uint8_t, uint16_t,
133 uint32_t *);
134 #ifdef notyet
135 static int rtsx_write_cfg(struct rtsx_softc *, uint8_t, uint16_t, uint32_t,
136 uint32_t);
137 #endif
138 static void rtsx_hostcmd(uint32_t *, int *, uint8_t, uint16_t, uint8_t,
139 uint8_t);
140 static int rtsx_hostcmd_send(struct rtsx_softc *, int);
141 static uint8_t rtsx_response_type(uint16_t);
142 static int rtsx_read_ppbuf(struct rtsx_softc *, struct sdmmc_command *,
143 uint32_t *);
144 static int rtsx_write_ppbuf(struct rtsx_softc *, struct sdmmc_command *,
145 uint32_t *);
146 static int rtsx_exec_short_xfer(struct rtsx_softc *,
147 struct sdmmc_command *, uint32_t *, uint8_t);
148 static int rtsx_xfer(struct rtsx_softc *, struct sdmmc_command *,
149 uint32_t *);
150 static void rtsx_card_insert(struct rtsx_softc *);
151 static void rtsx_card_eject(struct rtsx_softc *);
152 static int rtsx_led_enable(struct rtsx_softc *);
153 static int rtsx_led_disable(struct rtsx_softc *);
154 static void rtsx_save_regs(struct rtsx_softc *);
155 static void rtsx_restore_regs(struct rtsx_softc *);
156
157 #ifdef RTSX_DEBUG
158 int rtsxdebug = 0;
159 #define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0)
160 #else
161 #define DPRINTF(n,s) /**/
162 #endif
163
164 #define DEVNAME(sc) SDMMCDEVNAME(sc)
165
166 static struct sdmmc_chip_functions rtsx_chip_functions = {
167 /* host controller reset */
168 .host_reset = rtsx_host_reset,
169
170 /* host controller capabilities */
171 .host_ocr = rtsx_host_ocr,
172 .host_maxblklen = rtsx_host_maxblklen,
173
174 /* card detection */
175 .card_detect = rtsx_card_detect,
176
177 /* write protect */
178 .write_protect = rtsx_write_protect,
179
180 /* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */
181 .bus_power = rtsx_bus_power,
182 .bus_clock = rtsx_bus_clock,
183 .bus_width = rtsx_bus_width,
184 .bus_rod = rtsx_bus_rod,
185
186 /* command execution */
187 .exec_command = rtsx_exec_command,
188
189 /* card interrupt */
190 .card_enable_intr = NULL,
191 .card_intr_ack = NULL,
192 };
193
194 /*
195 * Called by attachment driver.
196 */
197 int
rtsx_attach(struct rtsx_softc * sc,bus_space_tag_t iot,bus_space_handle_t ioh,bus_size_t iosize,bus_dma_tag_t dmat,int flags)198 rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot,
199 bus_space_handle_t ioh, bus_size_t iosize, bus_dma_tag_t dmat, int flags)
200 {
201 struct sdmmcbus_attach_args saa;
202 uint32_t sdio_cfg;
203
204 sc->sc_iot = iot;
205 sc->sc_ioh = ioh;
206 sc->sc_iosize = iosize;
207 sc->sc_dmat = dmat;
208 sc->sc_flags = flags;
209
210 mutex_init(&sc->sc_host_mtx, MUTEX_DEFAULT, IPL_SDMMC);
211 mutex_init(&sc->sc_intr_mtx, MUTEX_DEFAULT, IPL_SDMMC);
212 cv_init(&sc->sc_intr_cv, "rtsxintr");
213
214 if (rtsx_init(sc, 1))
215 goto error;
216
217 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) {
218 if (sdio_cfg & (RTSX_SDIOCFG_SDIO_ONLY|RTSX_SDIOCFG_HAVE_SDIO)){
219 sc->sc_flags |= RTSX_F_SDIO_SUPPORT;
220 }
221 }
222
223 if (bus_dmamap_create(sc->sc_dmat, RTSX_HOSTCMD_BUFSIZE, 1,
224 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW,
225 &sc->sc_dmap_cmd) != 0)
226 goto error;
227
228 /*
229 * Attach the generic SD/MMC bus driver. (The bus driver must
230 * not invoke any chipset functions before it is attached.)
231 */
232 memset(&saa, 0, sizeof(saa));
233 saa.saa_busname = "sdmmc";
234 saa.saa_sct = &rtsx_chip_functions;
235 saa.saa_spi_sct = NULL;
236 saa.saa_sch = sc;
237 saa.saa_dmat = sc->sc_dmat;
238 saa.saa_clkmin = SDMMC_SDCLK_400K;
239 saa.saa_clkmax = 25000;
240 saa.saa_caps = SMC_CAPS_DMA|SMC_CAPS_4BIT_MODE;
241
242 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL, CFARGS_NONE);
243 if (sc->sc_sdmmc == NULL)
244 goto destroy_dmamap_cmd;
245
246 /* Now handle cards discovered during attachment. */
247 if (ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT))
248 rtsx_card_insert(sc);
249
250 return 0;
251
252 destroy_dmamap_cmd:
253 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap_cmd);
254 error:
255 cv_destroy(&sc->sc_intr_cv);
256 mutex_destroy(&sc->sc_intr_mtx);
257 mutex_destroy(&sc->sc_host_mtx);
258 return 1;
259 }
260
261 int
rtsx_detach(struct rtsx_softc * sc,int flags)262 rtsx_detach(struct rtsx_softc *sc, int flags)
263 {
264 int rv;
265
266 if (sc->sc_sdmmc != NULL) {
267 rv = config_detach(sc->sc_sdmmc, flags);
268 if (rv != 0)
269 return rv;
270 sc->sc_sdmmc = NULL;
271 }
272
273 /* disable interrupts */
274 if ((flags & DETACH_FORCE) == 0) {
275 WRITE4(sc, RTSX_BIER, 0);
276 rtsx_soft_reset(sc);
277 }
278
279 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmap_cmd);
280 cv_destroy(&sc->sc_intr_cv);
281 mutex_destroy(&sc->sc_intr_mtx);
282 mutex_destroy(&sc->sc_host_mtx);
283 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_iosize);
284
285 return 0;
286 }
287
288 bool
rtsx_suspend(device_t dev,const pmf_qual_t * qual)289 rtsx_suspend(device_t dev, const pmf_qual_t *qual)
290 {
291 struct rtsx_softc *sc = device_private(dev);
292
293 /* Save the host controller state. */
294 rtsx_save_regs(sc);
295
296 return true;
297 }
298
299 bool
rtsx_resume(device_t dev,const pmf_qual_t * qual)300 rtsx_resume(device_t dev, const pmf_qual_t *qual)
301 {
302 struct rtsx_softc *sc = device_private(dev);
303
304 /* Restore the host controller state. */
305 rtsx_restore_regs(sc);
306
307 if (READ4(sc, RTSX_BIPR) & RTSX_SD_EXIST)
308 rtsx_card_insert(sc);
309 else
310 rtsx_card_eject(sc);
311
312 return true;
313 }
314
315 bool
rtsx_shutdown(device_t dev,int flags)316 rtsx_shutdown(device_t dev, int flags)
317 {
318 struct rtsx_softc *sc = device_private(dev);
319
320 /* XXX chip locks up if we don't disable it before reboot. */
321 (void)rtsx_host_reset(sc);
322
323 return true;
324 }
325
326 static int
rtsx_init(struct rtsx_softc * sc,int attaching)327 rtsx_init(struct rtsx_softc *sc, int attaching)
328 {
329 uint32_t status;
330 uint8_t reg;
331 int error;
332
333 if (attaching) {
334 if (RTSX_IS_RTS5229(sc)) {
335 /* Read IC version from dummy register. */
336 RTSX_READ(sc, RTSX_DUMMY_REG, ®);
337 switch (reg & 0x0f) {
338 case RTSX_IC_VERSION_A:
339 case RTSX_IC_VERSION_B:
340 case RTSX_IC_VERSION_D:
341 break;
342 case RTSX_IC_VERSION_C:
343 sc->sc_flags |= RTSX_F_5229_TYPE_C;
344 break;
345 default:
346 aprint_error_dev(sc->sc_dev,
347 "unknown RTS5229 version 0x%02x\n", reg);
348 return 1;
349 }
350 } else if (RTSX_IS_RTL8411B(sc)) {
351 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, ®);
352 if (reg & RTSX_RTL8411B_QFN48)
353 sc->sc_flags |= RTSX_F_8411B_QFN48;
354 }
355 }
356
357 /* Enable interrupt write-clear (default is read-clear). */
358 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR);
359
360 /* Clear any pending interrupts. */
361 status = READ4(sc, RTSX_BIPR);
362 WRITE4(sc, RTSX_BIPR, status);
363
364 /* Check for cards already inserted at attach time. */
365 if (attaching && (status & RTSX_SD_EXIST))
366 sc->sc_flags |= RTSX_F_CARD_PRESENT;
367
368 /* Enable interrupts. */
369 WRITE4(sc, RTSX_BIER,
370 RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN);
371
372 /* Power on SSC clock. */
373 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN);
374 delay(200);
375
376 /* XXX magic numbers from linux driver */
377 if (RTSX_IS_RTS5209(sc))
378 error = rtsx_write_phy(sc, 0x00, 0xB966);
379 else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc))
380 error = rtsx_write_phy(sc, 0x00, 0xBA42);
381 else
382 error = 0;
383 if (error) {
384 aprint_error_dev(sc->sc_dev, "couldn't write phy register\n");
385 return 1;
386 }
387
388 RTSX_SET(sc, RTSX_CLK_DIV, 0x07);
389
390 /* Disable sleep mode. */
391 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE,
392 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3);
393
394 /* Disable card clock. */
395 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL);
396
397 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE,
398 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG | 0x04);
399 RTSX_WRITE(sc, RTSX_SD30_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_3V3);
400
401 /* Enable SSC clock. */
402 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M);
403 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12);
404
405 RTSX_SET(sc, RTSX_CHANGE_LINK_STATE, RTSX_MAC_PHY_RST_N_DBG);
406 RTSX_SET(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT);
407
408 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80);
409
410 /* Set RC oscillator to 400K. */
411 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M);
412
413 /* Request clock by driving CLKREQ pin to zero. */
414 RTSX_SET(sc, RTSX_PETXCFG, RTSX_PETXCFG_CLKREQ_PIN);
415
416 /* Set up LED GPIO. */
417 if (RTSX_IS_RTS5209(sc)) {
418 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03);
419 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03);
420 } else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) {
421 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON);
422 /* Switch LDO3318 source from DV33 to 3V3. */
423 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33);
424 RTSX_SET(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_3V3);
425 /* Set default OLT blink period. */
426 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_PERIOD);
427 } else if (RTSX_IS_RTL8402(sc)
428 || RTSX_IS_RTL8411(sc)
429 || RTSX_IS_RTL8411B(sc)) {
430 if (RTSX_IS_RTL8411B_QFN48(sc))
431 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5);
432 /* Enable SD interrupt */
433 RTSX_WRITE(sc, RTSX_CARD_PAD_CTL, 0x05);
434 RTSX_BITOP(sc, RTSX_EFUSE_CONTENT, 0xe0, 0x80);
435 if (RTSX_IS_RTL8411B(sc))
436 RTSX_WRITE(sc, RTSX_FUNC_FORCE_CTL, 0x00);
437 }
438
439 return 0;
440 }
441
442 int
rtsx_led_enable(struct rtsx_softc * sc)443 rtsx_led_enable(struct rtsx_softc *sc)
444 {
445
446 if (RTSX_IS_RTS5209(sc)) {
447 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF);
448 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK,
449 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED);
450 } else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) {
451 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON);
452 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK);
453 } else if (RTSX_IS_RTL8402(sc)
454 || RTSX_IS_RTL8411(sc)
455 || RTSX_IS_RTL8411B(sc)) {
456 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01);
457 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK,
458 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED);
459 }
460
461 return 0;
462 }
463
464 int
rtsx_led_disable(struct rtsx_softc * sc)465 rtsx_led_disable(struct rtsx_softc *sc)
466 {
467
468 if (RTSX_IS_RTS5209(sc)) {
469 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN);
470 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF);
471 } else if (RTSX_IS_RTS5227(sc) || RTSX_IS_RTS5229(sc)) {
472 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK);
473 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON);
474 } else if (RTSX_IS_RTL8402(sc)
475 || RTSX_IS_RTL8411(sc)
476 || RTSX_IS_RTL8411B(sc)) {
477 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN);
478 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01);
479 }
480
481 return 0;
482 }
483
484 /*
485 * Reset the host controller. Called during initialization, when
486 * cards are removed, upon resume, and during error recovery.
487 */
488 int
rtsx_host_reset(sdmmc_chipset_handle_t sch)489 rtsx_host_reset(sdmmc_chipset_handle_t sch)
490 {
491 struct rtsx_softc *sc = sch;
492 int error;
493
494 DPRINTF(1,("%s: host reset\n", DEVNAME(sc)));
495
496 mutex_enter(&sc->sc_host_mtx);
497
498 if (ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT))
499 rtsx_soft_reset(sc);
500
501 error = rtsx_init(sc, 0);
502
503 mutex_exit(&sc->sc_host_mtx);
504
505 return error;
506 }
507
508 static uint32_t
rtsx_host_ocr(sdmmc_chipset_handle_t sch)509 rtsx_host_ocr(sdmmc_chipset_handle_t sch)
510 {
511
512 return RTSX_SUPPORT_VOLTAGE;
513 }
514
515 static int
rtsx_host_maxblklen(sdmmc_chipset_handle_t sch)516 rtsx_host_maxblklen(sdmmc_chipset_handle_t sch)
517 {
518
519 return 512;
520 }
521
522 /*
523 * Return non-zero if the card is currently inserted.
524 */
525 static int
rtsx_card_detect(sdmmc_chipset_handle_t sch)526 rtsx_card_detect(sdmmc_chipset_handle_t sch)
527 {
528 struct rtsx_softc *sc = sch;
529
530 return ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT);
531 }
532
533 static int
rtsx_write_protect(sdmmc_chipset_handle_t sch)534 rtsx_write_protect(sdmmc_chipset_handle_t sch)
535 {
536
537 return 0; /* XXX */
538 }
539
540 /*
541 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and
542 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229
543 * it is a mask of *enabled* gates.
544 */
545
546 static int
rtsx_bus_power_off(struct rtsx_softc * sc)547 rtsx_bus_power_off(struct rtsx_softc *sc)
548 {
549 int error;
550 uint8_t disable3;
551
552 error = rtsx_stop_sd_clock(sc);
553 if (error)
554 return error;
555
556 /* Disable SD output. */
557 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_CARD_OUTPUT_EN);
558
559 /* Turn off power. */
560 disable3 = RTSX_PULL_CTL_DISABLE3;
561 if (RTSX_IS_RTS5209(sc))
562 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF);
563 else if (RTSX_IS_RTS5227(sc)
564 || RTSX_IS_RTS5229(sc)
565 || RTSX_IS_RTS525A(sc)) {
566 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1 |
567 RTSX_LDO3318_VCC2);
568 if (RTSX_IS_RTS5229_TYPE_C(sc))
569 disable3 = RTSX_PULL_CTL_DISABLE3_TYPE_C;
570 } else if (RTSX_IS_RTL8402(sc)
571 || RTSX_IS_RTL8411(sc)
572 || RTSX_IS_RTL8411B(sc)) {
573 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
574 RTSX_BPP_POWER_OFF);
575 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
576 RTSX_BPP_LDO_SUSPEND);
577 }
578
579 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF);
580 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA);
581
582 /* Disable pull control. */
583 if (RTSX_IS_RTS5209(sc)
584 || RTSX_IS_RTS5227(sc)
585 || RTSX_IS_RTS5229(sc)
586 || RTSX_IS_RTS525A(sc)) {
587 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12);
588 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12);
589 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, disable3);
590 } else if (RTSX_IS_RTL8402(sc) || RTSX_IS_RTL8411(sc)) {
591 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65);
592 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x65);
593 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95);
594 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09);
595 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05);
596 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04);
597 } else if (RTSX_IS_RTL8411B(sc)) {
598 if (RTSX_IS_RTL8411B_QFN48(sc)) {
599 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55);
600 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5);
601 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15);
602 } else {
603 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65);
604 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55);
605 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9);
606 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59);
607 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55);
608 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15);
609 }
610 }
611
612 return 0;
613 }
614
615 static int
rtsx_bus_power_on(struct rtsx_softc * sc)616 rtsx_bus_power_on(struct rtsx_softc *sc)
617 {
618 uint8_t enable3;
619
620 if (RTSX_IS_RTS525A(sc)) {
621 int err = rtsx_write(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK,
622 RTSX_LDO_VCC_3V3);
623 if (err)
624 return err;
625 }
626
627 /* Select SD card. */
628 RTSX_WRITE(sc, RTSX_CARD_SELECT, RTSX_SD_MOD_SEL);
629 RTSX_WRITE(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_48_SD);
630 RTSX_SET(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN);
631
632 /* Enable pull control. */
633 if (RTSX_IS_RTS5209(sc)
634 || RTSX_IS_RTS5227(sc)
635 || RTSX_IS_RTS5229(sc)
636 || RTSX_IS_RTS525A(sc)) {
637 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12);
638 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12);
639 if (RTSX_IS_RTS5229_TYPE_C(sc))
640 enable3 = RTSX_PULL_CTL_ENABLE3_TYPE_C;
641 else
642 enable3 = RTSX_PULL_CTL_ENABLE3;
643 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, enable3);
644 } else if (RTSX_IS_RTL8402(sc) || RTSX_IS_RTL8411(sc)) {
645 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa);
646 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa);
647 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9);
648 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09);
649 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09);
650 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04);
651 } else if (RTSX_IS_RTL8411B(sc)) {
652 if (RTSX_IS_RTL8411B_QFN48(sc)) {
653 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa);
654 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9);
655 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19);
656 } else {
657 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa);
658 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa);
659 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9);
660 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59);
661 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x59);
662 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15);
663 }
664 }
665
666 /*
667 * To avoid a current peak, enable card power in two phases with a
668 * delay in between.
669 */
670
671 if (RTSX_IS_RTS5209(sc)
672 || RTSX_IS_RTS5227(sc)
673 || RTSX_IS_RTS5229(sc)
674 || RTSX_IS_RTS525A(sc)) {
675 /* Partial power. */
676 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PARTIAL_PWR_ON);
677 if (RTSX_IS_RTS5209(sc))
678 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_SUSPEND);
679 else
680 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1);
681
682 delay(200);
683
684 /* Full power. */
685 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF);
686 if (RTSX_IS_RTS5209(sc))
687 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF);
688 else
689 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC2);
690 } else if (RTSX_IS_RTL8402(sc)
691 || RTSX_IS_RTL8411(sc)
692 || RTSX_IS_RTL8411B(sc)) {
693 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
694 RTSX_BPP_POWER_5_PERCENT_ON);
695 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
696 RTSX_BPP_LDO_SUSPEND);
697 delay(150);
698 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
699 RTSX_BPP_POWER_10_PERCENT_ON);
700 delay(150);
701 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
702 RTSX_BPP_POWER_15_PERCENT_ON);
703 delay(150);
704 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK,
705 RTSX_BPP_POWER_ON);
706 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB,
707 RTSX_BPP_LDO_ON);
708 }
709
710 /* Enable SD card output. */
711 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN);
712
713 return 0;
714 }
715
716 static int
rtsx_set_bus_width(struct rtsx_softc * sc,int width)717 rtsx_set_bus_width(struct rtsx_softc *sc, int width)
718 {
719 uint32_t bus_width;
720
721 DPRINTF(1,("%s: bus width=%d\n", DEVNAME(sc), width));
722
723 switch (width) {
724 case 8:
725 bus_width = RTSX_BUS_WIDTH_8;
726 break;
727 case 4:
728 bus_width = RTSX_BUS_WIDTH_4;
729 break;
730 case 1:
731 bus_width = RTSX_BUS_WIDTH_1;
732 break;
733 default:
734 return EINVAL;
735 }
736
737 if (bus_width == RTSX_BUS_WIDTH_1)
738 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK);
739 else
740 RTSX_SET(sc, RTSX_SD_CFG1, bus_width);
741
742 return 0;
743 }
744
745 static int
rtsx_stop_sd_clock(struct rtsx_softc * sc)746 rtsx_stop_sd_clock(struct rtsx_softc *sc)
747 {
748
749 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL);
750 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP);
751
752 return 0;
753 }
754
755 static int
rtsx_switch_sd_clock(struct rtsx_softc * sc,uint8_t n,int div,int mcu)756 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t n, int div, int mcu)
757 {
758
759 /* Enable SD 2.0 mode. */
760 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK);
761
762 RTSX_SET(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ);
763
764 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE,
765 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1);
766 RTSX_CLR(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_SEL_MASK);
767 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE);
768 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu);
769 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB);
770 RTSX_CLR(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK);
771 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n);
772 RTSX_SET(sc, RTSX_SSC_CTL1, RTSX_RSTB);
773 delay(100);
774
775 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ);
776
777 return 0;
778 }
779
780 /*
781 * Set or change SD bus voltage and enable or disable SD bus power.
782 * Return zero on success.
783 */
784 static int
rtsx_bus_power(sdmmc_chipset_handle_t sch,uint32_t ocr)785 rtsx_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
786 {
787 struct rtsx_softc *sc = sch;
788 int error = 0;
789
790 DPRINTF(1,("%s: voltage change ocr=0x%x\n", DEVNAME(sc), ocr));
791
792 mutex_enter(&sc->sc_host_mtx);
793
794 /*
795 * Disable bus power before voltage change.
796 */
797 error = rtsx_bus_power_off(sc);
798 if (error)
799 goto ret;
800
801 delay(200);
802
803 /* If power is disabled, reset the host and return now. */
804 if (ocr == 0) {
805 mutex_exit(&sc->sc_host_mtx);
806 (void)rtsx_host_reset(sc);
807 return 0;
808 }
809
810 if (!ISSET(ocr, RTSX_SUPPORT_VOLTAGE)) {
811 /* Unsupported voltage level requested. */
812 DPRINTF(1,("%s: unsupported voltage ocr=0x%x\n",
813 DEVNAME(sc), ocr));
814 error = EINVAL;
815 goto ret;
816 }
817
818 error = rtsx_set_bus_width(sc, 1);
819 if (error)
820 goto ret;
821
822 error = rtsx_bus_power_on(sc);
823 ret:
824 mutex_exit(&sc->sc_host_mtx);
825
826 return error;
827 }
828
829 /*
830 * Set or change SDCLK frequency or disable the SD clock.
831 * Return zero on success.
832 */
833 static int
rtsx_bus_clock(sdmmc_chipset_handle_t sch,int freq)834 rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq)
835 {
836 struct rtsx_softc *sc = sch;
837 uint8_t n;
838 int div;
839 int mcu;
840 int error = 0;
841
842 DPRINTF(1,("%s: bus clock change freq=%d\n", DEVNAME(sc), freq));
843
844 mutex_enter(&sc->sc_host_mtx);
845
846 if (freq == SDMMC_SDCLK_OFF) {
847 error = rtsx_stop_sd_clock(sc);
848 goto ret;
849 }
850
851 /*
852 * Configure the clock frequency.
853 */
854 switch (freq) {
855 case SDMMC_SDCLK_400K:
856 n = 80; /* minimum */
857 div = RTSX_CLK_DIV_8;
858 mcu = 7;
859 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128, 0xff);
860 if (error)
861 goto ret;
862 break;
863 case 20000:
864 n = 80;
865 div = RTSX_CLK_DIV_4;
866 mcu = 7;
867 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0);
868 if (error)
869 goto ret;
870 break;
871 case 25000:
872 n = 100;
873 div = RTSX_CLK_DIV_4;
874 mcu = 7;
875 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0);
876 if (error)
877 goto ret;
878 break;
879 case 30000:
880 n = 120;
881 div = RTSX_CLK_DIV_4;
882 mcu = 7;
883 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0);
884 if (error)
885 goto ret;
886 break;
887 case 40000:
888 n = 80;
889 div = RTSX_CLK_DIV_2;
890 mcu = 7;
891 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0);
892 if (error)
893 goto ret;
894 break;
895 case 50000:
896 n = 100;
897 div = RTSX_CLK_DIV_2;
898 mcu = 6;
899 error = rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, 0);
900 if (error)
901 goto ret;
902 break;
903 default:
904 error = EINVAL;
905 goto ret;
906 }
907
908 /*
909 * Enable SD clock.
910 */
911 error = rtsx_switch_sd_clock(sc, n, div, mcu);
912 ret:
913 mutex_exit(&sc->sc_host_mtx);
914
915 return error;
916 }
917
918 static int
rtsx_bus_width(sdmmc_chipset_handle_t sch,int width)919 rtsx_bus_width(sdmmc_chipset_handle_t sch, int width)
920 {
921 struct rtsx_softc *sc = sch;
922
923 return rtsx_set_bus_width(sc, width);
924 }
925
926 static int
rtsx_bus_rod(sdmmc_chipset_handle_t sch,int on)927 rtsx_bus_rod(sdmmc_chipset_handle_t sch, int on)
928 {
929
930 /* Not support */
931 return -1;
932 }
933
934 static int
rtsx_read(struct rtsx_softc * sc,uint16_t addr,uint8_t * val)935 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val)
936 {
937 int tries = 1024;
938 uint32_t reg = 0 /* XXXGCC12 */;
939
940 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY |
941 (uint32_t)((addr & 0x3FFF) << 16));
942
943 while (tries--) {
944 reg = READ4(sc, RTSX_HAIMR);
945 if (!(reg & RTSX_HAIMR_BUSY))
946 break;
947 }
948
949 *val = (reg & 0xff);
950 return (tries == 0) ? ETIMEDOUT : 0;
951 }
952
953 static int
rtsx_write(struct rtsx_softc * sc,uint16_t addr,uint8_t mask,uint8_t val)954 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val)
955 {
956 int tries = 1024;
957 uint32_t reg;
958
959 WRITE4(sc, RTSX_HAIMR,
960 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE |
961 (uint32_t)(((addr & 0x3FFF) << 16) |
962 (mask << 8) | val));
963
964 while (tries--) {
965 reg = READ4(sc, RTSX_HAIMR);
966 if (!(reg & RTSX_HAIMR_BUSY)) {
967 if (val != (reg & 0xff))
968 return EIO;
969 return 0;
970 }
971 }
972 return ETIMEDOUT;
973 }
974
975 #ifdef notyet
976 static int
rtsx_read_phy(struct rtsx_softc * sc,uint8_t addr,uint16_t * val)977 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val)
978 {
979 int timeout = 100000;
980 uint8_t data0;
981 uint8_t data1;
982 uint8_t rwctl;
983
984 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr);
985 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_READ);
986
987 while (timeout--) {
988 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl);
989 if (!(rwctl & RTSX_PHY_BUSY))
990 break;
991 }
992 if (timeout == 0)
993 return ETIMEDOUT;
994
995 RTSX_READ(sc, RTSX_PHY_DATA0, &data0);
996 RTSX_READ(sc, RTSX_PHY_DATA1, &data1);
997 *val = data0 | (data1 << 8);
998
999 return 0;
1000 }
1001 #endif
1002
1003 static int
rtsx_write_phy(struct rtsx_softc * sc,uint8_t addr,uint16_t val)1004 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val)
1005 {
1006 int timeout = 100000;
1007 uint8_t rwctl;
1008
1009 RTSX_WRITE(sc, RTSX_PHY_DATA0, val);
1010 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8);
1011 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr);
1012 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_WRITE);
1013
1014 while (timeout--) {
1015 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl);
1016 if (!(rwctl & RTSX_PHY_BUSY))
1017 break;
1018 }
1019 if (timeout == 0)
1020 return ETIMEDOUT;
1021
1022 return 0;
1023 }
1024
1025 static int
rtsx_read_cfg(struct rtsx_softc * sc,uint8_t func,uint16_t addr,uint32_t * val)1026 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val)
1027 {
1028 int tries = 1024;
1029 uint8_t data0, data1, data2, data3, rwctl;
1030
1031 RTSX_WRITE(sc, RTSX_CFGADDR0, addr);
1032 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8);
1033 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4));
1034
1035 while (tries--) {
1036 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl);
1037 if (!(rwctl & RTSX_CFG_BUSY))
1038 break;
1039 }
1040 if (tries == 0)
1041 return EIO;
1042
1043 RTSX_READ(sc, RTSX_CFGDATA0, &data0);
1044 RTSX_READ(sc, RTSX_CFGDATA1, &data1);
1045 RTSX_READ(sc, RTSX_CFGDATA2, &data2);
1046 RTSX_READ(sc, RTSX_CFGDATA3, &data3);
1047 *val = ((uint32_t)data3 << 24) | (data2 << 16) | (data1 << 8) | data0;
1048
1049 return 0;
1050 }
1051
1052 #ifdef notyet
1053 static int
rtsx_write_cfg(struct rtsx_softc * sc,uint8_t func,uint16_t addr,uint32_t mask,uint32_t val)1054 rtsx_write_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr,
1055 uint32_t mask, uint32_t val)
1056 {
1057 uint32_t writemask = 0;
1058 int i, tries = 1024;
1059 uint8_t rwctl;
1060
1061 for (i = 0; i < 4; i++) {
1062 if (mask & 0xff) {
1063 RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff);
1064 writemask |= (1 << i);
1065 }
1066 mask >>= 8;
1067 val >>= 8;
1068 }
1069
1070 if (writemask) {
1071 RTSX_WRITE(sc, RTSX_CFGADDR0, addr);
1072 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8);
1073 RTSX_WRITE(sc, RTSX_CFGRWCTL,
1074 RTSX_CFG_BUSY | writemask | (func & 0x03 << 4));
1075 }
1076
1077 while (tries--) {
1078 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl);
1079 if (!(rwctl & RTSX_CFG_BUSY))
1080 break;
1081 }
1082 if (tries == 0)
1083 return EIO;
1084
1085 return 0;
1086 }
1087 #endif
1088
1089 /* Append a properly encoded host command to the host command buffer. */
1090 static void
rtsx_hostcmd(uint32_t * cmdbuf,int * n,uint8_t cmd,uint16_t reg,uint8_t mask,uint8_t data)1091 rtsx_hostcmd(uint32_t *cmdbuf, int *n, uint8_t cmd, uint16_t reg,
1092 uint8_t mask, uint8_t data)
1093 {
1094
1095 KASSERT(*n < RTSX_HOSTCMD_MAX);
1096
1097 cmdbuf[(*n)++] = htole32((uint32_t)(cmd & 0x3) << 30) |
1098 ((uint32_t)(reg & 0x3fff) << 16) |
1099 ((uint32_t)(mask) << 8) |
1100 ((uint32_t)data);
1101 }
1102
1103 static void
rtsx_save_regs(struct rtsx_softc * sc)1104 rtsx_save_regs(struct rtsx_softc *sc)
1105 {
1106 int i;
1107 uint16_t reg;
1108
1109 mutex_enter(&sc->sc_host_mtx);
1110
1111 i = 0;
1112 for (reg = 0xFDA0; reg < 0xFDAE; reg++)
1113 (void)rtsx_read(sc, reg, &sc->sc_regs[i++]);
1114 for (reg = 0xFD52; reg < 0xFD69; reg++)
1115 (void)rtsx_read(sc, reg, &sc->sc_regs[i++]);
1116 for (reg = 0xFE20; reg < 0xFE34; reg++)
1117 (void)rtsx_read(sc, reg, &sc->sc_regs[i++]);
1118
1119 sc->sc_regs4[0] = READ4(sc, RTSX_HCBAR);
1120 sc->sc_regs4[1] = READ4(sc, RTSX_HCBCTLR);
1121 sc->sc_regs4[2] = READ4(sc, RTSX_HDBAR);
1122 sc->sc_regs4[3] = READ4(sc, RTSX_HDBCTLR);
1123 sc->sc_regs4[4] = READ4(sc, RTSX_HAIMR);
1124 sc->sc_regs4[5] = READ4(sc, RTSX_BIER);
1125 /* Not saving RTSX_BIPR. */
1126
1127 mutex_exit(&sc->sc_host_mtx);
1128 }
1129
1130 static void
rtsx_restore_regs(struct rtsx_softc * sc)1131 rtsx_restore_regs(struct rtsx_softc *sc)
1132 {
1133 int i;
1134 uint16_t reg;
1135
1136 mutex_enter(&sc->sc_host_mtx);
1137
1138 WRITE4(sc, RTSX_HCBAR, sc->sc_regs4[0]);
1139 WRITE4(sc, RTSX_HCBCTLR, sc->sc_regs4[1]);
1140 WRITE4(sc, RTSX_HDBAR, sc->sc_regs4[2]);
1141 WRITE4(sc, RTSX_HDBCTLR, sc->sc_regs4[3]);
1142 WRITE4(sc, RTSX_HAIMR, sc->sc_regs4[4]);
1143 WRITE4(sc, RTSX_BIER, sc->sc_regs4[5]);
1144 /* Not writing RTSX_BIPR since doing so would clear it. */
1145
1146 i = 0;
1147 for (reg = 0xFDA0; reg < 0xFDAE; reg++)
1148 (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]);
1149 for (reg = 0xFD52; reg < 0xFD69; reg++)
1150 (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]);
1151 for (reg = 0xFE20; reg < 0xFE34; reg++)
1152 (void)rtsx_write(sc, reg, 0xff, sc->sc_regs[i++]);
1153
1154 mutex_exit(&sc->sc_host_mtx);
1155 }
1156
1157 static uint8_t
rtsx_response_type(uint16_t sdmmc_rsp)1158 rtsx_response_type(uint16_t sdmmc_rsp)
1159 {
1160 static const struct rsp_type {
1161 uint16_t sdmmc_rsp;
1162 uint8_t rtsx_rsp;
1163 } rsp_types[] = {
1164 { SCF_RSP_R0, RTSX_SD_RSP_TYPE_R0 },
1165 { SCF_RSP_R1, RTSX_SD_RSP_TYPE_R1 },
1166 { SCF_RSP_R1B, RTSX_SD_RSP_TYPE_R1B },
1167 { SCF_RSP_R2, RTSX_SD_RSP_TYPE_R2 },
1168 { SCF_RSP_R3, RTSX_SD_RSP_TYPE_R3 },
1169 { SCF_RSP_R4, RTSX_SD_RSP_TYPE_R4 },
1170 { SCF_RSP_R5, RTSX_SD_RSP_TYPE_R5 },
1171 { SCF_RSP_R6, RTSX_SD_RSP_TYPE_R6 },
1172 { SCF_RSP_R7, RTSX_SD_RSP_TYPE_R7 }
1173 };
1174 size_t i;
1175
1176 for (i = 0; i < __arraycount(rsp_types); i++) {
1177 if (sdmmc_rsp == rsp_types[i].sdmmc_rsp)
1178 return rsp_types[i].rtsx_rsp;
1179 }
1180 return 0;
1181 }
1182
1183 static int
rtsx_hostcmd_send(struct rtsx_softc * sc,int ncmd)1184 rtsx_hostcmd_send(struct rtsx_softc *sc, int ncmd)
1185 {
1186
1187 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE,
1188 BUS_DMASYNC_PREWRITE);
1189
1190 mutex_enter(&sc->sc_host_mtx);
1191
1192 /* Tell the chip where the command buffer is and run the commands. */
1193 WRITE4(sc, RTSX_HCBAR, sc->sc_dmap_cmd->dm_segs[0].ds_addr);
1194 WRITE4(sc, RTSX_HCBCTLR,
1195 ((ncmd * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP);
1196
1197 mutex_exit(&sc->sc_host_mtx);
1198
1199 return 0;
1200 }
1201
1202 static int
rtsx_read_ppbuf(struct rtsx_softc * sc,struct sdmmc_command * cmd,uint32_t * cmdbuf)1203 rtsx_read_ppbuf(struct rtsx_softc *sc, struct sdmmc_command *cmd,
1204 uint32_t *cmdbuf)
1205 {
1206 uint8_t *ptr;
1207 int ncmd, remain;
1208 uint16_t reg;
1209 int error;
1210 int i, j;
1211
1212 DPRINTF(3,("%s: read %d bytes from ppbuf2\n", DEVNAME(sc),
1213 cmd->c_datalen));
1214
1215 reg = RTSX_PPBUF_BASE2;
1216 ptr = cmd->c_data;
1217 remain = cmd->c_datalen;
1218 for (j = 0; j < cmd->c_datalen / RTSX_HOSTCMD_MAX; j++) {
1219 ncmd = 0;
1220 for (i = 0; i < RTSX_HOSTCMD_MAX; i++) {
1221 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, reg++,
1222 0, 0);
1223 }
1224 error = rtsx_hostcmd_send(sc, ncmd);
1225 if (error == 0)
1226 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4);
1227 if (error)
1228 goto ret;
1229 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0,
1230 RTSX_HOSTCMD_BUFSIZE, BUS_DMASYNC_POSTREAD);
1231 memcpy(ptr, cmdbuf, RTSX_HOSTCMD_MAX);
1232 ptr += RTSX_HOSTCMD_MAX;
1233 remain -= RTSX_HOSTCMD_MAX;
1234 }
1235 if (remain > 0) {
1236 ncmd = 0;
1237 for (i = 0; i < remain; i++) {
1238 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, reg++,
1239 0, 0);
1240 }
1241 error = rtsx_hostcmd_send(sc, ncmd);
1242 if (error == 0)
1243 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4);
1244 if (error)
1245 goto ret;
1246 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0,
1247 RTSX_HOSTCMD_BUFSIZE, BUS_DMASYNC_POSTREAD);
1248 memcpy(ptr, cmdbuf, remain);
1249 }
1250 ret:
1251 return error;
1252 }
1253
1254 static int
rtsx_write_ppbuf(struct rtsx_softc * sc,struct sdmmc_command * cmd,uint32_t * cmdbuf)1255 rtsx_write_ppbuf(struct rtsx_softc *sc, struct sdmmc_command *cmd,
1256 uint32_t *cmdbuf)
1257 {
1258 const uint8_t *ptr;
1259 int ncmd, remain;
1260 uint16_t reg;
1261 int error;
1262 int i, j;
1263
1264 DPRINTF(3,("%s: write %d bytes to ppbuf2\n", DEVNAME(sc),
1265 cmd->c_datalen));
1266
1267 reg = RTSX_PPBUF_BASE2;
1268 ptr = cmd->c_data;
1269 remain = cmd->c_datalen;
1270 for (j = 0; j < cmd->c_datalen / RTSX_HOSTCMD_MAX; j++) {
1271 ncmd = 0;
1272 for (i = 0; i < RTSX_HOSTCMD_MAX; i++) {
1273 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, reg++,
1274 0xff, *ptr++);
1275 }
1276 error = rtsx_hostcmd_send(sc, ncmd);
1277 if (error == 0)
1278 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4);
1279 if (error)
1280 goto ret;
1281 remain -= RTSX_HOSTCMD_MAX;
1282 }
1283 if (remain > 0) {
1284 ncmd = 0;
1285 for (i = 0; i < remain; i++) {
1286 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, reg++,
1287 0xff, *ptr++);
1288 }
1289 error = rtsx_hostcmd_send(sc, ncmd);
1290 if (error == 0)
1291 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz / 4);
1292 if (error)
1293 goto ret;
1294 }
1295 ret:
1296 return error;
1297 }
1298
1299 static int
rtsx_exec_short_xfer(struct rtsx_softc * sc,struct sdmmc_command * cmd,uint32_t * cmdbuf,uint8_t rsp_type)1300 rtsx_exec_short_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd,
1301 uint32_t *cmdbuf, uint8_t rsp_type)
1302 {
1303 int read = ISSET(cmd->c_flags, SCF_CMD_READ);
1304 int ncmd;
1305 uint8_t tmode = read ? RTSX_TM_NORMAL_READ : RTSX_TM_AUTO_WRITE2;
1306 int error;
1307
1308 DPRINTF(3,("%s: %s short xfer: %d bytes with block size %d\n",
1309 DEVNAME(sc), read ? "read" : "write", cmd->c_datalen,
1310 cmd->c_blklen));
1311
1312 if (cmd->c_datalen > 512) {
1313 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n",
1314 DEVNAME(sc), cmd->c_datalen, 512));
1315 return ENOMEM;
1316 }
1317
1318 if (!read && cmd->c_data != NULL && cmd->c_datalen > 0) {
1319 error = rtsx_write_ppbuf(sc, cmd, cmdbuf);
1320 if (error)
1321 goto ret;
1322 }
1323
1324 /* The command buffer queues commands the host controller will
1325 * run asynchronously. */
1326 ncmd = 0;
1327
1328 /* Queue commands to set SD command index and argument. */
1329 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0,
1330 0xff, 0x40 | cmd->c_opcode);
1331 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1,
1332 0xff, cmd->c_arg >> 24);
1333 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2,
1334 0xff, cmd->c_arg >> 16);
1335 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3,
1336 0xff, cmd->c_arg >> 8);
1337 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4,
1338 0xff, cmd->c_arg);
1339
1340 /* Queue commands to configure data transfer size. */
1341 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L,
1342 0xff, cmd->c_datalen);
1343 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H,
1344 0xff, cmd->c_datalen >> 8);
1345 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L,
1346 0xff, 0x01);
1347 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H,
1348 0xff, 0x00);
1349
1350 /* Queue command to set response type. */
1351 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,
1352 0xff, rsp_type);
1353
1354 if (tmode == RTSX_TM_NORMAL_READ) {
1355 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD,
1356 RTSX_CARD_DATA_SOURCE, 0x01, RTSX_PINGPONG_BUFFER);
1357 }
1358
1359 /* Queue commands to perform SD transfer. */
1360 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
1361 0xff, tmode | RTSX_SD_TRANSFER_START);
1362 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
1363 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END);
1364
1365 /* Run the command queue and wait for completion. */
1366 error = rtsx_hostcmd_send(sc, ncmd);
1367 if (error == 0)
1368 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 2 * hz);
1369 if (error)
1370 goto ret;
1371
1372 if (read && cmd->c_data != NULL && cmd->c_datalen > 0)
1373 error = rtsx_read_ppbuf(sc, cmd, cmdbuf);
1374 ret:
1375 DPRINTF(3,("%s: short xfer done, error=%d\n", DEVNAME(sc), error));
1376 return error;
1377 }
1378
1379 static int
rtsx_xfer(struct rtsx_softc * sc,struct sdmmc_command * cmd,uint32_t * cmdbuf)1380 rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, uint32_t *cmdbuf)
1381 {
1382 int ncmd, dma_dir, error, tmode;
1383 int read = ISSET(cmd->c_flags, SCF_CMD_READ);
1384 uint8_t cfg2;
1385
1386 DPRINTF(3,("%s: %s xfer: %d bytes with block size %d\n", DEVNAME(sc),
1387 read ? "read" : "write", cmd->c_datalen, cmd->c_blklen));
1388
1389 if (cmd->c_datalen > RTSX_DMA_DATA_BUFSIZE) {
1390 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n",
1391 DEVNAME(sc), cmd->c_datalen, RTSX_DMA_DATA_BUFSIZE));
1392 return ENOMEM;
1393 }
1394
1395 /* Configure DMA transfer mode parameters. */
1396 cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO | RTSX_SD_CHECK_CRC16 |
1397 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0;
1398 if (read) {
1399 dma_dir = RTSX_DMA_DIR_FROM_CARD;
1400 /* Use transfer mode AUTO_READ3, which assumes we've already
1401 * sent the read command and gotten the response, and will
1402 * send CMD 12 manually after reading multiple blocks. */
1403 tmode = RTSX_TM_AUTO_READ3;
1404 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7;
1405 } else {
1406 dma_dir = RTSX_DMA_DIR_TO_CARD;
1407 /* Use transfer mode AUTO_WRITE3, which assumes we've already
1408 * sent the write command and gotten the response, and will
1409 * send CMD 12 manually after writing multiple blocks. */
1410 tmode = RTSX_TM_AUTO_WRITE3;
1411 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7;
1412 }
1413
1414 /* The command buffer queues commands the host controller will
1415 * run asynchronously. */
1416 ncmd = 0;
1417
1418 /* Queue command to set response type. */
1419 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,
1420 0xff, cfg2);
1421
1422 /* Queue commands to configure data transfer size. */
1423 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L,
1424 0xff, 0x00);
1425 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H,
1426 0xff, 0x02);
1427 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L,
1428 0xff, cmd->c_datalen / cmd->c_blklen);
1429 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H,
1430 0xff, (cmd->c_datalen / cmd->c_blklen) >> 8);
1431
1432 /* Use the DMA ring buffer for commands which transfer data. */
1433 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,
1434 0x01, RTSX_RING_BUFFER);
1435
1436 /* Configure DMA controller. */
1437 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0,
1438 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT);
1439 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC3,
1440 0xff, cmd->c_datalen >> 24);
1441 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC2,
1442 0xff, cmd->c_datalen >> 16);
1443 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC1,
1444 0xff, cmd->c_datalen >> 8);
1445 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMATC0,
1446 0xff, cmd->c_datalen);
1447 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_DMACTL,
1448 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK,
1449 RTSX_DMA_EN | dma_dir | RTSX_DMA_512);
1450
1451 /* Queue commands to perform SD transfer. */
1452 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
1453 0xff, tmode | RTSX_SD_TRANSFER_START);
1454 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
1455 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END);
1456
1457 error = rtsx_hostcmd_send(sc, ncmd);
1458 if (error)
1459 goto ret;
1460
1461 mutex_enter(&sc->sc_host_mtx);
1462
1463 /* Tell the chip where the data buffer is and run the transfer. */
1464 WRITE4(sc, RTSX_HDBAR, cmd->c_dmamap->dm_segs[0].ds_addr);
1465 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) |
1466 (cmd->c_dmamap->dm_segs[0].ds_len & 0x00ffffff));
1467
1468 mutex_exit(&sc->sc_host_mtx);
1469
1470 /* Wait for completion. */
1471 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 10*hz);
1472 ret:
1473 DPRINTF(3,("%s: xfer done, error=%d\n", DEVNAME(sc), error));
1474 return error;
1475 }
1476
1477 static void
rtsx_exec_command(sdmmc_chipset_handle_t sch,struct sdmmc_command * cmd)1478 rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
1479 {
1480 struct rtsx_softc *sc = sch;
1481 bus_dma_segment_t segs[1];
1482 int rsegs;
1483 void *cmdkvap;
1484 uint32_t *cmdbuf;
1485 uint8_t rsp_type;
1486 uint16_t r;
1487 int ncmd;
1488 int error = 0;
1489
1490 DPRINTF(3,("%s: executing cmd %hu\n", DEVNAME(sc), cmd->c_opcode));
1491
1492 /* Refuse SDIO probe if the chip doesn't support SDIO. */
1493 if (cmd->c_opcode == SD_IO_SEND_OP_COND &&
1494 !ISSET(sc->sc_flags, RTSX_F_SDIO_SUPPORT)) {
1495 error = ENOTSUP;
1496 goto ret;
1497 }
1498
1499 rsp_type = rtsx_response_type(cmd->c_flags & SCF_RSP_MASK);
1500 if (rsp_type == 0) {
1501 aprint_error_dev(sc->sc_dev, "unknown response type 0x%x\n",
1502 cmd->c_flags & SCF_RSP_MASK);
1503 error = EINVAL;
1504 goto ret;
1505 }
1506
1507 /* Allocate and map the host command buffer. */
1508 error = bus_dmamem_alloc(sc->sc_dmat, RTSX_HOSTCMD_BUFSIZE, 0, 0,
1509 segs, 1, &rsegs, BUS_DMA_WAITOK);
1510 if (error)
1511 goto ret;
1512 error = bus_dmamem_map(sc->sc_dmat, segs, rsegs, RTSX_HOSTCMD_BUFSIZE,
1513 &cmdkvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT);
1514 if (error)
1515 goto free_cmdbuf;
1516
1517 /* Load command DMA buffer. */
1518 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmap_cmd, cmdkvap,
1519 RTSX_HOSTCMD_BUFSIZE, NULL, BUS_DMA_WAITOK);
1520 if (error)
1521 goto unmap_cmdbuf;
1522
1523 /* Use another transfer method when data size < 512. */
1524 if (cmd->c_data != NULL && cmd->c_datalen < 512) {
1525 error = rtsx_exec_short_xfer(sch, cmd, cmdkvap, rsp_type);
1526 goto unload_cmdbuf;
1527 }
1528
1529 /* The command buffer queues commands the host controller will
1530 * run asynchronously. */
1531 cmdbuf = cmdkvap;
1532 ncmd = 0;
1533
1534 /* Queue commands to set SD command index and argument. */
1535 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0,
1536 0xff, 0x40 | cmd->c_opcode);
1537 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1,
1538 0xff, cmd->c_arg >> 24);
1539 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2,
1540 0xff, cmd->c_arg >> 16);
1541 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3,
1542 0xff, cmd->c_arg >> 8);
1543 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4,
1544 0xff, cmd->c_arg);
1545
1546 /* Queue command to set response type. */
1547 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,
1548 0xff, rsp_type);
1549
1550 /* Use the ping-pong buffer for commands which do not transfer data. */
1551 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,
1552 0x01, RTSX_PINGPONG_BUFFER);
1553
1554 /* Queue commands to perform SD transfer. */
1555 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
1556 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START);
1557 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
1558 RTSX_SD_TRANSFER_END | RTSX_SD_STAT_IDLE,
1559 RTSX_SD_TRANSFER_END | RTSX_SD_STAT_IDLE);
1560
1561 /* Queue commands to read back card status response.*/
1562 if (rsp_type == RTSX_SD_RSP_TYPE_R2) {
1563 for (r = RTSX_PPBUF_BASE2 + 15; r > RTSX_PPBUF_BASE2; r--)
1564 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0);
1565 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, RTSX_SD_CMD5,
1566 0, 0);
1567 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) {
1568 for (r = RTSX_SD_CMD0; r <= RTSX_SD_CMD4; r++)
1569 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0);
1570 }
1571
1572 /* Run the command queue and wait for completion. */
1573 error = rtsx_hostcmd_send(sc, ncmd);
1574 if (error == 0)
1575 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz);
1576 if (error)
1577 goto unload_cmdbuf;
1578
1579 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE,
1580 BUS_DMASYNC_POSTREAD);
1581
1582 /* Copy card response into sdmmc response buffer. */
1583 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
1584 /* Copy bytes like sdhc(4), which on little-endian uses
1585 * different byte order for short and long responses... */
1586 if (ISSET(cmd->c_flags, SCF_RSP_136)) {
1587 uint8_t *resp = cmdkvap;
1588 memcpy(cmd->c_resp, resp + 1, sizeof(cmd->c_resp));
1589 } else {
1590 /* First byte is CHECK_REG_CMD return value, second
1591 * one is the command op code -- we skip those. */
1592 cmd->c_resp[0] =
1593 ((be32toh(cmdbuf[0]) & 0x0000ffff) << 16) |
1594 ((be32toh(cmdbuf[1]) & 0xffff0000) >> 16);
1595 }
1596 }
1597
1598 if (cmd->c_data) {
1599 error = rtsx_xfer(sc, cmd, cmdbuf);
1600 if (error) {
1601 uint8_t stat1;
1602 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 &&
1603 (stat1 & RTSX_SD_CRC_ERR)) {
1604 aprint_error_dev(sc->sc_dev,
1605 "CRC error (stat=0x%x)\n", stat1);
1606 }
1607 }
1608 }
1609
1610 unload_cmdbuf:
1611 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmap_cmd);
1612 unmap_cmdbuf:
1613 bus_dmamem_unmap(sc->sc_dmat, cmdkvap, RTSX_HOSTCMD_BUFSIZE);
1614 free_cmdbuf:
1615 bus_dmamem_free(sc->sc_dmat, segs, rsegs);
1616 ret:
1617 SET(cmd->c_flags, SCF_ITSDONE);
1618 cmd->c_error = error;
1619 }
1620
1621 /* Prepare for another command. */
1622 static void
rtsx_soft_reset(struct rtsx_softc * sc)1623 rtsx_soft_reset(struct rtsx_softc *sc)
1624 {
1625
1626 DPRINTF(1,("%s: soft reset\n", DEVNAME(sc)));
1627
1628 /* Stop command transfer. */
1629 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD);
1630
1631 (void)rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP|RTSX_SD_CLR_ERR,
1632 RTSX_SD_STOP|RTSX_SD_CLR_ERR);
1633
1634 /* Stop DMA transfer. */
1635 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA);
1636 (void)rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST);
1637
1638 (void)rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH);
1639 }
1640
1641 static int
rtsx_wait_intr(struct rtsx_softc * sc,int mask,int timo)1642 rtsx_wait_intr(struct rtsx_softc *sc, int mask, int timo)
1643 {
1644 int status;
1645 int error = 0;
1646
1647 mask |= RTSX_TRANS_FAIL_INT;
1648
1649 mutex_enter(&sc->sc_intr_mtx);
1650
1651 status = sc->sc_intr_status & mask;
1652 while (status == 0) {
1653 if (cv_timedwait(&sc->sc_intr_cv, &sc->sc_intr_mtx, timo)
1654 == EWOULDBLOCK) {
1655 rtsx_soft_reset(sc);
1656 error = ETIMEDOUT;
1657 break;
1658 }
1659 status = sc->sc_intr_status & mask;
1660 }
1661 sc->sc_intr_status &= ~status;
1662
1663 /* Has the card disappeared? */
1664 if (!ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT))
1665 error = ENODEV;
1666
1667 mutex_exit(&sc->sc_intr_mtx);
1668
1669 if (error == 0 && (status & RTSX_TRANS_FAIL_INT))
1670 error = EIO;
1671 return error;
1672 }
1673
1674 static void
rtsx_card_insert(struct rtsx_softc * sc)1675 rtsx_card_insert(struct rtsx_softc *sc)
1676 {
1677
1678 DPRINTF(1, ("%s: card inserted\n", DEVNAME(sc)));
1679
1680 sc->sc_flags |= RTSX_F_CARD_PRESENT;
1681 (void)rtsx_led_enable(sc);
1682
1683 /* Schedule card discovery task. */
1684 sdmmc_needs_discover(sc->sc_sdmmc);
1685 }
1686
1687 static void
rtsx_card_eject(struct rtsx_softc * sc)1688 rtsx_card_eject(struct rtsx_softc *sc)
1689 {
1690
1691 DPRINTF(1, ("%s: card ejected\n", DEVNAME(sc)));
1692
1693 sc->sc_flags &= ~RTSX_F_CARD_PRESENT;
1694 (void)rtsx_led_disable(sc);
1695
1696 /* Schedule card discovery task. */
1697 sdmmc_needs_discover(sc->sc_sdmmc);
1698 }
1699
1700 /*
1701 * Established by attachment driver at interrupt priority IPL_SDMMC.
1702 */
1703 int
rtsx_intr(void * arg)1704 rtsx_intr(void *arg)
1705 {
1706 struct rtsx_softc *sc = arg;
1707 uint32_t enabled, status;
1708
1709 enabled = READ4(sc, RTSX_BIER);
1710 status = READ4(sc, RTSX_BIPR);
1711
1712 /* Ack interrupts. */
1713 WRITE4(sc, RTSX_BIPR, status);
1714
1715 if (((enabled & status) == 0) || status == 0xffffffff)
1716 return 0;
1717
1718 mutex_enter(&sc->sc_intr_mtx);
1719
1720 if (status & RTSX_SD_INT) {
1721 if (status & RTSX_SD_EXIST) {
1722 if (!ISSET(sc->sc_flags, RTSX_F_CARD_PRESENT))
1723 rtsx_card_insert(sc);
1724 } else {
1725 rtsx_card_eject(sc);
1726 }
1727 }
1728
1729 if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) {
1730 sc->sc_intr_status |= status;
1731 cv_broadcast(&sc->sc_intr_cv);
1732 }
1733
1734 mutex_exit(&sc->sc_intr_mtx);
1735
1736 return 1;
1737 }
1738