1 /* $NetBSD: radeon_rs780_dpm.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */
2
3 /*
4 * Copyright 2011 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: radeon_rs780_dpm.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
29
30 #include <linux/pci.h>
31 #include <linux/seq_file.h>
32
33 #include "atom.h"
34 #include "r600_dpm.h"
35 #include "radeon.h"
36 #include "radeon_asic.h"
37 #include "rs780_dpm.h"
38 #include "rs780d.h"
39
rs780_get_ps(struct radeon_ps * rps)40 static struct igp_ps *rs780_get_ps(struct radeon_ps *rps)
41 {
42 struct igp_ps *ps = rps->ps_priv;
43
44 return ps;
45 }
46
rs780_get_pi(struct radeon_device * rdev)47 static struct igp_power_info *rs780_get_pi(struct radeon_device *rdev)
48 {
49 struct igp_power_info *pi = rdev->pm.dpm.priv;
50
51 return pi;
52 }
53
rs780_get_pm_mode_parameters(struct radeon_device * rdev)54 static void rs780_get_pm_mode_parameters(struct radeon_device *rdev)
55 {
56 struct igp_power_info *pi = rs780_get_pi(rdev);
57 struct radeon_mode_info *minfo = &rdev->mode_info;
58 struct drm_crtc *crtc;
59 struct radeon_crtc *radeon_crtc;
60 int i;
61
62 /* defaults */
63 pi->crtc_id = 0;
64 pi->refresh_rate = 60;
65
66 for (i = 0; i < rdev->num_crtc; i++) {
67 crtc = (struct drm_crtc *)minfo->crtcs[i];
68 if (crtc && crtc->enabled) {
69 radeon_crtc = to_radeon_crtc(crtc);
70 pi->crtc_id = radeon_crtc->crtc_id;
71 if (crtc->mode.htotal && crtc->mode.vtotal)
72 pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);
73 break;
74 }
75 }
76 }
77
78 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable);
79
rs780_initialize_dpm_power_state(struct radeon_device * rdev,struct radeon_ps * boot_ps)80 static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
81 struct radeon_ps *boot_ps)
82 {
83 struct atom_clock_dividers dividers;
84 struct igp_ps *default_state = rs780_get_ps(boot_ps);
85 int i, ret;
86
87 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
88 default_state->sclk_low, false, ÷rs);
89 if (ret)
90 return ret;
91
92 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div);
93 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div);
94 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div);
95
96 if (dividers.enable_post_div)
97 r600_engine_clock_entry_enable_post_divider(rdev, 0, true);
98 else
99 r600_engine_clock_entry_enable_post_divider(rdev, 0, false);
100
101 r600_engine_clock_entry_set_step_time(rdev, 0, R600_SST_DFLT);
102 r600_engine_clock_entry_enable_pulse_skipping(rdev, 0, false);
103
104 r600_engine_clock_entry_enable(rdev, 0, true);
105 for (i = 1; i < R600_PM_NUMBER_OF_SCLKS; i++)
106 r600_engine_clock_entry_enable(rdev, i, false);
107
108 r600_enable_mclk_control(rdev, false);
109 r600_voltage_control_enable_pins(rdev, 0);
110
111 return 0;
112 }
113
rs780_initialize_dpm_parameters(struct radeon_device * rdev,struct radeon_ps * boot_ps)114 static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
115 struct radeon_ps *boot_ps)
116 {
117 int ret = 0;
118 int i;
119
120 r600_set_bsp(rdev, R600_BSU_DFLT, R600_BSP_DFLT);
121
122 r600_set_at(rdev, 0, 0, 0, 0);
123
124 r600_set_git(rdev, R600_GICST_DFLT);
125
126 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
127 r600_set_tc(rdev, i, 0, 0);
128
129 r600_select_td(rdev, R600_TD_DFLT);
130 r600_set_vrc(rdev, 0);
131
132 r600_set_tpu(rdev, R600_TPU_DFLT);
133 r600_set_tpc(rdev, R600_TPC_DFLT);
134
135 r600_set_sstu(rdev, R600_SSTU_DFLT);
136 r600_set_sst(rdev, R600_SST_DFLT);
137
138 r600_set_fctu(rdev, R600_FCTU_DFLT);
139 r600_set_fct(rdev, R600_FCT_DFLT);
140
141 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
142 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
143 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
144 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
145 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
146
147 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
148 r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
149 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
150
151 ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
152
153 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
154 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
155 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH, 0);
156
157 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
158 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
159 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
160
161 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
162 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
163 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH, 0);
164
165 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW, R600_DISPLAY_WATERMARK_HIGH);
166 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM, R600_DISPLAY_WATERMARK_HIGH);
167 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH, R600_DISPLAY_WATERMARK_HIGH);
168
169 r600_power_level_enable(rdev, R600_POWER_LEVEL_CTXSW, false);
170 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
171 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
172 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
173
174 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_LOW);
175
176 r600_set_vrc(rdev, RS780_CGFTV_DFLT);
177
178 return ret;
179 }
180
rs780_start_dpm(struct radeon_device * rdev)181 static void rs780_start_dpm(struct radeon_device *rdev)
182 {
183 r600_enable_sclk_control(rdev, false);
184 r600_enable_mclk_control(rdev, false);
185
186 r600_dynamicpm_enable(rdev, true);
187
188 radeon_wait_for_vblank(rdev, 0);
189 radeon_wait_for_vblank(rdev, 1);
190
191 r600_enable_spll_bypass(rdev, true);
192 r600_wait_for_spll_change(rdev);
193 r600_enable_spll_bypass(rdev, false);
194 r600_wait_for_spll_change(rdev);
195
196 r600_enable_spll_bypass(rdev, true);
197 r600_wait_for_spll_change(rdev);
198 r600_enable_spll_bypass(rdev, false);
199 r600_wait_for_spll_change(rdev);
200
201 r600_enable_sclk_control(rdev, true);
202 }
203
204
rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device * rdev)205 static void rs780_preset_ranges_slow_clk_fbdiv_en(struct radeon_device *rdev)
206 {
207 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN,
208 ~RANGE_SLOW_CLK_FEEDBACK_DIV_EN);
209
210 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1,
211 RANGE0_SLOW_CLK_FEEDBACK_DIV(RS780_SLOWCLKFEEDBACKDIV_DFLT),
212 ~RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK);
213 }
214
rs780_preset_starting_fbdiv(struct radeon_device * rdev)215 static void rs780_preset_starting_fbdiv(struct radeon_device *rdev)
216 {
217 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
218
219 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv),
220 ~STARTING_FEEDBACK_DIV_MASK);
221
222 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv),
223 ~FORCED_FEEDBACK_DIV_MASK);
224
225 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
226 }
227
rs780_voltage_scaling_init(struct radeon_device * rdev)228 static void rs780_voltage_scaling_init(struct radeon_device *rdev)
229 {
230 struct igp_power_info *pi = rs780_get_pi(rdev);
231 struct drm_device *dev = rdev->ddev;
232 u32 fv_throt_pwm_fb_div_range[3];
233 u32 fv_throt_pwm_range[4];
234
235 if (dev->pdev->device == 0x9614) {
236 fv_throt_pwm_fb_div_range[0] = RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
237 fv_throt_pwm_fb_div_range[1] = RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
238 fv_throt_pwm_fb_div_range[2] = RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
239 } else if ((dev->pdev->device == 0x9714) ||
240 (dev->pdev->device == 0x9715)) {
241 fv_throt_pwm_fb_div_range[0] = RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT;
242 fv_throt_pwm_fb_div_range[1] = RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT;
243 fv_throt_pwm_fb_div_range[2] = RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT;
244 } else {
245 fv_throt_pwm_fb_div_range[0] = RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT;
246 fv_throt_pwm_fb_div_range[1] = RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT;
247 fv_throt_pwm_fb_div_range[2] = RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT;
248 }
249
250 if (pi->pwm_voltage_control) {
251 fv_throt_pwm_range[0] = pi->min_voltage;
252 fv_throt_pwm_range[1] = pi->min_voltage;
253 fv_throt_pwm_range[2] = pi->max_voltage;
254 fv_throt_pwm_range[3] = pi->max_voltage;
255 } else {
256 fv_throt_pwm_range[0] = pi->invert_pwm_required ?
257 RS780_FVTHROTPWMRANGE3_GPIO_DFLT : RS780_FVTHROTPWMRANGE0_GPIO_DFLT;
258 fv_throt_pwm_range[1] = pi->invert_pwm_required ?
259 RS780_FVTHROTPWMRANGE2_GPIO_DFLT : RS780_FVTHROTPWMRANGE1_GPIO_DFLT;
260 fv_throt_pwm_range[2] = pi->invert_pwm_required ?
261 RS780_FVTHROTPWMRANGE1_GPIO_DFLT : RS780_FVTHROTPWMRANGE2_GPIO_DFLT;
262 fv_throt_pwm_range[3] = pi->invert_pwm_required ?
263 RS780_FVTHROTPWMRANGE0_GPIO_DFLT : RS780_FVTHROTPWMRANGE3_GPIO_DFLT;
264 }
265
266 WREG32_P(FVTHROT_PWM_CTRL_REG0,
267 STARTING_PWM_HIGHTIME(pi->max_voltage),
268 ~STARTING_PWM_HIGHTIME_MASK);
269
270 WREG32_P(FVTHROT_PWM_CTRL_REG0,
271 NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),
272 ~NUMBER_OF_CYCLES_IN_PERIOD_MASK);
273
274 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME,
275 ~FORCE_STARTING_PWM_HIGHTIME);
276
277 if (pi->invert_pwm_required)
278 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM);
279 else
280 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM);
281
282 rs780_voltage_scaling_enable(rdev, true);
283
284 WREG32(FVTHROT_PWM_CTRL_REG1,
285 (MIN_PWM_HIGHTIME(pi->min_voltage) |
286 MAX_PWM_HIGHTIME(pi->max_voltage)));
287
288 WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);
289 WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);
290 WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);
291 WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);
292
293 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
294 RANGE0_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[0]),
295 ~RANGE0_PWM_FEEDBACK_DIV_MASK);
296
297 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,
298 (RANGE1_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[1]) |
299 RANGE2_PWM_FEEDBACK_DIV(fv_throt_pwm_fb_div_range[2])));
300
301 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,
302 (RANGE0_PWM(fv_throt_pwm_range[1]) |
303 RANGE1_PWM(fv_throt_pwm_range[2])));
304 WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,
305 (RANGE2_PWM(fv_throt_pwm_range[1]) |
306 RANGE3_PWM(fv_throt_pwm_range[2])));
307 }
308
rs780_clk_scaling_enable(struct radeon_device * rdev,bool enable)309 static void rs780_clk_scaling_enable(struct radeon_device *rdev, bool enable)
310 {
311 if (enable)
312 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT | ENABLE_FV_UPDATE,
313 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
314 else
315 WREG32_P(FVTHROT_CNTRL_REG, 0,
316 ~(ENABLE_FV_THROT | ENABLE_FV_UPDATE));
317 }
318
rs780_voltage_scaling_enable(struct radeon_device * rdev,bool enable)319 static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool enable)
320 {
321 if (enable)
322 WREG32_P(FVTHROT_CNTRL_REG, ENABLE_FV_THROT_IO, ~ENABLE_FV_THROT_IO);
323 else
324 WREG32_P(FVTHROT_CNTRL_REG, 0, ~ENABLE_FV_THROT_IO);
325 }
326
rs780_set_engine_clock_wfc(struct radeon_device * rdev)327 static void rs780_set_engine_clock_wfc(struct radeon_device *rdev)
328 {
329 WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);
330 WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);
331 WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);
332 WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);
333 WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);
334
335 WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);
336 WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);
337 WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);
338 WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);
339 WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);
340 }
341
rs780_set_engine_clock_sc(struct radeon_device * rdev)342 static void rs780_set_engine_clock_sc(struct radeon_device *rdev)
343 {
344 WREG32_P(FVTHROT_FBDIV_REG2,
345 FB_DIV_TIMER_VAL(RS780_FBDIVTIMERVAL_DFLT),
346 ~FB_DIV_TIMER_VAL_MASK);
347
348 WREG32_P(FVTHROT_CNTRL_REG,
349 REFRESH_RATE_DIVISOR(0) | MINIMUM_CIP(0xf),
350 ~(REFRESH_RATE_DIVISOR_MASK | MINIMUM_CIP_MASK));
351 }
352
rs780_set_engine_clock_tdc(struct radeon_device * rdev)353 static void rs780_set_engine_clock_tdc(struct radeon_device *rdev)
354 {
355 WREG32_P(FVTHROT_CNTRL_REG, 0, ~(FORCE_TREND_SEL | TREND_SEL_MODE));
356 }
357
rs780_set_engine_clock_ssc(struct radeon_device * rdev)358 static void rs780_set_engine_clock_ssc(struct radeon_device *rdev)
359 {
360 WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);
361 WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);
362 WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);
363 WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);
364
365 WREG32_P(FVTHROT_FBDIV_REG1, MAX_FEEDBACK_STEP(1), ~MAX_FEEDBACK_STEP_MASK);
366 }
367
rs780_program_at(struct radeon_device * rdev)368 static void rs780_program_at(struct radeon_device *rdev)
369 {
370 struct igp_power_info *pi = rs780_get_pi(rdev);
371
372 WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);
373 WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);
374 WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);
375 WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);
376 WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);
377 }
378
rs780_disable_vbios_powersaving(struct radeon_device * rdev)379 static void rs780_disable_vbios_powersaving(struct radeon_device *rdev)
380 {
381 WREG32_P(CG_INTGFX_MISC, 0, ~0xFFF00000);
382 }
383
rs780_force_voltage(struct radeon_device * rdev,u16 voltage)384 static void rs780_force_voltage(struct radeon_device *rdev, u16 voltage)
385 {
386 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
387
388 if ((current_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
389 (current_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
390 return;
391
392 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
393
394 udelay(1);
395
396 WREG32_P(FVTHROT_PWM_CTRL_REG0,
397 STARTING_PWM_HIGHTIME(voltage),
398 ~STARTING_PWM_HIGHTIME_MASK);
399
400 WREG32_P(FVTHROT_PWM_CTRL_REG0,
401 FORCE_STARTING_PWM_HIGHTIME, ~FORCE_STARTING_PWM_HIGHTIME);
402
403 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1, 0,
404 ~RANGE_PWM_FEEDBACK_DIV_EN);
405
406 udelay(1);
407
408 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
409 }
410
rs780_force_fbdiv(struct radeon_device * rdev,u32 fb_div)411 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div)
412 {
413 struct igp_ps *current_state = rs780_get_ps(rdev->pm.dpm.current_ps);
414
415 if (current_state->sclk_low == current_state->sclk_high)
416 return;
417
418 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
419
420 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div),
421 ~FORCED_FEEDBACK_DIV_MASK);
422 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div),
423 ~STARTING_FEEDBACK_DIV_MASK);
424 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV);
425
426 udelay(100);
427
428 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
429 }
430
rs780_set_engine_clock_scaling(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)431 static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
432 struct radeon_ps *new_ps,
433 struct radeon_ps *old_ps)
434 {
435 struct atom_clock_dividers min_dividers, max_dividers, current_max_dividers;
436 struct igp_ps *new_state = rs780_get_ps(new_ps);
437 struct igp_ps *old_state = rs780_get_ps(old_ps);
438 int ret;
439
440 if ((new_state->sclk_high == old_state->sclk_high) &&
441 (new_state->sclk_low == old_state->sclk_low))
442 return 0;
443
444 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
445 new_state->sclk_low, false, &min_dividers);
446 if (ret)
447 return ret;
448
449 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
450 new_state->sclk_high, false, &max_dividers);
451 if (ret)
452 return ret;
453
454 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
455 old_state->sclk_high, false, ¤t_max_dividers);
456 if (ret)
457 return ret;
458
459 if ((min_dividers.ref_div != max_dividers.ref_div) ||
460 (min_dividers.post_div != max_dividers.post_div) ||
461 (max_dividers.ref_div != current_max_dividers.ref_div) ||
462 (max_dividers.post_div != current_max_dividers.post_div))
463 return -EINVAL;
464
465 rs780_force_fbdiv(rdev, max_dividers.fb_div);
466
467 if (max_dividers.fb_div > min_dividers.fb_div) {
468 WREG32_P(FVTHROT_FBDIV_REG0,
469 MIN_FEEDBACK_DIV(min_dividers.fb_div) |
470 MAX_FEEDBACK_DIV(max_dividers.fb_div),
471 ~(MIN_FEEDBACK_DIV_MASK | MAX_FEEDBACK_DIV_MASK));
472
473 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
474 }
475
476 return 0;
477 }
478
rs780_set_engine_clock_spc(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)479 static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
480 struct radeon_ps *new_ps,
481 struct radeon_ps *old_ps)
482 {
483 struct igp_ps *new_state = rs780_get_ps(new_ps);
484 struct igp_ps *old_state = rs780_get_ps(old_ps);
485 struct igp_power_info *pi = rs780_get_pi(rdev);
486
487 if ((new_state->sclk_high == old_state->sclk_high) &&
488 (new_state->sclk_low == old_state->sclk_low))
489 return;
490
491 if (pi->crtc_id == 0)
492 WREG32_P(CG_INTGFX_MISC, 0, ~FVTHROT_VBLANK_SEL);
493 else
494 WREG32_P(CG_INTGFX_MISC, FVTHROT_VBLANK_SEL, ~FVTHROT_VBLANK_SEL);
495
496 }
497
rs780_activate_engine_clk_scaling(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)498 static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
499 struct radeon_ps *new_ps,
500 struct radeon_ps *old_ps)
501 {
502 struct igp_ps *new_state = rs780_get_ps(new_ps);
503 struct igp_ps *old_state = rs780_get_ps(old_ps);
504
505 if ((new_state->sclk_high == old_state->sclk_high) &&
506 (new_state->sclk_low == old_state->sclk_low))
507 return;
508
509 if (new_state->sclk_high == new_state->sclk_low)
510 return;
511
512 rs780_clk_scaling_enable(rdev, true);
513 }
514
rs780_get_voltage_for_vddc_level(struct radeon_device * rdev,enum rs780_vddc_level vddc)515 static u32 rs780_get_voltage_for_vddc_level(struct radeon_device *rdev,
516 enum rs780_vddc_level vddc)
517 {
518 struct igp_power_info *pi = rs780_get_pi(rdev);
519
520 if (vddc == RS780_VDDC_LEVEL_HIGH)
521 return pi->max_voltage;
522 else if (vddc == RS780_VDDC_LEVEL_LOW)
523 return pi->min_voltage;
524 else
525 return pi->max_voltage;
526 }
527
rs780_enable_voltage_scaling(struct radeon_device * rdev,struct radeon_ps * new_ps)528 static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
529 struct radeon_ps *new_ps)
530 {
531 struct igp_ps *new_state = rs780_get_ps(new_ps);
532 struct igp_power_info *pi = rs780_get_pi(rdev);
533 enum rs780_vddc_level vddc_high, vddc_low;
534
535 udelay(100);
536
537 if ((new_state->max_voltage == RS780_VDDC_LEVEL_HIGH) &&
538 (new_state->min_voltage == RS780_VDDC_LEVEL_HIGH))
539 return;
540
541 vddc_high = rs780_get_voltage_for_vddc_level(rdev,
542 new_state->max_voltage);
543 vddc_low = rs780_get_voltage_for_vddc_level(rdev,
544 new_state->min_voltage);
545
546 WREG32_P(GFX_MACRO_BYPASS_CNTL, SPLL_BYPASS_CNTL, ~SPLL_BYPASS_CNTL);
547
548 udelay(1);
549 if (vddc_high > vddc_low) {
550 WREG32_P(FVTHROT_PWM_FEEDBACK_DIV_REG1,
551 RANGE_PWM_FEEDBACK_DIV_EN, ~RANGE_PWM_FEEDBACK_DIV_EN);
552
553 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~FORCE_STARTING_PWM_HIGHTIME);
554 } else if (vddc_high == vddc_low) {
555 if (pi->max_voltage != vddc_high) {
556 WREG32_P(FVTHROT_PWM_CTRL_REG0,
557 STARTING_PWM_HIGHTIME(vddc_high),
558 ~STARTING_PWM_HIGHTIME_MASK);
559
560 WREG32_P(FVTHROT_PWM_CTRL_REG0,
561 FORCE_STARTING_PWM_HIGHTIME,
562 ~FORCE_STARTING_PWM_HIGHTIME);
563 }
564 }
565
566 WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
567 }
568
rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)569 static void rs780_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
570 struct radeon_ps *new_ps,
571 struct radeon_ps *old_ps)
572 {
573 struct igp_ps *new_state = rs780_get_ps(new_ps);
574 struct igp_ps *current_state = rs780_get_ps(old_ps);
575
576 if ((new_ps->vclk == old_ps->vclk) &&
577 (new_ps->dclk == old_ps->dclk))
578 return;
579
580 if (new_state->sclk_high >= current_state->sclk_high)
581 return;
582
583 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
584 }
585
rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device * rdev,struct radeon_ps * new_ps,struct radeon_ps * old_ps)586 static void rs780_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
587 struct radeon_ps *new_ps,
588 struct radeon_ps *old_ps)
589 {
590 struct igp_ps *new_state = rs780_get_ps(new_ps);
591 struct igp_ps *current_state = rs780_get_ps(old_ps);
592
593 if ((new_ps->vclk == old_ps->vclk) &&
594 (new_ps->dclk == old_ps->dclk))
595 return;
596
597 if (new_state->sclk_high < current_state->sclk_high)
598 return;
599
600 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
601 }
602
rs780_dpm_enable(struct radeon_device * rdev)603 int rs780_dpm_enable(struct radeon_device *rdev)
604 {
605 struct igp_power_info *pi = rs780_get_pi(rdev);
606 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
607 int ret;
608
609 rs780_get_pm_mode_parameters(rdev);
610 rs780_disable_vbios_powersaving(rdev);
611
612 if (r600_dynamicpm_enabled(rdev))
613 return -EINVAL;
614 ret = rs780_initialize_dpm_parameters(rdev, boot_ps);
615 if (ret)
616 return ret;
617 rs780_start_dpm(rdev);
618
619 rs780_preset_ranges_slow_clk_fbdiv_en(rdev);
620 rs780_preset_starting_fbdiv(rdev);
621 if (pi->voltage_control)
622 rs780_voltage_scaling_init(rdev);
623 rs780_clk_scaling_enable(rdev, true);
624 rs780_set_engine_clock_sc(rdev);
625 rs780_set_engine_clock_wfc(rdev);
626 rs780_program_at(rdev);
627 rs780_set_engine_clock_tdc(rdev);
628 rs780_set_engine_clock_ssc(rdev);
629
630 if (pi->gfx_clock_gating)
631 r600_gfx_clockgating_enable(rdev, true);
632
633 return 0;
634 }
635
rs780_dpm_disable(struct radeon_device * rdev)636 void rs780_dpm_disable(struct radeon_device *rdev)
637 {
638 struct igp_power_info *pi = rs780_get_pi(rdev);
639
640 r600_dynamicpm_enable(rdev, false);
641
642 rs780_clk_scaling_enable(rdev, false);
643 rs780_voltage_scaling_enable(rdev, false);
644
645 if (pi->gfx_clock_gating)
646 r600_gfx_clockgating_enable(rdev, false);
647
648 if (rdev->irq.installed &&
649 (rdev->pm.int_thermal_type == THERMAL_TYPE_RV6XX)) {
650 rdev->irq.dpm_thermal = false;
651 radeon_irq_set(rdev);
652 }
653 }
654
rs780_dpm_set_power_state(struct radeon_device * rdev)655 int rs780_dpm_set_power_state(struct radeon_device *rdev)
656 {
657 struct igp_power_info *pi = rs780_get_pi(rdev);
658 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
659 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
660 int ret;
661
662 rs780_get_pm_mode_parameters(rdev);
663
664 rs780_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
665
666 if (pi->voltage_control) {
667 rs780_force_voltage(rdev, pi->max_voltage);
668 mdelay(5);
669 }
670
671 ret = rs780_set_engine_clock_scaling(rdev, new_ps, old_ps);
672 if (ret)
673 return ret;
674 rs780_set_engine_clock_spc(rdev, new_ps, old_ps);
675
676 rs780_activate_engine_clk_scaling(rdev, new_ps, old_ps);
677
678 if (pi->voltage_control)
679 rs780_enable_voltage_scaling(rdev, new_ps);
680
681 rs780_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
682
683 return 0;
684 }
685
rs780_dpm_setup_asic(struct radeon_device * rdev)686 void rs780_dpm_setup_asic(struct radeon_device *rdev)
687 {
688
689 }
690
rs780_dpm_display_configuration_changed(struct radeon_device * rdev)691 void rs780_dpm_display_configuration_changed(struct radeon_device *rdev)
692 {
693 rs780_get_pm_mode_parameters(rdev);
694 rs780_program_at(rdev);
695 }
696
697 union igp_info {
698 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
699 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
700 };
701
702 union power_info {
703 struct _ATOM_POWERPLAY_INFO info;
704 struct _ATOM_POWERPLAY_INFO_V2 info_2;
705 struct _ATOM_POWERPLAY_INFO_V3 info_3;
706 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
707 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
708 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
709 };
710
711 union pplib_clock_info {
712 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
713 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
714 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
715 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
716 };
717
718 union pplib_power_state {
719 struct _ATOM_PPLIB_STATE v1;
720 struct _ATOM_PPLIB_STATE_V2 v2;
721 };
722
rs780_parse_pplib_non_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)723 static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
724 struct radeon_ps *rps,
725 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
726 u8 table_rev)
727 {
728 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
729 rps->class = le16_to_cpu(non_clock_info->usClassification);
730 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
731
732 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
733 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
734 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
735 } else {
736 rps->vclk = 0;
737 rps->dclk = 0;
738 }
739
740 if (r600_is_uvd_state(rps->class, rps->class2)) {
741 if ((rps->vclk == 0) || (rps->dclk == 0)) {
742 rps->vclk = RS780_DEFAULT_VCLK_FREQ;
743 rps->dclk = RS780_DEFAULT_DCLK_FREQ;
744 }
745 }
746
747 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
748 rdev->pm.dpm.boot_ps = rps;
749 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
750 rdev->pm.dpm.uvd_ps = rps;
751 }
752
rs780_parse_pplib_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,union pplib_clock_info * clock_info)753 static void rs780_parse_pplib_clock_info(struct radeon_device *rdev,
754 struct radeon_ps *rps,
755 union pplib_clock_info *clock_info)
756 {
757 struct igp_ps *ps = rs780_get_ps(rps);
758 u32 sclk;
759
760 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
761 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
762 ps->sclk_low = sclk;
763 sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow);
764 sclk |= clock_info->rs780.ucHighEngineClockHigh << 16;
765 ps->sclk_high = sclk;
766 switch (le16_to_cpu(clock_info->rs780.usVDDC)) {
767 case ATOM_PPLIB_RS780_VOLTAGE_NONE:
768 default:
769 ps->min_voltage = RS780_VDDC_LEVEL_UNKNOWN;
770 ps->max_voltage = RS780_VDDC_LEVEL_UNKNOWN;
771 break;
772 case ATOM_PPLIB_RS780_VOLTAGE_LOW:
773 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
774 ps->max_voltage = RS780_VDDC_LEVEL_LOW;
775 break;
776 case ATOM_PPLIB_RS780_VOLTAGE_HIGH:
777 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
778 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
779 break;
780 case ATOM_PPLIB_RS780_VOLTAGE_VARIABLE:
781 ps->min_voltage = RS780_VDDC_LEVEL_LOW;
782 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
783 break;
784 }
785 ps->flags = le32_to_cpu(clock_info->rs780.ulFlags);
786
787 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
788 ps->sclk_low = rdev->clock.default_sclk;
789 ps->sclk_high = rdev->clock.default_sclk;
790 ps->min_voltage = RS780_VDDC_LEVEL_HIGH;
791 ps->max_voltage = RS780_VDDC_LEVEL_HIGH;
792 }
793 }
794
rs780_parse_power_table(struct radeon_device * rdev)795 static int rs780_parse_power_table(struct radeon_device *rdev)
796 {
797 struct radeon_mode_info *mode_info = &rdev->mode_info;
798 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
799 union pplib_power_state *power_state;
800 int i;
801 union pplib_clock_info *clock_info;
802 union power_info *power_info;
803 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
804 u16 data_offset;
805 u8 frev, crev;
806 struct igp_ps *ps;
807
808 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
809 &frev, &crev, &data_offset))
810 return -EINVAL;
811 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
812
813 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
814 sizeof(struct radeon_ps),
815 GFP_KERNEL);
816 if (!rdev->pm.dpm.ps)
817 return -ENOMEM;
818
819 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
820 power_state = (union pplib_power_state *)
821 (mode_info->atom_context->bios + data_offset +
822 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
823 i * power_info->pplib.ucStateEntrySize);
824 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
825 (mode_info->atom_context->bios + data_offset +
826 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
827 (power_state->v1.ucNonClockStateIndex *
828 power_info->pplib.ucNonClockSize));
829 if (power_info->pplib.ucStateEntrySize - 1) {
830 clock_info = (union pplib_clock_info *)
831 (mode_info->atom_context->bios + data_offset +
832 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
833 (power_state->v1.ucClockStateIndices[0] *
834 power_info->pplib.ucClockInfoSize));
835 ps = kzalloc(sizeof(struct igp_ps), GFP_KERNEL);
836 if (ps == NULL) {
837 kfree(rdev->pm.dpm.ps);
838 return -ENOMEM;
839 }
840 rdev->pm.dpm.ps[i].ps_priv = ps;
841 rs780_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
842 non_clock_info,
843 power_info->pplib.ucNonClockSize);
844 rs780_parse_pplib_clock_info(rdev,
845 &rdev->pm.dpm.ps[i],
846 clock_info);
847 }
848 }
849 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
850 return 0;
851 }
852
rs780_dpm_init(struct radeon_device * rdev)853 int rs780_dpm_init(struct radeon_device *rdev)
854 {
855 struct igp_power_info *pi;
856 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
857 union igp_info *info;
858 u16 data_offset;
859 u8 frev, crev;
860 int ret;
861
862 pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);
863 if (pi == NULL)
864 return -ENOMEM;
865 rdev->pm.dpm.priv = pi;
866
867 ret = r600_get_platform_caps(rdev);
868 if (ret)
869 return ret;
870
871 ret = rs780_parse_power_table(rdev);
872 if (ret)
873 return ret;
874
875 pi->voltage_control = false;
876 pi->gfx_clock_gating = true;
877
878 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
879 &frev, &crev, &data_offset)) {
880 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
881
882 /* Get various system informations from bios */
883 switch (crev) {
884 case 1:
885 pi->num_of_cycles_in_period =
886 info->info.ucNumberOfCyclesInPeriod;
887 pi->num_of_cycles_in_period |=
888 info->info.ucNumberOfCyclesInPeriodHi << 8;
889 pi->invert_pwm_required =
890 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
891 pi->boot_voltage = info->info.ucStartingPWM_HighTime;
892 pi->max_voltage = info->info.ucMaxNBVoltage;
893 pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;
894 pi->min_voltage = info->info.ucMinNBVoltage;
895 pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;
896 pi->inter_voltage_low =
897 le16_to_cpu(info->info.usInterNBVoltageLow);
898 pi->inter_voltage_high =
899 le16_to_cpu(info->info.usInterNBVoltageHigh);
900 pi->voltage_control = true;
901 pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;
902 break;
903 case 2:
904 pi->num_of_cycles_in_period =
905 le16_to_cpu(info->info_2.usNumberOfCyclesInPeriod);
906 pi->invert_pwm_required =
907 (pi->num_of_cycles_in_period & 0x8000) ? true : false;
908 pi->boot_voltage =
909 le16_to_cpu(info->info_2.usBootUpNBVoltage);
910 pi->max_voltage =
911 le16_to_cpu(info->info_2.usMaxNBVoltage);
912 pi->min_voltage =
913 le16_to_cpu(info->info_2.usMinNBVoltage);
914 pi->system_config =
915 le32_to_cpu(info->info_2.ulSystemConfig);
916 pi->pwm_voltage_control =
917 (pi->system_config & 0x4) ? true : false;
918 pi->voltage_control = true;
919 pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);
920 break;
921 default:
922 DRM_ERROR("No integrated system info for your GPU\n");
923 return -EINVAL;
924 }
925 if (pi->min_voltage > pi->max_voltage)
926 pi->voltage_control = false;
927 if (pi->pwm_voltage_control) {
928 if ((pi->num_of_cycles_in_period == 0) ||
929 (pi->max_voltage == 0) ||
930 (pi->min_voltage == 0))
931 pi->voltage_control = false;
932 } else {
933 if ((pi->num_of_cycles_in_period == 0) ||
934 (pi->max_voltage == 0))
935 pi->voltage_control = false;
936 }
937
938 return 0;
939 }
940 radeon_dpm_fini(rdev);
941 return -EINVAL;
942 }
943
rs780_dpm_print_power_state(struct radeon_device * rdev,struct radeon_ps * rps)944 void rs780_dpm_print_power_state(struct radeon_device *rdev,
945 struct radeon_ps *rps)
946 {
947 struct igp_ps *ps = rs780_get_ps(rps);
948
949 r600_dpm_print_class_info(rps->class, rps->class2);
950 r600_dpm_print_cap_info(rps->caps);
951 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
952 printk("\t\tpower level 0 sclk: %u vddc_index: %d\n",
953 ps->sclk_low, ps->min_voltage);
954 printk("\t\tpower level 1 sclk: %u vddc_index: %d\n",
955 ps->sclk_high, ps->max_voltage);
956 r600_dpm_print_ps_status(rdev, rps);
957 }
958
rs780_dpm_fini(struct radeon_device * rdev)959 void rs780_dpm_fini(struct radeon_device *rdev)
960 {
961 int i;
962
963 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
964 kfree(rdev->pm.dpm.ps[i].ps_priv);
965 }
966 kfree(rdev->pm.dpm.ps);
967 kfree(rdev->pm.dpm.priv);
968 }
969
rs780_dpm_get_sclk(struct radeon_device * rdev,bool low)970 u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low)
971 {
972 struct igp_ps *requested_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
973
974 if (low)
975 return requested_state->sclk_low;
976 else
977 return requested_state->sclk_high;
978 }
979
rs780_dpm_get_mclk(struct radeon_device * rdev,bool low)980 u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low)
981 {
982 struct igp_power_info *pi = rs780_get_pi(rdev);
983
984 return pi->bootup_uma_clk;
985 }
986
987 #ifdef CONFIG_DEBUG_FS
rs780_dpm_debugfs_print_current_performance_level(struct radeon_device * rdev,struct seq_file * m)988 void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
989 struct seq_file *m)
990 {
991 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
992 struct igp_ps *ps = rs780_get_ps(rps);
993 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
994 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
995 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
996 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
997 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
998 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
999 (post_div * ref_div);
1000
1001 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1002
1003 /* guess based on the current sclk */
1004 if (sclk < (ps->sclk_low + 500))
1005 seq_printf(m, "power level 0 sclk: %u vddc_index: %d\n",
1006 ps->sclk_low, ps->min_voltage);
1007 else
1008 seq_printf(m, "power level 1 sclk: %u vddc_index: %d\n",
1009 ps->sclk_high, ps->max_voltage);
1010 }
1011 #endif
1012
1013 /* get the current sclk in 10 khz units */
rs780_dpm_get_current_sclk(struct radeon_device * rdev)1014 u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev)
1015 {
1016 u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
1017 u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1018 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1;
1019 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 +
1020 ((func_cntl & SPLL_SW_LOLEN_MASK) >> SPLL_SW_LOLEN_SHIFT) + 1;
1021 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /
1022 (post_div * ref_div);
1023
1024 return sclk;
1025 }
1026
1027 /* get the current mclk in 10 khz units */
rs780_dpm_get_current_mclk(struct radeon_device * rdev)1028 u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev)
1029 {
1030 struct igp_power_info *pi = rs780_get_pi(rdev);
1031
1032 return pi->bootup_uma_clk;
1033 }
1034
rs780_dpm_force_performance_level(struct radeon_device * rdev,enum radeon_dpm_forced_level level)1035 int rs780_dpm_force_performance_level(struct radeon_device *rdev,
1036 enum radeon_dpm_forced_level level)
1037 {
1038 struct igp_power_info *pi = rs780_get_pi(rdev);
1039 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1040 struct igp_ps *ps = rs780_get_ps(rps);
1041 struct atom_clock_dividers dividers;
1042 int ret;
1043
1044 rs780_clk_scaling_enable(rdev, false);
1045 rs780_voltage_scaling_enable(rdev, false);
1046
1047 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1048 if (pi->voltage_control)
1049 rs780_force_voltage(rdev, pi->max_voltage);
1050
1051 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1052 ps->sclk_high, false, ÷rs);
1053 if (ret)
1054 return ret;
1055
1056 rs780_force_fbdiv(rdev, dividers.fb_div);
1057 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1058 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1059 ps->sclk_low, false, ÷rs);
1060 if (ret)
1061 return ret;
1062
1063 rs780_force_fbdiv(rdev, dividers.fb_div);
1064
1065 if (pi->voltage_control)
1066 rs780_force_voltage(rdev, pi->min_voltage);
1067 } else {
1068 if (pi->voltage_control)
1069 rs780_force_voltage(rdev, pi->max_voltage);
1070
1071 if (ps->sclk_high != ps->sclk_low) {
1072 WREG32_P(FVTHROT_FBDIV_REG1, 0, ~FORCE_FEEDBACK_DIV);
1073 rs780_clk_scaling_enable(rdev, true);
1074 }
1075
1076 if (pi->voltage_control) {
1077 rs780_voltage_scaling_enable(rdev, true);
1078 rs780_enable_voltage_scaling(rdev, rps);
1079 }
1080 }
1081
1082 rdev->pm.dpm.forced_level = level;
1083
1084 return 0;
1085 }
1086