1 //===- Mips16InstrInfo.cpp - Mips16 Instruction Information ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Mips16 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "Mips16InstrInfo.h" 14 #include "llvm/ADT/BitVector.h" 15 #include "llvm/CodeGen/MachineBasicBlock.h" 16 #include "llvm/CodeGen/MachineFrameInfo.h" 17 #include "llvm/CodeGen/MachineFunction.h" 18 #include "llvm/CodeGen/MachineInstr.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineMemOperand.h" 21 #include "llvm/CodeGen/MachineOperand.h" 22 #include "llvm/CodeGen/RegisterScavenging.h" 23 #include "llvm/CodeGen/TargetRegisterInfo.h" 24 #include "llvm/IR/DebugLoc.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MathExtras.h" 27 #include <cassert> 28 #include <cctype> 29 #include <cstdint> 30 #include <cstdlib> 31 #include <cstring> 32 #include <iterator> 33 #include <vector> 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "mips16-instrinfo" 38 39 Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI) 40 : MipsInstrInfo(STI, Mips::Bimm16) {} 41 42 const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const { 43 return RI; 44 } 45 46 /// isLoadFromStackSlot - If the specified machine instruction is a direct 47 /// load from a stack slot, return the virtual or physical register number of 48 /// the destination along with the FrameIndex of the loaded stack slot. If 49 /// not, return 0. This predicate must return 0 if the instruction has 50 /// any side effects other than loading from the stack slot. 51 Register Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 52 int &FrameIndex) const { 53 return 0; 54 } 55 56 /// isStoreToStackSlot - If the specified machine instruction is a direct 57 /// store to a stack slot, return the virtual or physical register number of 58 /// the source reg along with the FrameIndex of the loaded stack slot. If 59 /// not, return 0. This predicate must return 0 if the instruction has 60 /// any side effects other than storing to the stack slot. 61 Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI, 62 int &FrameIndex) const { 63 return 0; 64 } 65 66 void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 67 MachineBasicBlock::iterator I, 68 const DebugLoc &DL, MCRegister DestReg, 69 MCRegister SrcReg, bool KillSrc, 70 bool RenamableDest, bool RenamableSrc) const { 71 unsigned Opc = 0; 72 73 if (Mips::CPU16RegsRegClass.contains(DestReg) && 74 Mips::GPR32RegClass.contains(SrcReg)) 75 Opc = Mips::MoveR3216; 76 else if (Mips::GPR32RegClass.contains(DestReg) && 77 Mips::CPU16RegsRegClass.contains(SrcReg)) 78 Opc = Mips::Move32R16; 79 else if ((SrcReg == Mips::HI0) && 80 (Mips::CPU16RegsRegClass.contains(DestReg))) 81 Opc = Mips::Mfhi16, SrcReg = 0; 82 else if ((SrcReg == Mips::LO0) && 83 (Mips::CPU16RegsRegClass.contains(DestReg))) 84 Opc = Mips::Mflo16, SrcReg = 0; 85 86 assert(Opc && "Cannot copy registers"); 87 88 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 89 90 if (DestReg) 91 MIB.addReg(DestReg, RegState::Define); 92 93 if (SrcReg) 94 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 95 } 96 97 std::optional<DestSourcePair> 98 Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { 99 if (MI.isMoveReg()) 100 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; 101 return std::nullopt; 102 } 103 104 void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, 105 MachineBasicBlock::iterator I, 106 Register SrcReg, bool isKill, int FI, 107 const TargetRegisterClass *RC, 108 const TargetRegisterInfo *TRI, 109 int64_t Offset, 110 MachineInstr::MIFlag Flags) const { 111 DebugLoc DL; 112 if (I != MBB.end()) DL = I->getDebugLoc(); 113 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 114 unsigned Opc = 0; 115 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 116 Opc = Mips::SwRxSpImmX16; 117 assert(Opc && "Register class not handled!"); 118 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)). 119 addFrameIndex(FI).addImm(Offset) 120 .addMemOperand(MMO); 121 } 122 123 void Mips16InstrInfo::loadRegFromStack( 124 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, 125 int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 126 int64_t Offset, MachineInstr::MIFlag Flags) const { 127 DebugLoc DL; 128 if (I != MBB.end()) DL = I->getDebugLoc(); 129 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 130 unsigned Opc = 0; 131 132 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 133 Opc = Mips::LwRxSpImmX16; 134 assert(Opc && "Register class not handled!"); 135 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) 136 .addMemOperand(MMO); 137 } 138 139 bool Mips16InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 140 MachineBasicBlock &MBB = *MI.getParent(); 141 switch (MI.getDesc().getOpcode()) { 142 default: 143 return false; 144 case Mips::RetRA16: 145 ExpandRetRA16(MBB, MI, Mips::JrcRa16); 146 break; 147 } 148 149 MBB.erase(MI.getIterator()); 150 return true; 151 } 152 153 /// GetOppositeBranchOpc - Return the inverse of the specified 154 /// opcode, e.g. turning BEQ to BNE. 155 unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const { 156 switch (Opc) { 157 case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16; 158 case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16; 159 case Mips::BeqzRxImm16: return Mips::BnezRxImm16; 160 case Mips::BnezRxImm16: return Mips::BeqzRxImm16; 161 case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16; 162 case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16; 163 case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16; 164 case Mips::Btnez16: return Mips::Bteqz16; 165 case Mips::BtnezX16: return Mips::BteqzX16; 166 case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16; 167 case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16; 168 case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16; 169 case Mips::Bteqz16: return Mips::Btnez16; 170 case Mips::BteqzX16: return Mips::BtnezX16; 171 case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16; 172 case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16; 173 case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16; 174 case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16; 175 case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16; 176 case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16; 177 } 178 llvm_unreachable("Illegal opcode!"); 179 } 180 181 static void addSaveRestoreRegs(MachineInstrBuilder &MIB, 182 ArrayRef<CalleeSavedInfo> CSI, 183 unsigned Flags = 0) { 184 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 185 // Add the callee-saved register as live-in. Do not add if the register is 186 // RA and return address is taken, because it has already been added in 187 // method MipsTargetLowering::lowerRETURNADDR. 188 // It's killed at the spill, unless the register is RA and return address 189 // is taken. 190 Register Reg = CSI[e-i-1].getReg(); 191 switch (Reg) { 192 case Mips::RA: 193 case Mips::S0: 194 case Mips::S1: 195 MIB.addReg(Reg, Flags); 196 break; 197 case Mips::S2: 198 break; 199 default: 200 llvm_unreachable("unexpected mips16 callee saved register"); 201 202 } 203 } 204 } 205 206 // Adjust SP by FrameSize bytes. Save RA, S0, S1 207 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, 208 MachineBasicBlock &MBB, 209 MachineBasicBlock::iterator I) const { 210 DebugLoc DL; 211 MachineFunction &MF = *MBB.getParent(); 212 MachineFrameInfo &MFI = MF.getFrameInfo(); 213 const BitVector Reserved = RI.getReservedRegs(MF); 214 bool SaveS2 = Reserved[Mips::S2]; 215 MachineInstrBuilder MIB; 216 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; 217 MIB = BuildMI(MBB, I, DL, get(Opc)); 218 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); 219 addSaveRestoreRegs(MIB, CSI); 220 if (SaveS2) 221 MIB.addReg(Mips::S2); 222 if (isUInt<11>(FrameSize)) 223 MIB.addImm(FrameSize); 224 else { 225 int Base = 2040; // should create template function like isUInt that 226 // returns largest possible n bit unsigned integer 227 int64_t Remainder = FrameSize - Base; 228 MIB.addImm(Base); 229 if (isInt<16>(-Remainder)) 230 BuildAddiuSpImm(MBB, I, -Remainder); 231 else 232 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1); 233 } 234 } 235 236 // Adjust SP by FrameSize bytes. Restore RA, S0, S1 237 void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, 238 MachineBasicBlock &MBB, 239 MachineBasicBlock::iterator I) const { 240 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); 241 MachineFunction *MF = MBB.getParent(); 242 MachineFrameInfo &MFI = MF->getFrameInfo(); 243 const BitVector Reserved = RI.getReservedRegs(*MF); 244 bool SaveS2 = Reserved[Mips::S2]; 245 MachineInstrBuilder MIB; 246 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? 247 Mips::Restore16:Mips::RestoreX16; 248 249 if (!isUInt<11>(FrameSize)) { 250 unsigned Base = 2040; 251 int64_t Remainder = FrameSize - Base; 252 FrameSize = Base; // should create template function like isUInt that 253 // returns largest possible n bit unsigned integer 254 255 if (isInt<16>(Remainder)) 256 BuildAddiuSpImm(MBB, I, Remainder); 257 else 258 adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1); 259 } 260 MIB = BuildMI(MBB, I, DL, get(Opc)); 261 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); 262 addSaveRestoreRegs(MIB, CSI, RegState::Define); 263 if (SaveS2) 264 MIB.addReg(Mips::S2, RegState::Define); 265 MIB.addImm(FrameSize); 266 } 267 268 // Adjust SP by Amount bytes where bytes can be up to 32bit number. 269 // This can only be called at times that we know that there is at least one free 270 // register. 271 // This is clearly safe at prologue and epilogue. 272 void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, 273 MachineBasicBlock &MBB, 274 MachineBasicBlock::iterator I, 275 unsigned Reg1, unsigned Reg2) const { 276 DebugLoc DL; 277 // 278 // li reg1, constant 279 // move reg2, sp 280 // add reg1, reg1, reg2 281 // move sp, reg1 282 // 283 // 284 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1); 285 MIB1.addImm(Amount).addImm(-1); 286 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2); 287 MIB2.addReg(Mips::SP, RegState::Kill); 288 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); 289 MIB3.addReg(Reg1); 290 MIB3.addReg(Reg2, RegState::Kill); 291 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16), 292 Mips::SP); 293 MIB4.addReg(Reg1, RegState::Kill); 294 } 295 296 void Mips16InstrInfo::adjustStackPtrBigUnrestricted( 297 unsigned SP, int64_t Amount, MachineBasicBlock &MBB, 298 MachineBasicBlock::iterator I) const { 299 llvm_unreachable("adjust stack pointer amount exceeded"); 300 } 301 302 /// Adjust SP by Amount bytes. 303 void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 304 MachineBasicBlock &MBB, 305 MachineBasicBlock::iterator I) const { 306 if (Amount == 0) 307 return; 308 309 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16> 310 BuildAddiuSpImm(MBB, I, Amount); 311 else 312 adjustStackPtrBigUnrestricted(SP, Amount, MBB, I); 313 } 314 315 /// This function generates the sequence of instructions needed to get the 316 /// result of adding register REG and immediate IMM. 317 unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm, 318 MachineBasicBlock &MBB, 319 MachineBasicBlock::iterator II, 320 const DebugLoc &DL, 321 unsigned &NewImm) const { 322 // 323 // given original instruction is: 324 // Instr rx, T[offset] where offset is too big. 325 // 326 // lo = offset & 0xFFFF 327 // hi = ((offset >> 16) + (lo >> 15)) & 0xFFFF; 328 // 329 // let T = temporary register 330 // li T, hi 331 // shl T, 16 332 // add T, Rx, T 333 // 334 RegScavenger rs; 335 int32_t lo = Imm & 0xFFFF; 336 NewImm = lo; 337 int Reg =0; 338 int SpReg = 0; 339 340 rs.enterBasicBlockEnd(MBB); 341 rs.backward(std::next(II)); 342 // 343 // We need to know which registers can be used, in the case where there 344 // are not enough free registers. We exclude all registers that 345 // are used in the instruction that we are helping. 346 // // Consider all allocatable registers in the register class initially 347 BitVector Candidates = 348 RI.getAllocatableSet 349 (*II->getParent()->getParent(), &Mips::CPU16RegsRegClass); 350 // Exclude all the registers being used by the instruction. 351 for (MachineOperand &MO : II->operands()) { 352 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() && 353 !MO.getReg().isVirtual()) 354 Candidates.reset(MO.getReg()); 355 } 356 357 // If the same register was used and defined in an instruction, then 358 // it will not be in the list of candidates. 359 // 360 // we need to analyze the instruction that we are helping. 361 // we need to know if it defines register x but register x is not 362 // present as an operand of the instruction. this tells 363 // whether the register is live before the instruction. if it's not 364 // then we don't need to save it in case there are no free registers. 365 int DefReg = 0; 366 for (MachineOperand &MO : II->operands()) { 367 if (MO.isReg() && MO.isDef()) { 368 DefReg = MO.getReg(); 369 break; 370 } 371 } 372 373 BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass); 374 Available &= Candidates; 375 // 376 // we use T0 for the first register, if we need to save something away. 377 // we use T1 for the second register, if we need to save something away. 378 // 379 unsigned FirstRegSaved =0, SecondRegSaved=0; 380 unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0; 381 382 Reg = Available.find_first(); 383 384 if (Reg == -1) { 385 Reg = Candidates.find_first(); 386 Candidates.reset(Reg); 387 if (DefReg != Reg) { 388 FirstRegSaved = Reg; 389 FirstRegSavedTo = Mips::T0; 390 copyPhysReg(MBB, II, DL, FirstRegSavedTo, FirstRegSaved, true); 391 } 392 } 393 else 394 Available.reset(Reg); 395 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1); 396 NewImm = 0; 397 if (FrameReg == Mips::SP) { 398 SpReg = Available.find_first(); 399 if (SpReg == -1) { 400 SpReg = Candidates.find_first(); 401 // Candidates.reset(SpReg); // not really needed 402 if (DefReg!= SpReg) { 403 SecondRegSaved = SpReg; 404 SecondRegSavedTo = Mips::T1; 405 } 406 if (SecondRegSaved) 407 copyPhysReg(MBB, II, DL, SecondRegSavedTo, SecondRegSaved, true); 408 } 409 else 410 Available.reset(SpReg); 411 copyPhysReg(MBB, II, DL, SpReg, Mips::SP, false); 412 BuildMI(MBB, II, DL, get(Mips::AdduRxRyRz16), Reg) 413 .addReg(SpReg, RegState::Kill) 414 .addReg(Reg); 415 } 416 else 417 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg) 418 .addReg(Reg, RegState::Kill); 419 if (FirstRegSaved || SecondRegSaved) { 420 II = std::next(II); 421 if (FirstRegSaved) 422 copyPhysReg(MBB, II, DL, FirstRegSaved, FirstRegSavedTo, true); 423 if (SecondRegSaved) 424 copyPhysReg(MBB, II, DL, SecondRegSaved, SecondRegSavedTo, true); 425 } 426 return Reg; 427 } 428 429 unsigned Mips16InstrInfo::getAnalyzableBrOpc(unsigned Opc) const { 430 return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 || 431 Opc == Mips::Bimm16 || 432 Opc == Mips::Bteqz16 || Opc == Mips::Btnez16 || 433 Opc == Mips::BeqzRxImm16 || Opc == Mips::BnezRxImm16 || 434 Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 || 435 Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 || 436 Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 || 437 Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 || 438 Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 || 439 Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 || 440 Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 || 441 Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0; 442 } 443 444 void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB, 445 MachineBasicBlock::iterator I, 446 unsigned Opc) const { 447 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); 448 } 449 450 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const { 451 if (validSpImm8(Imm)) 452 return get(Mips::AddiuSpImm16); 453 else 454 return get(Mips::AddiuSpImmX16); 455 } 456 457 void Mips16InstrInfo::BuildAddiuSpImm 458 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const { 459 DebugLoc DL; 460 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm); 461 } 462 463 const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) { 464 return new Mips16InstrInfo(STI); 465 } 466 467 bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg, 468 int64_t Amount) { 469 switch (Opcode) { 470 case Mips::LbRxRyOffMemX16: 471 case Mips::LbuRxRyOffMemX16: 472 case Mips::LhRxRyOffMemX16: 473 case Mips::LhuRxRyOffMemX16: 474 case Mips::SbRxRyOffMemX16: 475 case Mips::ShRxRyOffMemX16: 476 case Mips::LwRxRyOffMemX16: 477 case Mips::SwRxRyOffMemX16: 478 case Mips::SwRxSpImmX16: 479 case Mips::LwRxSpImmX16: 480 return isInt<16>(Amount); 481 case Mips::AddiuRxRyOffMemX16: 482 if ((Reg == Mips::PC) || (Reg == Mips::SP)) 483 return isInt<16>(Amount); 484 return isInt<15>(Amount); 485 } 486 llvm_unreachable("unexpected Opcode in validImmediate"); 487 } 488