1 ///===- FastISelEmitter.cpp - Generate an instruction selector ------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend emits code for use by the "fast" instruction 10 // selection algorithm. See the comments at the top of 11 // lib/CodeGen/SelectionDAG/FastISel.cpp for background. 12 // 13 // This file scans through the target's tablegen instruction-info files 14 // and extracts instructions with obvious-looking patterns, and it emits 15 // code to look up these instructions by type and operator. 16 // 17 //===----------------------------------------------------------------------===// 18 19 #include "Common/CodeGenDAGPatterns.h" 20 #include "Common/CodeGenInstruction.h" 21 #include "Common/CodeGenRegisters.h" 22 #include "Common/CodeGenTarget.h" 23 #include "Common/InfoByHwMode.h" 24 #include "llvm/ADT/StringSwitch.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/TableGen/Error.h" 27 #include "llvm/TableGen/Record.h" 28 #include "llvm/TableGen/TableGenBackend.h" 29 #include <set> 30 #include <utility> 31 using namespace llvm; 32 33 /// InstructionMemo - This class holds additional information about an 34 /// instruction needed to emit code for it. 35 /// 36 namespace { 37 struct InstructionMemo { 38 std::string Name; 39 const CodeGenRegisterClass *RC; 40 std::string SubRegNo; 41 std::vector<std::string> PhysRegs; 42 std::string PredicateCheck; 43 44 InstructionMemo(StringRef Name, const CodeGenRegisterClass *RC, 45 std::string SubRegNo, std::vector<std::string> PhysRegs, 46 std::string PredicateCheck) 47 : Name(Name), RC(RC), SubRegNo(std::move(SubRegNo)), 48 PhysRegs(std::move(PhysRegs)), 49 PredicateCheck(std::move(PredicateCheck)) {} 50 51 // Make sure we do not copy InstructionMemo. 52 InstructionMemo(const InstructionMemo &Other) = delete; 53 InstructionMemo(InstructionMemo &&Other) = default; 54 }; 55 } // End anonymous namespace 56 57 /// ImmPredicateSet - This uniques predicates (represented as a string) and 58 /// gives them unique (small) integer ID's that start at 0. 59 namespace { 60 class ImmPredicateSet { 61 DenseMap<TreePattern *, unsigned> ImmIDs; 62 std::vector<TreePredicateFn> PredsByName; 63 64 public: 65 unsigned getIDFor(TreePredicateFn Pred) { 66 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; 67 if (Entry == 0) { 68 PredsByName.push_back(Pred); 69 Entry = PredsByName.size(); 70 } 71 return Entry - 1; 72 } 73 74 const TreePredicateFn &getPredicate(unsigned i) { 75 assert(i < PredsByName.size()); 76 return PredsByName[i]; 77 } 78 79 typedef std::vector<TreePredicateFn>::const_iterator iterator; 80 iterator begin() const { return PredsByName.begin(); } 81 iterator end() const { return PredsByName.end(); } 82 }; 83 } // End anonymous namespace 84 85 /// OperandsSignature - This class holds a description of a list of operand 86 /// types. It has utility methods for emitting text based on the operands. 87 /// 88 namespace { 89 struct OperandsSignature { 90 class OpKind { 91 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; 92 char Repr; 93 94 public: 95 OpKind() : Repr(OK_Invalid) {} 96 97 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } 98 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } 99 100 static OpKind getReg() { 101 OpKind K; 102 K.Repr = OK_Reg; 103 return K; 104 } 105 static OpKind getFP() { 106 OpKind K; 107 K.Repr = OK_FP; 108 return K; 109 } 110 static OpKind getImm(unsigned V) { 111 assert((unsigned)OK_Imm + V < 128 && 112 "Too many integer predicates for the 'Repr' char"); 113 OpKind K; 114 K.Repr = OK_Imm + V; 115 return K; 116 } 117 118 bool isReg() const { return Repr == OK_Reg; } 119 bool isFP() const { return Repr == OK_FP; } 120 bool isImm() const { return Repr >= OK_Imm; } 121 122 unsigned getImmCode() const { 123 assert(isImm()); 124 return Repr - OK_Imm; 125 } 126 127 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 128 bool StripImmCodes) const { 129 if (isReg()) 130 OS << 'r'; 131 else if (isFP()) 132 OS << 'f'; 133 else { 134 OS << 'i'; 135 if (!StripImmCodes) 136 if (unsigned Code = getImmCode()) 137 OS << "_" << ImmPredicates.getPredicate(Code - 1).getFnName(); 138 } 139 } 140 }; 141 142 SmallVector<OpKind, 3> Operands; 143 144 bool operator<(const OperandsSignature &O) const { 145 return Operands < O.Operands; 146 } 147 bool operator==(const OperandsSignature &O) const { 148 return Operands == O.Operands; 149 } 150 151 bool empty() const { return Operands.empty(); } 152 153 bool hasAnyImmediateCodes() const { 154 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 155 if (Operands[i].isImm() && Operands[i].getImmCode() != 0) 156 return true; 157 return false; 158 } 159 160 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced 161 /// to zero. 162 OperandsSignature getWithoutImmCodes() const { 163 OperandsSignature Result; 164 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 165 if (!Operands[i].isImm()) 166 Result.Operands.push_back(Operands[i]); 167 else 168 Result.Operands.push_back(OpKind::getImm(0)); 169 return Result; 170 } 171 172 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { 173 bool EmittedAnything = false; 174 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 175 if (!Operands[i].isImm()) 176 continue; 177 178 unsigned Code = Operands[i].getImmCode(); 179 if (Code == 0) 180 continue; 181 182 if (EmittedAnything) 183 OS << " &&\n "; 184 185 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code - 1); 186 187 // Emit the type check. 188 TreePattern *TP = PredFn.getOrigPatFragRecord(); 189 ValueTypeByHwMode VVT = TP->getTree(0)->getType(0); 190 assert(VVT.isSimple() && 191 "Cannot use variable value types with fast isel"); 192 OS << "VT == " << getEnumName(VVT.getSimple().SimpleTy) << " && "; 193 194 OS << PredFn.getFnName() << "(imm" << i << ')'; 195 EmittedAnything = true; 196 } 197 } 198 199 /// initialize - Examine the given pattern and initialize the contents 200 /// of the Operands array accordingly. Return true if all the operands 201 /// are supported, false otherwise. 202 /// 203 bool initialize(TreePatternNode &InstPatNode, const CodeGenTarget &Target, 204 MVT::SimpleValueType VT, ImmPredicateSet &ImmediatePredicates, 205 const CodeGenRegisterClass *OrigDstRC) { 206 if (InstPatNode.isLeaf()) 207 return false; 208 209 if (InstPatNode.getOperator()->getName() == "imm") { 210 Operands.push_back(OpKind::getImm(0)); 211 return true; 212 } 213 214 if (InstPatNode.getOperator()->getName() == "fpimm") { 215 Operands.push_back(OpKind::getFP()); 216 return true; 217 } 218 219 const CodeGenRegisterClass *DstRC = nullptr; 220 221 for (const TreePatternNode &Op : InstPatNode.children()) { 222 // Handle imm operands specially. 223 if (!Op.isLeaf() && Op.getOperator()->getName() == "imm") { 224 unsigned PredNo = 0; 225 if (!Op.getPredicateCalls().empty()) { 226 TreePredicateFn PredFn = Op.getPredicateCalls()[0].Fn; 227 // If there is more than one predicate weighing in on this operand 228 // then we don't handle it. This doesn't typically happen for 229 // immediates anyway. 230 if (Op.getPredicateCalls().size() > 1 || 231 !PredFn.isImmediatePattern() || PredFn.usesOperands()) 232 return false; 233 // Ignore any instruction with 'FastIselShouldIgnore', these are 234 // not needed and just bloat the fast instruction selector. For 235 // example, X86 doesn't need to generate code to match ADD16ri8 since 236 // ADD16ri will do just fine. 237 const Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); 238 if (Rec->getValueAsBit("FastIselShouldIgnore")) 239 return false; 240 241 PredNo = ImmediatePredicates.getIDFor(PredFn) + 1; 242 } 243 244 Operands.push_back(OpKind::getImm(PredNo)); 245 continue; 246 } 247 248 // For now, filter out any operand with a predicate. 249 // For now, filter out any operand with multiple values. 250 if (!Op.getPredicateCalls().empty() || Op.getNumTypes() != 1) 251 return false; 252 253 if (!Op.isLeaf()) { 254 if (Op.getOperator()->getName() == "fpimm") { 255 Operands.push_back(OpKind::getFP()); 256 continue; 257 } 258 // For now, ignore other non-leaf nodes. 259 return false; 260 } 261 262 assert(Op.hasConcreteType(0) && "Type infererence not done?"); 263 264 // For now, all the operands must have the same type (if they aren't 265 // immediates). Note that this causes us to reject variable sized shifts 266 // on X86. 267 if (Op.getSimpleType(0) != VT) 268 return false; 269 270 const DefInit *OpDI = dyn_cast<DefInit>(Op.getLeafValue()); 271 if (!OpDI) 272 return false; 273 const Record *OpLeafRec = OpDI->getDef(); 274 275 // For now, the only other thing we accept is register operands. 276 const CodeGenRegisterClass *RC = nullptr; 277 if (OpLeafRec->isSubClassOf("RegisterOperand")) 278 OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); 279 if (OpLeafRec->isSubClassOf("RegisterClass")) 280 RC = &Target.getRegisterClass(OpLeafRec); 281 else if (OpLeafRec->isSubClassOf("Register")) 282 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 283 else if (OpLeafRec->isSubClassOf("ValueType")) { 284 RC = OrigDstRC; 285 } else 286 return false; 287 288 // For now, this needs to be a register class of some sort. 289 if (!RC) 290 return false; 291 292 // For now, all the operands must have the same register class or be 293 // a strict subclass of the destination. 294 if (DstRC) { 295 if (DstRC != RC && !DstRC->hasSubClass(RC)) 296 return false; 297 } else 298 DstRC = RC; 299 Operands.push_back(OpKind::getReg()); 300 } 301 return true; 302 } 303 304 void PrintParameters(raw_ostream &OS) const { 305 ListSeparator LS; 306 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 307 OS << LS; 308 if (Operands[i].isReg()) { 309 OS << "unsigned Op" << i; 310 } else if (Operands[i].isImm()) { 311 OS << "uint64_t imm" << i; 312 } else if (Operands[i].isFP()) { 313 OS << "const ConstantFP *f" << i; 314 } else { 315 llvm_unreachable("Unknown operand kind!"); 316 } 317 } 318 } 319 320 void PrintArguments(raw_ostream &OS, 321 const std::vector<std::string> &PR) const { 322 assert(PR.size() == Operands.size()); 323 ListSeparator LS; 324 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 325 if (PR[i] != "") 326 // Implicit physical register operand. 327 continue; 328 329 OS << LS; 330 if (Operands[i].isReg()) { 331 OS << "Op" << i; 332 } else if (Operands[i].isImm()) { 333 OS << "imm" << i; 334 } else if (Operands[i].isFP()) { 335 OS << "f" << i; 336 } else { 337 llvm_unreachable("Unknown operand kind!"); 338 } 339 } 340 } 341 342 void PrintArguments(raw_ostream &OS) const { 343 ListSeparator LS; 344 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 345 OS << LS; 346 if (Operands[i].isReg()) { 347 OS << "Op" << i; 348 } else if (Operands[i].isImm()) { 349 OS << "imm" << i; 350 } else if (Operands[i].isFP()) { 351 OS << "f" << i; 352 } else { 353 llvm_unreachable("Unknown operand kind!"); 354 } 355 } 356 } 357 358 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR, 359 ImmPredicateSet &ImmPredicates, 360 bool StripImmCodes = false) const { 361 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 362 if (PR[i] != "") 363 // Implicit physical register operand. e.g. Instruction::Mul expect to 364 // select to a binary op. On x86, mul may take a single operand with 365 // the other operand being implicit. We must emit something that looks 366 // like a binary instruction except for the very inner fastEmitInst_* 367 // call. 368 continue; 369 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 370 } 371 } 372 373 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, 374 bool StripImmCodes = false) const { 375 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 376 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); 377 } 378 }; 379 } // End anonymous namespace 380 381 namespace { 382 class FastISelMap { 383 // A multimap is needed instead of a "plain" map because the key is 384 // the instruction's complexity (an int) and they are not unique. 385 typedef std::multimap<int, InstructionMemo> PredMap; 386 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; 387 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; 388 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; 389 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> 390 OperandsOpcodeTypeRetPredMap; 391 392 OperandsOpcodeTypeRetPredMap SimplePatterns; 393 394 // This is used to check that there are no duplicate predicates 395 std::set<std::tuple<OperandsSignature, std::string, MVT::SimpleValueType, 396 MVT::SimpleValueType, std::string>> 397 SimplePatternsCheck; 398 399 std::map<OperandsSignature, std::vector<OperandsSignature>> 400 SignaturesWithConstantForms; 401 402 StringRef InstNS; 403 ImmPredicateSet ImmediatePredicates; 404 405 public: 406 explicit FastISelMap(StringRef InstNS); 407 408 void collectPatterns(const CodeGenDAGPatterns &CGP); 409 void printImmediatePredicates(raw_ostream &OS); 410 void printFunctionDefinitions(raw_ostream &OS); 411 412 private: 413 void emitInstructionCode(raw_ostream &OS, const OperandsSignature &Operands, 414 const PredMap &PM, const std::string &RetVTName); 415 }; 416 } // End anonymous namespace 417 418 static std::string getOpcodeName(const Record *Op, 419 const CodeGenDAGPatterns &CGP) { 420 return std::string(CGP.getSDNodeInfo(Op).getEnumName()); 421 } 422 423 static std::string getLegalCName(std::string OpName) { 424 std::string::size_type pos = OpName.find("::"); 425 if (pos != std::string::npos) 426 OpName.replace(pos, 2, "_"); 427 return OpName; 428 } 429 430 FastISelMap::FastISelMap(StringRef instns) : InstNS(instns) {} 431 432 static std::string PhysRegForNode(const TreePatternNode &Op, 433 const CodeGenTarget &Target) { 434 std::string PhysReg; 435 436 if (!Op.isLeaf()) 437 return PhysReg; 438 439 const Record *OpLeafRec = cast<DefInit>(Op.getLeafValue())->getDef(); 440 if (!OpLeafRec->isSubClassOf("Register")) 441 return PhysReg; 442 443 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue()) 444 ->getValue(); 445 PhysReg += "::"; 446 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); 447 return PhysReg; 448 } 449 450 void FastISelMap::collectPatterns(const CodeGenDAGPatterns &CGP) { 451 const CodeGenTarget &Target = CGP.getTargetInfo(); 452 453 // Scan through all the patterns and record the simple ones. 454 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), E = CGP.ptm_end(); 455 I != E; ++I) { 456 const PatternToMatch &Pattern = *I; 457 458 // For now, just look at Instructions, so that we don't have to worry 459 // about emitting multiple instructions for a pattern. 460 TreePatternNode &Dst = Pattern.getDstPattern(); 461 if (Dst.isLeaf()) 462 continue; 463 const Record *Op = Dst.getOperator(); 464 if (!Op->isSubClassOf("Instruction")) 465 continue; 466 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); 467 if (II.Operands.empty()) 468 continue; 469 470 // Allow instructions to be marked as unavailable for FastISel for 471 // certain cases, i.e. an ISA has two 'and' instruction which differ 472 // by what registers they can use but are otherwise identical for 473 // codegen purposes. 474 if (II.FastISelShouldIgnore) 475 continue; 476 477 // For now, ignore multi-instruction patterns. 478 bool MultiInsts = false; 479 for (const TreePatternNode &ChildOp : Dst.children()) { 480 if (ChildOp.isLeaf()) 481 continue; 482 if (ChildOp.getOperator()->isSubClassOf("Instruction")) { 483 MultiInsts = true; 484 break; 485 } 486 } 487 if (MultiInsts) 488 continue; 489 490 // For now, ignore instructions where the first operand is not an 491 // output register. 492 const CodeGenRegisterClass *DstRC = nullptr; 493 std::string SubRegNo; 494 if (Op->getName() != "EXTRACT_SUBREG") { 495 const Record *Op0Rec = II.Operands[0].Rec; 496 if (Op0Rec->isSubClassOf("RegisterOperand")) 497 Op0Rec = Op0Rec->getValueAsDef("RegClass"); 498 if (!Op0Rec->isSubClassOf("RegisterClass")) 499 continue; 500 DstRC = &Target.getRegisterClass(Op0Rec); 501 if (!DstRC) 502 continue; 503 } else { 504 // If this isn't a leaf, then continue since the register classes are 505 // a bit too complicated for now. 506 if (!Dst.getChild(1).isLeaf()) 507 continue; 508 509 const DefInit *SR = dyn_cast<DefInit>(Dst.getChild(1).getLeafValue()); 510 if (SR) 511 SubRegNo = getQualifiedName(SR->getDef()); 512 else 513 SubRegNo = Dst.getChild(1).getLeafValue()->getAsString(); 514 } 515 516 // Inspect the pattern. 517 TreePatternNode &InstPatNode = Pattern.getSrcPattern(); 518 if (InstPatNode.isLeaf()) 519 continue; 520 521 // Ignore multiple result nodes for now. 522 if (InstPatNode.getNumTypes() > 1) 523 continue; 524 525 const Record *InstPatOp = InstPatNode.getOperator(); 526 std::string OpcodeName = getOpcodeName(InstPatOp, CGP); 527 MVT::SimpleValueType RetVT = MVT::isVoid; 528 if (InstPatNode.getNumTypes()) 529 RetVT = InstPatNode.getSimpleType(0); 530 MVT::SimpleValueType VT = RetVT; 531 if (InstPatNode.getNumChildren()) { 532 assert(InstPatNode.getChild(0).getNumTypes() == 1); 533 VT = InstPatNode.getChild(0).getSimpleType(0); 534 } 535 536 // For now, filter out any instructions with predicates. 537 if (!InstPatNode.getPredicateCalls().empty()) 538 continue; 539 540 // Check all the operands. 541 OperandsSignature Operands; 542 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates, 543 DstRC)) 544 continue; 545 546 std::vector<std::string> PhysRegInputs; 547 if (InstPatNode.getOperator()->getName() == "imm" || 548 InstPatNode.getOperator()->getName() == "fpimm") 549 PhysRegInputs.push_back(""); 550 else { 551 // Compute the PhysRegs used by the given pattern, and check that 552 // the mapping from the src to dst patterns is simple. 553 bool FoundNonSimplePattern = false; 554 unsigned DstIndex = 0; 555 for (const TreePatternNode &SrcChild : InstPatNode.children()) { 556 std::string PhysReg = PhysRegForNode(SrcChild, Target); 557 if (PhysReg.empty()) { 558 if (DstIndex >= Dst.getNumChildren() || 559 Dst.getChild(DstIndex).getName() != SrcChild.getName()) { 560 FoundNonSimplePattern = true; 561 break; 562 } 563 ++DstIndex; 564 } 565 566 PhysRegInputs.push_back(std::move(PhysReg)); 567 } 568 569 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst.getNumChildren()) 570 FoundNonSimplePattern = true; 571 572 if (FoundNonSimplePattern) 573 continue; 574 } 575 576 // Check if the operands match one of the patterns handled by FastISel. 577 std::string ManglingSuffix; 578 raw_string_ostream SuffixOS(ManglingSuffix); 579 Operands.PrintManglingSuffix(SuffixOS, ImmediatePredicates, true); 580 if (!StringSwitch<bool>(ManglingSuffix) 581 .Cases("", "r", "rr", "ri", "i", "f", true) 582 .Default(false)) 583 continue; 584 585 // Get the predicate that guards this pattern. 586 std::string PredicateCheck = Pattern.getPredicateCheck(); 587 588 // Ok, we found a pattern that we can handle. Remember it. 589 InstructionMemo Memo(Pattern.getDstPattern().getOperator()->getName(), 590 DstRC, std::move(SubRegNo), std::move(PhysRegInputs), 591 PredicateCheck); 592 593 int complexity = Pattern.getPatternComplexity(CGP); 594 595 auto inserted_simple_pattern = SimplePatternsCheck.insert( 596 {Operands, OpcodeName, VT, RetVT, PredicateCheck}); 597 if (!inserted_simple_pattern.second) { 598 PrintFatalError(Pattern.getSrcRecord()->getLoc(), 599 "Duplicate predicate in FastISel table!"); 600 } 601 602 // Note: Instructions with the same complexity will appear in the order 603 // that they are encountered. 604 SimplePatterns[Operands][OpcodeName][VT][RetVT].emplace(complexity, 605 std::move(Memo)); 606 607 // If any of the operands were immediates with predicates on them, strip 608 // them down to a signature that doesn't have predicates so that we can 609 // associate them with the stripped predicate version. 610 if (Operands.hasAnyImmediateCodes()) { 611 SignaturesWithConstantForms[Operands.getWithoutImmCodes()].push_back( 612 Operands); 613 } 614 } 615 } 616 617 void FastISelMap::printImmediatePredicates(raw_ostream &OS) { 618 if (ImmediatePredicates.begin() == ImmediatePredicates.end()) 619 return; 620 621 OS << "\n// FastEmit Immediate Predicate functions.\n"; 622 for (auto ImmediatePredicate : ImmediatePredicates) { 623 OS << "static bool " << ImmediatePredicate.getFnName() 624 << "(int64_t Imm) {\n"; 625 OS << ImmediatePredicate.getImmediatePredicateCode() << "\n}\n"; 626 } 627 628 OS << "\n\n"; 629 } 630 631 void FastISelMap::emitInstructionCode(raw_ostream &OS, 632 const OperandsSignature &Operands, 633 const PredMap &PM, 634 const std::string &RetVTName) { 635 // Emit code for each possible instruction. There may be 636 // multiple if there are subtarget concerns. A reverse iterator 637 // is used to produce the ones with highest complexity first. 638 639 bool OneHadNoPredicate = false; 640 for (PredMap::const_reverse_iterator PI = PM.rbegin(), PE = PM.rend(); 641 PI != PE; ++PI) { 642 const InstructionMemo &Memo = PI->second; 643 std::string PredicateCheck = Memo.PredicateCheck; 644 645 if (PredicateCheck.empty()) { 646 assert(!OneHadNoPredicate && 647 "Multiple instructions match and more than one had " 648 "no predicate!"); 649 OneHadNoPredicate = true; 650 } else { 651 if (OneHadNoPredicate) { 652 PrintFatalError("Multiple instructions match and one with no " 653 "predicate came before one with a predicate! " 654 "name:" + 655 Memo.Name + " predicate: " + PredicateCheck); 656 } 657 OS << " if (" + PredicateCheck + ") {\n"; 658 OS << " "; 659 } 660 661 for (unsigned i = 0; i < Memo.PhysRegs.size(); ++i) { 662 if (Memo.PhysRegs[i] != "") 663 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, " 664 << "TII.get(TargetOpcode::COPY), " << Memo.PhysRegs[i] 665 << ").addReg(Op" << i << ");\n"; 666 } 667 668 OS << " return fastEmitInst_"; 669 if (Memo.SubRegNo.empty()) { 670 Operands.PrintManglingSuffix(OS, Memo.PhysRegs, ImmediatePredicates, 671 true); 672 OS << "(" << InstNS << "::" << Memo.Name << ", "; 673 OS << "&" << InstNS << "::" << Memo.RC->getName() << "RegClass"; 674 if (!Operands.empty()) 675 OS << ", "; 676 Operands.PrintArguments(OS, Memo.PhysRegs); 677 OS << ");\n"; 678 } else { 679 OS << "extractsubreg(" << RetVTName << ", Op0, " << Memo.SubRegNo 680 << ");\n"; 681 } 682 683 if (!PredicateCheck.empty()) { 684 OS << " }\n"; 685 } 686 } 687 // Return 0 if all of the possibilities had predicates but none 688 // were satisfied. 689 if (!OneHadNoPredicate) 690 OS << " return 0;\n"; 691 OS << "}\n"; 692 OS << "\n"; 693 } 694 695 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { 696 // Now emit code for all the patterns that we collected. 697 for (const auto &SimplePattern : SimplePatterns) { 698 const OperandsSignature &Operands = SimplePattern.first; 699 const OpcodeTypeRetPredMap &OTM = SimplePattern.second; 700 701 for (const auto &I : OTM) { 702 const std::string &Opcode = I.first; 703 const TypeRetPredMap &TM = I.second; 704 705 OS << "// FastEmit functions for " << Opcode << ".\n"; 706 OS << "\n"; 707 708 // Emit one function for each opcode,type pair. 709 for (const auto &TI : TM) { 710 MVT::SimpleValueType VT = TI.first; 711 const RetPredMap &RM = TI.second; 712 if (RM.size() != 1) { 713 for (const auto &RI : RM) { 714 MVT::SimpleValueType RetVT = RI.first; 715 const PredMap &PM = RI.second; 716 717 OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" 718 << getLegalCName(std::string(getEnumName(VT))) << "_" 719 << getLegalCName(std::string(getEnumName(RetVT))) << "_"; 720 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 721 OS << "("; 722 Operands.PrintParameters(OS); 723 OS << ") {\n"; 724 725 emitInstructionCode(OS, Operands, PM, 726 std::string(getEnumName(RetVT))); 727 } 728 729 // Emit one function for the type that demultiplexes on return type. 730 OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" 731 << getLegalCName(std::string(getEnumName(VT))) << "_"; 732 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 733 OS << "(MVT RetVT"; 734 if (!Operands.empty()) 735 OS << ", "; 736 Operands.PrintParameters(OS); 737 OS << ") {\nswitch (RetVT.SimpleTy) {\n"; 738 for (const auto &RI : RM) { 739 MVT::SimpleValueType RetVT = RI.first; 740 OS << " case " << getEnumName(RetVT) << ": return fastEmit_" 741 << getLegalCName(Opcode) << "_" 742 << getLegalCName(std::string(getEnumName(VT))) << "_" 743 << getLegalCName(std::string(getEnumName(RetVT))) << "_"; 744 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 745 OS << "("; 746 Operands.PrintArguments(OS); 747 OS << ");\n"; 748 } 749 OS << " default: return 0;\n}\n}\n\n"; 750 751 } else { 752 // Non-variadic return type. 753 OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_" 754 << getLegalCName(std::string(getEnumName(VT))) << "_"; 755 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 756 OS << "(MVT RetVT"; 757 if (!Operands.empty()) 758 OS << ", "; 759 Operands.PrintParameters(OS); 760 OS << ") {\n"; 761 762 OS << " if (RetVT.SimpleTy != " << getEnumName(RM.begin()->first) 763 << ")\n return 0;\n"; 764 765 const PredMap &PM = RM.begin()->second; 766 767 emitInstructionCode(OS, Operands, PM, "RetVT"); 768 } 769 } 770 771 // Emit one function for the opcode that demultiplexes based on the type. 772 OS << "unsigned fastEmit_" << getLegalCName(Opcode) << "_"; 773 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 774 OS << "(MVT VT, MVT RetVT"; 775 if (!Operands.empty()) 776 OS << ", "; 777 Operands.PrintParameters(OS); 778 OS << ") {\n"; 779 OS << " switch (VT.SimpleTy) {\n"; 780 for (const auto &TI : TM) { 781 MVT::SimpleValueType VT = TI.first; 782 std::string TypeName = std::string(getEnumName(VT)); 783 OS << " case " << TypeName << ": return fastEmit_" 784 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; 785 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 786 OS << "(RetVT"; 787 if (!Operands.empty()) 788 OS << ", "; 789 Operands.PrintArguments(OS); 790 OS << ");\n"; 791 } 792 OS << " default: return 0;\n"; 793 OS << " }\n"; 794 OS << "}\n"; 795 OS << "\n"; 796 } 797 798 OS << "// Top-level FastEmit function.\n"; 799 OS << "\n"; 800 801 // Emit one function for the operand signature that demultiplexes based 802 // on opcode and type. 803 OS << "unsigned fastEmit_"; 804 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 805 OS << "(MVT VT, MVT RetVT, unsigned Opcode"; 806 if (!Operands.empty()) 807 OS << ", "; 808 Operands.PrintParameters(OS); 809 OS << ") "; 810 if (!Operands.hasAnyImmediateCodes()) 811 OS << "override "; 812 OS << "{\n"; 813 814 // If there are any forms of this signature available that operate on 815 // constrained forms of the immediate (e.g., 32-bit sext immediate in a 816 // 64-bit operand), check them first. 817 818 std::map<OperandsSignature, std::vector<OperandsSignature>>::iterator MI = 819 SignaturesWithConstantForms.find(Operands); 820 if (MI != SignaturesWithConstantForms.end()) { 821 // Unique any duplicates out of the list. 822 llvm::sort(MI->second); 823 MI->second.erase(llvm::unique(MI->second), MI->second.end()); 824 825 // Check each in order it was seen. It would be nice to have a good 826 // relative ordering between them, but we're not going for optimality 827 // here. 828 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) { 829 OS << " if ("; 830 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates); 831 OS << ")\n if (unsigned Reg = fastEmit_"; 832 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates); 833 OS << "(VT, RetVT, Opcode"; 834 if (!MI->second[i].empty()) 835 OS << ", "; 836 MI->second[i].PrintArguments(OS); 837 OS << "))\n return Reg;\n\n"; 838 } 839 840 // Done with this, remove it. 841 SignaturesWithConstantForms.erase(MI); 842 } 843 844 OS << " switch (Opcode) {\n"; 845 for (const auto &I : OTM) { 846 const std::string &Opcode = I.first; 847 848 OS << " case " << Opcode << ": return fastEmit_" << getLegalCName(Opcode) 849 << "_"; 850 Operands.PrintManglingSuffix(OS, ImmediatePredicates); 851 OS << "(VT, RetVT"; 852 if (!Operands.empty()) 853 OS << ", "; 854 Operands.PrintArguments(OS); 855 OS << ");\n"; 856 } 857 OS << " default: return 0;\n"; 858 OS << " }\n"; 859 OS << "}\n"; 860 OS << "\n"; 861 } 862 863 // TODO: SignaturesWithConstantForms should be empty here. 864 } 865 866 static void EmitFastISel(const RecordKeeper &RK, raw_ostream &OS) { 867 const CodeGenDAGPatterns CGP(RK); 868 const CodeGenTarget &Target = CGP.getTargetInfo(); 869 emitSourceFileHeader("\"Fast\" Instruction Selector for the " + 870 Target.getName().str() + " target", 871 OS); 872 873 // Determine the target's namespace name. 874 StringRef InstNS = Target.getInstNamespace(); 875 assert(!InstNS.empty() && "Can't determine target-specific namespace!"); 876 877 FastISelMap F(InstNS); 878 F.collectPatterns(CGP); 879 F.printImmediatePredicates(OS); 880 F.printFunctionDefinitions(OS); 881 } 882 883 static TableGen::Emitter::Opt X("gen-fast-isel", EmitFastISel, 884 "Generate a \"fast\" instruction selector"); 885