1 /* $NetBSD: amdgpu_polaris10_smumgr.c,v 1.3 2021/12/19 12:21:30 riastradh Exp $ */
2
3 /*
4 * Copyright 2015 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_polaris10_smumgr.c,v 1.3 2021/12/19 12:21:30 riastradh Exp $");
28
29 #include <linux/pci.h>
30
31 #include "pp_debug.h"
32 #include "smumgr.h"
33 #include "smu74.h"
34 #include "smu_ucode_xfer_vi.h"
35 #include "polaris10_smumgr.h"
36 #include "smu74_discrete.h"
37 #include "smu/smu_7_1_3_d.h"
38 #include "smu/smu_7_1_3_sh_mask.h"
39 #include "gmc/gmc_8_1_d.h"
40 #include "gmc/gmc_8_1_sh_mask.h"
41 #include "oss/oss_3_0_d.h"
42 #include "gca/gfx_8_0_d.h"
43 #include "bif/bif_5_0_d.h"
44 #include "bif/bif_5_0_sh_mask.h"
45 #include "ppatomctrl.h"
46 #include "cgs_common.h"
47 #include "smu7_ppsmc.h"
48 #include "smu7_smumgr.h"
49
50 #include "smu7_dyn_defaults.h"
51
52 #include "smu7_hwmgr.h"
53 #include "hardwaremanager.h"
54 #include "atombios.h"
55 #include "pppcielanes.h"
56
57 #include "dce/dce_10_0_d.h"
58 #include "dce/dce_10_0_sh_mask.h"
59
60 #define POLARIS10_SMC_SIZE 0x20000
61 #define POWERTUNE_DEFAULT_SET_MAX 1
62 #define VDDC_VDDCI_DELTA 200
63 #define MC_CG_ARB_FREQ_F1 0x0b
64
65 static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
66 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
67 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
68 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
69 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
70 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
71 };
72
73 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
74 {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
75 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
76 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
77 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
78 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
79 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
80 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
81 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
82
83 #define PPPOLARIS10_TARGETACTIVITY_DFLT 50
84
85 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
86 /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */
87 /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
88 { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
89 { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
90 { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
91 { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
92 { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
93 { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
94 { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
95 { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
96 };
97
98 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
99 0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
100
polaris10_perform_btc(struct pp_hwmgr * hwmgr)101 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
102 {
103 int result = 0;
104 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
105
106 if (0 != smu_data->avfs_btc_param) {
107 if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param)) {
108 pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
109 result = -1;
110 }
111 }
112 if (smu_data->avfs_btc_param > 1) {
113 /* Soft-Reset to reset the engine before loading uCode */
114 /* halt */
115 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
116 /* reset everything */
117 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
118 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
119 }
120 return result;
121 }
122
123
polaris10_setup_graphics_level_structure(struct pp_hwmgr * hwmgr)124 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
125 {
126 uint32_t vr_config;
127 uint32_t dpm_table_start;
128
129 uint16_t u16_boot_mvdd;
130 uint32_t graphics_level_address, vr_config_address, graphics_level_size;
131
132 graphics_level_size = sizeof(avfs_graphics_level_polaris10);
133 u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
134
135 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
136 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
137 &dpm_table_start, 0x40000),
138 "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
139 return -1);
140
141 /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
142 vr_config = 0x01000500; /* Real value:0x50001 */
143
144 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
145
146 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
147 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
148 "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
149 return -1);
150
151 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
152
153 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
154 (uint8_t *)(&avfs_graphics_level_polaris10),
155 graphics_level_size, 0x40000),
156 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
157 return -1);
158
159 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
160
161 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
162 (const uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
163 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
164 return -1);
165
166 /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
167
168 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
169
170 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
171 (const uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
172 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
173 return -1);
174
175 return 0;
176 }
177
178
polaris10_avfs_event_mgr(struct pp_hwmgr * hwmgr)179 static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
180 {
181 struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
182
183 if (!hwmgr->avfs_supported)
184 return 0;
185
186 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
187 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
188 return -EINVAL);
189
190 if (smu_data->avfs_btc_param > 1) {
191 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
192 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
193 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
194 return -EINVAL);
195 }
196
197 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
198 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
199 return -EINVAL);
200
201 return 0;
202 }
203
polaris10_start_smu_in_protection_mode(struct pp_hwmgr * hwmgr)204 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
205 {
206 int result = 0;
207
208 /* Wait for smc boot up */
209 /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
210
211 /* Assert reset */
212 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
213 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
214
215 result = smu7_upload_smu_firmware_image(hwmgr);
216 if (result != 0)
217 return result;
218
219 /* Clear status */
220 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
221
222 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
223 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
224
225 /* De-assert reset */
226 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
227 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
228
229
230 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
231
232
233 /* Call Test SMU message with 0x20000 offset to trigger SMU start */
234 smu7_send_msg_to_smc_offset(hwmgr);
235
236 /* Wait done bit to be set */
237 /* Check pass/failed indicator */
238
239 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
240
241 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
242 SMU_STATUS, SMU_PASS))
243 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
244
245 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
246
247 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
248 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
249
250 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
251 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
252
253 /* Wait for firmware to initialize */
254 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
255
256 return result;
257 }
258
polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr * hwmgr)259 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
260 {
261 int result = 0;
262
263 /* wait for smc boot up */
264 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
265
266 /* Clear firmware interrupt enable flag */
267 /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
268 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
269 ixFIRMWARE_FLAGS, 0);
270
271 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
272 SMC_SYSCON_RESET_CNTL,
273 rst_reg, 1);
274
275 result = smu7_upload_smu_firmware_image(hwmgr);
276 if (result != 0)
277 return result;
278
279 /* Set smc instruct start point at 0x0 */
280 smu7_program_jump_on_start(hwmgr);
281
282 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
283 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
284
285 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
286 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
287
288 /* Wait for firmware to initialize */
289
290 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
291 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
292
293 return result;
294 }
295
polaris10_start_smu(struct pp_hwmgr * hwmgr)296 static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
297 {
298 int result = 0;
299 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
300
301 /* Only start SMC if SMC RAM is not running */
302 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
303 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
304 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
305
306 /* Check if SMU is running in protected mode */
307 if (smu_data->protected_mode == 0)
308 result = polaris10_start_smu_in_non_protection_mode(hwmgr);
309 else
310 result = polaris10_start_smu_in_protection_mode(hwmgr);
311
312 if (result != 0)
313 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
314
315 polaris10_avfs_event_mgr(hwmgr);
316 }
317
318 /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
319 smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
320 &(smu_data->smu7_data.soft_regs_start), 0x40000);
321
322 result = smu7_request_smu_load_fw(hwmgr);
323
324 return result;
325 }
326
polaris10_is_hw_avfs_present(struct pp_hwmgr * hwmgr)327 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
328 {
329 uint32_t efuse;
330
331 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
332 efuse &= 0x00000001;
333 if (efuse)
334 return true;
335
336 return false;
337 }
338
polaris10_smu_init(struct pp_hwmgr * hwmgr)339 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
340 {
341 struct polaris10_smumgr *smu_data;
342
343 smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
344 if (smu_data == NULL)
345 return -ENOMEM;
346
347 hwmgr->smu_backend = smu_data;
348
349 if (smu7_init(hwmgr)) {
350 kfree(smu_data);
351 return -EINVAL;
352 }
353
354 return 0;
355 }
356
polaris10_get_dependency_volt_by_clk(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table * dep_table,uint32_t clock,SMU_VoltageLevel * voltage,uint32_t * mvdd)357 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
358 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
359 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
360 {
361 uint32_t i;
362 uint16_t vddci;
363 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
364
365 *voltage = *mvdd = 0;
366
367 /* clock - voltage dependency table is empty table */
368 if (dep_table->count == 0)
369 return -EINVAL;
370
371 for (i = 0; i < dep_table->count; i++) {
372 /* find first sclk bigger than request */
373 if (dep_table->entries[i].clk >= clock) {
374 *voltage |= (dep_table->entries[i].vddc *
375 VOLTAGE_SCALE) << VDDC_SHIFT;
376 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
377 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
378 VOLTAGE_SCALE) << VDDCI_SHIFT;
379 else if (dep_table->entries[i].vddci)
380 *voltage |= (dep_table->entries[i].vddci *
381 VOLTAGE_SCALE) << VDDCI_SHIFT;
382 else {
383 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
384 (dep_table->entries[i].vddc -
385 (uint16_t)VDDC_VDDCI_DELTA));
386 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
387 }
388
389 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
390 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
391 VOLTAGE_SCALE;
392 else if (dep_table->entries[i].mvdd)
393 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
394 VOLTAGE_SCALE;
395
396 *voltage |= 1 << PHASES_SHIFT;
397 return 0;
398 }
399 }
400
401 /* sclk is bigger than max sclk in the dependence table */
402 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
403
404 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
405 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
406 VOLTAGE_SCALE) << VDDCI_SHIFT;
407 else if (dep_table->entries[i-1].vddci) {
408 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
409 (dep_table->entries[i].vddc -
410 (uint16_t)VDDC_VDDCI_DELTA));
411 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
412 }
413
414 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
415 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
416 else if (dep_table->entries[i].mvdd)
417 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
418
419 return 0;
420 }
421
scale_fan_gain_settings(uint16_t raw_setting)422 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
423 {
424 uint32_t tmp;
425 tmp = raw_setting * 4096 / 100;
426 return (uint16_t)tmp;
427 }
428
polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr * hwmgr)429 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
430 {
431 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
432
433 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
434 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
435 struct phm_ppt_v1_information *table_info =
436 (struct phm_ppt_v1_information *)(hwmgr->pptable);
437 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
438 struct pp_advance_fan_control_parameters *fan_table =
439 &hwmgr->thermal_controller.advanceFanControlParameters;
440 int i, j, k;
441 const uint16_t *pdef1;
442 const uint16_t *pdef2;
443
444 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
445 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
446
447 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
448 "Target Operating Temp is out of Range!",
449 );
450
451 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
452 cac_dtp_table->usTargetOperatingTemp * 256);
453 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
454 cac_dtp_table->usTemperatureLimitHotspot * 256);
455 table->FanGainEdge = PP_HOST_TO_SMC_US(
456 scale_fan_gain_settings(fan_table->usFanGainEdge));
457 table->FanGainHotspot = PP_HOST_TO_SMC_US(
458 scale_fan_gain_settings(fan_table->usFanGainHotspot));
459
460 pdef1 = defaults->BAPMTI_R;
461 pdef2 = defaults->BAPMTI_RC;
462
463 for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
464 for (j = 0; j < SMU74_DTE_SOURCES; j++) {
465 for (k = 0; k < SMU74_DTE_SINKS; k++) {
466 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
467 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
468 pdef1++;
469 pdef2++;
470 }
471 }
472 }
473
474 return 0;
475 }
476
polaris10_populate_svi_load_line(struct pp_hwmgr * hwmgr)477 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
478 {
479 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
480 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
481
482 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
483 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
484 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
485 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
486
487 return 0;
488 }
489
polaris10_populate_tdc_limit(struct pp_hwmgr * hwmgr)490 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
491 {
492 uint16_t tdc_limit;
493 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
494 struct phm_ppt_v1_information *table_info =
495 (struct phm_ppt_v1_information *)(hwmgr->pptable);
496 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
497
498 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
499 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
500 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
501 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
502 defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
503 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
504
505 return 0;
506 }
507
polaris10_populate_dw8(struct pp_hwmgr * hwmgr,uint32_t fuse_table_offset)508 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
509 {
510 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
511 const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
512 uint32_t temp;
513
514 if (smu7_read_smc_sram_dword(hwmgr,
515 fuse_table_offset +
516 offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
517 (uint32_t *)&temp, SMC_RAM_END))
518 PP_ASSERT_WITH_CODE(false,
519 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
520 return -EINVAL);
521 else {
522 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
523 smu_data->power_tune_table.LPMLTemperatureMin =
524 (uint8_t)((temp >> 16) & 0xff);
525 smu_data->power_tune_table.LPMLTemperatureMax =
526 (uint8_t)((temp >> 8) & 0xff);
527 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
528 }
529 return 0;
530 }
531
polaris10_populate_temperature_scaler(struct pp_hwmgr * hwmgr)532 static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
533 {
534 int i;
535 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
536
537 /* Currently not used. Set all to zero. */
538 for (i = 0; i < 16; i++)
539 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
540
541 return 0;
542 }
543
polaris10_populate_fuzzy_fan(struct pp_hwmgr * hwmgr)544 static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
545 {
546 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
547
548 /* TO DO move to hwmgr */
549 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
550 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
551 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
552 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
553
554 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
555 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
556 return 0;
557 }
558
polaris10_populate_gnb_lpml(struct pp_hwmgr * hwmgr)559 static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
560 {
561 int i;
562 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
563
564 /* Currently not used. Set all to zero. */
565 for (i = 0; i < 16; i++)
566 smu_data->power_tune_table.GnbLPML[i] = 0;
567
568 return 0;
569 }
570
polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr * hwmgr)571 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
572 {
573 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
574 struct phm_ppt_v1_information *table_info =
575 (struct phm_ppt_v1_information *)(hwmgr->pptable);
576 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
577 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
578 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
579
580 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
581 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
582
583 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
584 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
585 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
586 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
587
588 return 0;
589 }
590
polaris10_populate_pm_fuses(struct pp_hwmgr * hwmgr)591 static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
592 {
593 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
594 uint32_t pm_fuse_table_offset;
595
596 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
597 PHM_PlatformCaps_PowerContainment)) {
598 if (smu7_read_smc_sram_dword(hwmgr,
599 SMU7_FIRMWARE_HEADER_LOCATION +
600 offsetof(SMU74_Firmware_Header, PmFuseTable),
601 &pm_fuse_table_offset, SMC_RAM_END))
602 PP_ASSERT_WITH_CODE(false,
603 "Attempt to get pm_fuse_table_offset Failed!",
604 return -EINVAL);
605
606 if (polaris10_populate_svi_load_line(hwmgr))
607 PP_ASSERT_WITH_CODE(false,
608 "Attempt to populate SviLoadLine Failed!",
609 return -EINVAL);
610
611 if (polaris10_populate_tdc_limit(hwmgr))
612 PP_ASSERT_WITH_CODE(false,
613 "Attempt to populate TDCLimit Failed!", return -EINVAL);
614
615 if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
616 PP_ASSERT_WITH_CODE(false,
617 "Attempt to populate TdcWaterfallCtl, "
618 "LPMLTemperature Min and Max Failed!",
619 return -EINVAL);
620
621 if (0 != polaris10_populate_temperature_scaler(hwmgr))
622 PP_ASSERT_WITH_CODE(false,
623 "Attempt to populate LPMLTemperatureScaler Failed!",
624 return -EINVAL);
625
626 if (polaris10_populate_fuzzy_fan(hwmgr))
627 PP_ASSERT_WITH_CODE(false,
628 "Attempt to populate Fuzzy Fan Control parameters Failed!",
629 return -EINVAL);
630
631 if (polaris10_populate_gnb_lpml(hwmgr))
632 PP_ASSERT_WITH_CODE(false,
633 "Attempt to populate GnbLPML Failed!",
634 return -EINVAL);
635
636 if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
637 PP_ASSERT_WITH_CODE(false,
638 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
639 "Sidd Failed!", return -EINVAL);
640
641 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
642 (const uint8_t *)&smu_data->power_tune_table,
643 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
644 PP_ASSERT_WITH_CODE(false,
645 "Attempt to download PmFuseTable Failed!",
646 return -EINVAL);
647 }
648 return 0;
649 }
650
polaris10_populate_smc_mvdd_table(struct pp_hwmgr * hwmgr,SMU74_Discrete_DpmTable * table)651 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
652 SMU74_Discrete_DpmTable *table)
653 {
654 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
655 uint32_t count, level;
656
657 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
658 count = data->mvdd_voltage_table.count;
659 if (count > SMU_MAX_SMIO_LEVELS)
660 count = SMU_MAX_SMIO_LEVELS;
661 for (level = 0; level < count; level++) {
662 table->SmioTable2.Pattern[level].Voltage =
663 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
664 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
665 table->SmioTable2.Pattern[level].Smio =
666 (uint8_t) level;
667 table->Smio[level] |=
668 data->mvdd_voltage_table.entries[level].smio_low;
669 }
670 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
671
672 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
673 }
674
675 return 0;
676 }
677
polaris10_populate_smc_vddci_table(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_DpmTable * table)678 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
679 struct SMU74_Discrete_DpmTable *table)
680 {
681 uint32_t count, level;
682 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
683
684 count = data->vddci_voltage_table.count;
685
686 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
687 if (count > SMU_MAX_SMIO_LEVELS)
688 count = SMU_MAX_SMIO_LEVELS;
689 for (level = 0; level < count; ++level) {
690 table->SmioTable1.Pattern[level].Voltage =
691 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
692 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
693
694 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
695 }
696 }
697
698 table->SmioMask1 = data->vddci_voltage_table.mask_low;
699
700 return 0;
701 }
702
polaris10_populate_cac_table(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_DpmTable * table)703 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
704 struct SMU74_Discrete_DpmTable *table)
705 {
706 uint32_t count;
707 uint8_t index;
708 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
709 struct phm_ppt_v1_information *table_info =
710 (struct phm_ppt_v1_information *)(hwmgr->pptable);
711 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
712 table_info->vddc_lookup_table;
713 /* tables is already swapped, so in order to use the value from it,
714 * we need to swap it back.
715 * We are populating vddc CAC data to BapmVddc table
716 * in split and merged mode
717 */
718 for (count = 0; count < lookup_table->count; count++) {
719 index = phm_get_voltage_index(lookup_table,
720 data->vddc_voltage_table.entries[count].value);
721 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
722 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
723 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
724 }
725
726 return 0;
727 }
728
polaris10_populate_smc_voltage_tables(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_DpmTable * table)729 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
730 struct SMU74_Discrete_DpmTable *table)
731 {
732 polaris10_populate_smc_vddci_table(hwmgr, table);
733 polaris10_populate_smc_mvdd_table(hwmgr, table);
734 polaris10_populate_cac_table(hwmgr, table);
735
736 return 0;
737 }
738
polaris10_populate_ulv_level(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_Ulv * state)739 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
740 struct SMU74_Discrete_Ulv *state)
741 {
742 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
743 struct phm_ppt_v1_information *table_info =
744 (struct phm_ppt_v1_information *)(hwmgr->pptable);
745
746 state->CcPwrDynRm = 0;
747 state->CcPwrDynRm1 = 0;
748
749 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
750 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
751 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
752
753 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
754 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
755 else
756 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
757
758 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
759 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
760 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
761
762 return 0;
763 }
764
polaris10_populate_ulv_state(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_DpmTable * table)765 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
766 struct SMU74_Discrete_DpmTable *table)
767 {
768 return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
769 }
770
polaris10_populate_smc_link_level(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_DpmTable * table)771 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
772 struct SMU74_Discrete_DpmTable *table)
773 {
774 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
775 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
776 struct smu7_dpm_table *dpm_table = &data->dpm_table;
777 int i;
778
779 /* Index (dpm_table->pcie_speed_table.count)
780 * is reserved for PCIE boot level. */
781 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
782 table->LinkLevel[i].PcieGenSpeed =
783 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
784 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
785 dpm_table->pcie_speed_table.dpm_levels[i].param1);
786 table->LinkLevel[i].EnabledForActivity = 1;
787 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
788 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
789 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
790 }
791
792 smu_data->smc_state_table.LinkLevelCount =
793 (uint8_t)dpm_table->pcie_speed_table.count;
794
795 /* To Do move to hwmgr */
796 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
797 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
798
799 return 0;
800 }
801
802
polaris10_get_sclk_range_table(struct pp_hwmgr * hwmgr,SMU74_Discrete_DpmTable * table)803 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
804 SMU74_Discrete_DpmTable *table)
805 {
806 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
807 uint32_t i, ref_clk;
808
809 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
810
811 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
812
813 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
814 for (i = 0; i < NUM_SCLK_RANGE; i++) {
815 table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
816 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
817 table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
818
819 table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
820 table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
821
822 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
823 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
824 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
825 }
826 return;
827 }
828
829 for (i = 0; i < NUM_SCLK_RANGE; i++) {
830 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
831 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
832
833 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
834 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
835 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
836
837 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
838 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
839
840 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
841 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
842 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
843 }
844 }
845
polaris10_calculate_sclk_params(struct pp_hwmgr * hwmgr,uint32_t clock,SMU_SclkSetting * sclk_setting)846 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
847 uint32_t clock, SMU_SclkSetting *sclk_setting)
848 {
849 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
850 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
851 struct pp_atomctrl_clock_dividers_ai dividers;
852 uint32_t ref_clock;
853 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
854 uint8_t i;
855 int result;
856 uint64_t temp;
857
858 sclk_setting->SclkFrequency = clock;
859 /* get the engine clock dividers for this clock value */
860 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
861 if (result == 0) {
862 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
863 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
864 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
865 sclk_setting->PllRange = dividers.ucSclkPllRange;
866 sclk_setting->Sclk_slew_rate = 0x400;
867 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
868 sclk_setting->Pcc_down_slew_rate = 0xffff;
869 sclk_setting->SSc_En = dividers.ucSscEnable;
870 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
871 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
872 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
873 return result;
874 }
875
876 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
877
878 for (i = 0; i < NUM_SCLK_RANGE; i++) {
879 if (clock > smu_data->range_table[i].trans_lower_frequency
880 && clock <= smu_data->range_table[i].trans_upper_frequency) {
881 sclk_setting->PllRange = i;
882 break;
883 }
884 }
885
886 sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
887 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
888 temp <<= 0x10;
889 do_div(temp, ref_clock);
890 sclk_setting->Fcw_frac = temp & 0xffff;
891
892 pcc_target_percent = 10; /* Hardcode 10% for now. */
893 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
894 sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
895
896 ss_target_percent = 2; /* Hardcode 2% for now. */
897 sclk_setting->SSc_En = 0;
898 if (ss_target_percent) {
899 sclk_setting->SSc_En = 1;
900 ss_target_freq = clock - (clock * ss_target_percent / 100);
901 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
902 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
903 temp <<= 0x10;
904 do_div(temp, ref_clock);
905 sclk_setting->Fcw1_frac = temp & 0xffff;
906 }
907
908 return 0;
909 }
910
polaris10_populate_single_graphic_level(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU74_Discrete_GraphicsLevel * level)911 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
912 uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
913 {
914 int result;
915 /* PP_Clocks minClocks; */
916 uint32_t mvdd;
917 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
918 struct phm_ppt_v1_information *table_info =
919 (struct phm_ppt_v1_information *)(hwmgr->pptable);
920 SMU_SclkSetting curr_sclk_setting = { 0 };
921 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
922
923 result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
924
925 if (hwmgr->od_enabled)
926 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
927 else
928 vdd_dep_table = table_info->vdd_dep_on_sclk;
929
930 /* populate graphics levels */
931 result = polaris10_get_dependency_volt_by_clk(hwmgr,
932 vdd_dep_table, clock,
933 &level->MinVoltage, &mvdd);
934
935 PP_ASSERT_WITH_CODE((0 == result),
936 "can not find VDDC voltage value for "
937 "VDDC engine clock dependency table",
938 return result);
939 level->ActivityLevel = data->current_profile_setting.sclk_activity;
940
941 level->CcPwrDynRm = 0;
942 level->CcPwrDynRm1 = 0;
943 level->EnabledForActivity = 0;
944 level->EnabledForThrottle = 1;
945 level->UpHyst = data->current_profile_setting.sclk_up_hyst;
946 level->DownHyst = data->current_profile_setting.sclk_down_hyst;
947 level->VoltageDownHyst = 0;
948 level->PowerThrottle = 0;
949 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
950
951 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
952 level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
953 hwmgr->display_config->min_core_set_clock_in_sr);
954
955 /* Default to slow, highest DPM level will be
956 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
957 */
958 if (data->update_up_hyst)
959 level->UpHyst = (uint8_t)data->up_hyst;
960 if (data->update_down_hyst)
961 level->DownHyst = (uint8_t)data->down_hyst;
962
963 level->SclkSetting = curr_sclk_setting;
964
965 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
966 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
967 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
968 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
969 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
970 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
971 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
972 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
973 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
974 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
975 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
976 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
977 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
978 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
979 return 0;
980 }
981
polaris10_populate_all_graphic_levels(struct pp_hwmgr * hwmgr)982 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
983 {
984 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
985 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
986 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
987 struct phm_ppt_v1_information *table_info =
988 (struct phm_ppt_v1_information *)(hwmgr->pptable);
989 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
990 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
991 int result = 0;
992 uint32_t array = smu_data->smu7_data.dpm_table_start +
993 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
994 uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
995 SMU74_MAX_LEVELS_GRAPHICS;
996 struct SMU74_Discrete_GraphicsLevel *levels =
997 smu_data->smc_state_table.GraphicsLevel;
998 uint32_t i, max_entry;
999 uint8_t hightest_pcie_level_enabled = 0,
1000 lowest_pcie_level_enabled = 0,
1001 mid_pcie_level_enabled = 0,
1002 count = 0;
1003
1004 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1005
1006 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1007
1008 result = polaris10_populate_single_graphic_level(hwmgr,
1009 dpm_table->sclk_table.dpm_levels[i].value,
1010 &(smu_data->smc_state_table.GraphicsLevel[i]));
1011 if (result)
1012 return result;
1013
1014 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1015 if (i > 1)
1016 levels[i].DeepSleepDivId = 0;
1017 }
1018 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1019 PHM_PlatformCaps_SPLLShutdownSupport))
1020 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1021
1022 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
1023 smu_data->smc_state_table.GraphicsDpmLevelCount =
1024 (uint8_t)dpm_table->sclk_table.count;
1025 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1026 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1027
1028
1029 if (pcie_table != NULL) {
1030 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1031 "There must be 1 or more PCIE levels defined in PPTable.",
1032 return -EINVAL);
1033 max_entry = pcie_entry_cnt - 1;
1034 for (i = 0; i < dpm_table->sclk_table.count; i++)
1035 levels[i].pcieDpmLevel =
1036 (uint8_t) ((i < max_entry) ? i : max_entry);
1037 } else {
1038 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1039 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1040 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1041 hightest_pcie_level_enabled++;
1042
1043 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1044 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1045 (1 << lowest_pcie_level_enabled)) == 0))
1046 lowest_pcie_level_enabled++;
1047
1048 while ((count < hightest_pcie_level_enabled) &&
1049 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1050 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1051 count++;
1052
1053 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1054 hightest_pcie_level_enabled ?
1055 (lowest_pcie_level_enabled + 1 + count) :
1056 hightest_pcie_level_enabled;
1057
1058 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1059 for (i = 2; i < dpm_table->sclk_table.count; i++)
1060 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1061
1062 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1063 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1064
1065 /* set pcieDpmLevel to mid_pcie_level_enabled */
1066 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1067 }
1068 /* level count will send to smc once at init smc table and never change */
1069 result = smu7_copy_bytes_to_smc(hwmgr, array, (const uint8_t *)levels,
1070 (uint32_t)array_size, SMC_RAM_END);
1071
1072 return result;
1073 }
1074
1075
polaris10_populate_single_memory_level(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU74_Discrete_MemoryLevel * mem_level)1076 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1077 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1078 {
1079 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1080 struct phm_ppt_v1_information *table_info =
1081 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1082 int result = 0;
1083 uint32_t mclk_stutter_mode_threshold = 40000;
1084 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1085
1086
1087 if (hwmgr->od_enabled)
1088 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1089 else
1090 vdd_dep_table = table_info->vdd_dep_on_mclk;
1091
1092 if (vdd_dep_table) {
1093 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1094 vdd_dep_table, clock,
1095 &mem_level->MinVoltage, &mem_level->MinMvdd);
1096 PP_ASSERT_WITH_CODE((0 == result),
1097 "can not find MinVddc voltage value from memory "
1098 "VDDC voltage dependency table", return result);
1099 }
1100
1101 mem_level->MclkFrequency = clock;
1102 mem_level->EnabledForThrottle = 1;
1103 mem_level->EnabledForActivity = 0;
1104 mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1105 mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1106 mem_level->VoltageDownHyst = 0;
1107 mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1108 mem_level->StutterEnable = false;
1109 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1110
1111 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1112 data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1113
1114 if (mclk_stutter_mode_threshold &&
1115 (clock <= mclk_stutter_mode_threshold) &&
1116 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1117 STUTTER_ENABLE) & 0x1))
1118 mem_level->StutterEnable = true;
1119
1120 if (!result) {
1121 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1122 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1123 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1124 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1125 }
1126 return result;
1127 }
1128
polaris10_populate_all_memory_levels(struct pp_hwmgr * hwmgr)1129 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1130 {
1131 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1132 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1133 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1134 int result;
1135 /* populate MCLK dpm table to SMU7 */
1136 uint32_t array = smu_data->smu7_data.dpm_table_start +
1137 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1138 uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1139 SMU74_MAX_LEVELS_MEMORY;
1140 struct SMU74_Discrete_MemoryLevel *levels =
1141 smu_data->smc_state_table.MemoryLevel;
1142 uint32_t i;
1143
1144 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1145 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1146 "can not populate memory level as memory clock is zero",
1147 return -EINVAL);
1148 result = polaris10_populate_single_memory_level(hwmgr,
1149 dpm_table->mclk_table.dpm_levels[i].value,
1150 &levels[i]);
1151 if (i == dpm_table->mclk_table.count - 1) {
1152 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1153 levels[i].EnabledForActivity = 1;
1154 }
1155 if (result)
1156 return result;
1157 }
1158
1159 /* In order to prevent MC activity from stutter mode to push DPM up,
1160 * the UVD change complements this by putting the MCLK in
1161 * a higher state by default such that we are not affected by
1162 * up threshold or and MCLK DPM latency.
1163 */
1164 levels[0].ActivityLevel = 0x1f;
1165 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1166
1167 smu_data->smc_state_table.MemoryDpmLevelCount =
1168 (uint8_t)dpm_table->mclk_table.count;
1169 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1170 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1171
1172 /* level count will send to smc once at init smc table and never change */
1173 result = smu7_copy_bytes_to_smc(hwmgr, array, (const uint8_t *)levels,
1174 (uint32_t)array_size, SMC_RAM_END);
1175
1176 return result;
1177 }
1178
polaris10_populate_mvdd_value(struct pp_hwmgr * hwmgr,uint32_t mclk,SMIO_Pattern * smio_pat)1179 static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1180 uint32_t mclk, SMIO_Pattern *smio_pat)
1181 {
1182 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1183 struct phm_ppt_v1_information *table_info =
1184 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1185 uint32_t i = 0;
1186
1187 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1188 /* find mvdd value which clock is more than request */
1189 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1190 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1191 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1192 break;
1193 }
1194 }
1195 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1196 "MVDD Voltage is outside the supported range.",
1197 return -EINVAL);
1198 } else
1199 return -EINVAL;
1200
1201 return 0;
1202 }
1203
polaris10_populate_smc_acpi_level(struct pp_hwmgr * hwmgr,SMU74_Discrete_DpmTable * table)1204 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1205 SMU74_Discrete_DpmTable *table)
1206 {
1207 int result = 0;
1208 uint32_t sclk_frequency;
1209 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1210 struct phm_ppt_v1_information *table_info =
1211 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1212 SMIO_Pattern vol_level;
1213 uint32_t mvdd;
1214
1215 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1216
1217 /* Get MinVoltage and Frequency from DPM0,
1218 * already converted to SMC_UL */
1219 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1220 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1221 table_info->vdd_dep_on_sclk,
1222 sclk_frequency,
1223 &table->ACPILevel.MinVoltage, &mvdd);
1224 PP_ASSERT_WITH_CODE((0 == result),
1225 "Cannot find ACPI VDDC voltage value "
1226 "in Clock Dependency Table",
1227 );
1228
1229 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting));
1230 PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1231
1232 table->ACPILevel.DeepSleepDivId = 0;
1233 table->ACPILevel.CcPwrDynRm = 0;
1234 table->ACPILevel.CcPwrDynRm1 = 0;
1235
1236 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1237 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1238 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1239 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1240
1241 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1242 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1243 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1244 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1245 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1246 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1247 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1248 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1249 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1250 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1251
1252
1253 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1254 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1255 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1256 table_info->vdd_dep_on_mclk,
1257 table->MemoryACPILevel.MclkFrequency,
1258 &table->MemoryACPILevel.MinVoltage, &mvdd);
1259 PP_ASSERT_WITH_CODE((0 == result),
1260 "Cannot find ACPI VDDCI voltage value "
1261 "in Clock Dependency Table",
1262 );
1263
1264 if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1265 (data->mclk_dpm_key_disabled)))
1266 polaris10_populate_mvdd_value(hwmgr,
1267 data->dpm_table.mclk_table.dpm_levels[0].value,
1268 &vol_level);
1269
1270 if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1271 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1272 else
1273 table->MemoryACPILevel.MinMvdd = 0;
1274
1275 table->MemoryACPILevel.StutterEnable = false;
1276
1277 table->MemoryACPILevel.EnabledForThrottle = 0;
1278 table->MemoryACPILevel.EnabledForActivity = 0;
1279 table->MemoryACPILevel.UpHyst = 0;
1280 table->MemoryACPILevel.DownHyst = 100;
1281 table->MemoryACPILevel.VoltageDownHyst = 0;
1282 table->MemoryACPILevel.ActivityLevel =
1283 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1284
1285 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1286 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1287
1288 return result;
1289 }
1290
polaris10_populate_smc_vce_level(struct pp_hwmgr * hwmgr,SMU74_Discrete_DpmTable * table)1291 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1292 SMU74_Discrete_DpmTable *table)
1293 {
1294 int result = -EINVAL;
1295 uint8_t count;
1296 struct pp_atomctrl_clock_dividers_vi dividers;
1297 struct phm_ppt_v1_information *table_info =
1298 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1299 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1300 table_info->mm_dep_table;
1301 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1302 uint32_t vddci;
1303
1304 table->VceLevelCount = (uint8_t)(mm_table->count);
1305 table->VceBootLevel = 0;
1306
1307 for (count = 0; count < table->VceLevelCount; count++) {
1308 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1309 table->VceLevel[count].MinVoltage = 0;
1310 table->VceLevel[count].MinVoltage |=
1311 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1312
1313 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1314 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1315 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1316 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1317 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1318 else
1319 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1320
1321
1322 table->VceLevel[count].MinVoltage |=
1323 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1324 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1325
1326 /*retrieve divider value for VBIOS */
1327 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1328 table->VceLevel[count].Frequency, ÷rs);
1329 PP_ASSERT_WITH_CODE((0 == result),
1330 "can not find divide id for VCE engine clock",
1331 return result);
1332
1333 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1334
1335 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1336 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1337 }
1338 return result;
1339 }
1340
polaris10_populate_memory_timing_parameters(struct pp_hwmgr * hwmgr,int32_t eng_clock,int32_t mem_clock,SMU74_Discrete_MCArbDramTimingTableEntry * arb_regs)1341 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1342 int32_t eng_clock, int32_t mem_clock,
1343 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1344 {
1345 uint32_t dram_timing;
1346 uint32_t dram_timing2;
1347 uint32_t burst_time;
1348 int result;
1349
1350 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1351 eng_clock, mem_clock);
1352 PP_ASSERT_WITH_CODE(result == 0,
1353 "Error calling VBIOS to set DRAM_TIMING.", return result);
1354
1355 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1356 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1357 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1358
1359
1360 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1361 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1362 arb_regs->McArbBurstTime = (uint8_t)burst_time;
1363
1364 return 0;
1365 }
1366
polaris10_program_memory_timing_parameters(struct pp_hwmgr * hwmgr)1367 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1368 {
1369 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1370 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1371 struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1372 uint32_t i, j;
1373 int result = 0;
1374
1375 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1376 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1377 result = polaris10_populate_memory_timing_parameters(hwmgr,
1378 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1379 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1380 &arb_regs.entries[i][j]);
1381 if (result == 0)
1382 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1383 if (result != 0)
1384 return result;
1385 }
1386 }
1387
1388 result = smu7_copy_bytes_to_smc(
1389 hwmgr,
1390 smu_data->smu7_data.arb_table_start,
1391 (const uint8_t *)&arb_regs,
1392 sizeof(SMU74_Discrete_MCArbDramTimingTable),
1393 SMC_RAM_END);
1394 return result;
1395 }
1396
polaris10_populate_smc_uvd_level(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_DpmTable * table)1397 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1398 struct SMU74_Discrete_DpmTable *table)
1399 {
1400 int result = -EINVAL;
1401 uint8_t count;
1402 struct pp_atomctrl_clock_dividers_vi dividers;
1403 struct phm_ppt_v1_information *table_info =
1404 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1405 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1406 table_info->mm_dep_table;
1407 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1408 uint32_t vddci;
1409
1410 table->UvdLevelCount = (uint8_t)(mm_table->count);
1411 table->UvdBootLevel = 0;
1412
1413 for (count = 0; count < table->UvdLevelCount; count++) {
1414 table->UvdLevel[count].MinVoltage = 0;
1415 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1416 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1417 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1418 VOLTAGE_SCALE) << VDDC_SHIFT;
1419
1420 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1421 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1422 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1423 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1424 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1425 else
1426 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1427
1428 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1429 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1430
1431 /* retrieve divider value for VBIOS */
1432 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1433 table->UvdLevel[count].VclkFrequency, ÷rs);
1434 PP_ASSERT_WITH_CODE((0 == result),
1435 "can not find divide id for Vclk clock", return result);
1436
1437 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1438
1439 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1440 table->UvdLevel[count].DclkFrequency, ÷rs);
1441 PP_ASSERT_WITH_CODE((0 == result),
1442 "can not find divide id for Dclk clock", return result);
1443
1444 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1445
1446 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1447 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1448 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1449 }
1450
1451 return result;
1452 }
1453
polaris10_populate_smc_boot_level(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_DpmTable * table)1454 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1455 struct SMU74_Discrete_DpmTable *table)
1456 {
1457 int result __unused = 0;
1458 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1459
1460 table->GraphicsBootLevel = 0;
1461 table->MemoryBootLevel = 0;
1462
1463 /* find boot level from dpm table */
1464 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1465 data->vbios_boot_state.sclk_bootup_value,
1466 (uint32_t *)&(table->GraphicsBootLevel));
1467
1468 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1469 data->vbios_boot_state.mclk_bootup_value,
1470 (uint32_t *)&(table->MemoryBootLevel));
1471
1472 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1473 VOLTAGE_SCALE;
1474 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1475 VOLTAGE_SCALE;
1476 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1477 VOLTAGE_SCALE;
1478
1479 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1480 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1481 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1482
1483 return 0;
1484 }
1485
polaris10_populate_smc_initailial_state(struct pp_hwmgr * hwmgr)1486 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1487 {
1488 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1489 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1490 struct phm_ppt_v1_information *table_info =
1491 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1492 uint8_t count, level;
1493
1494 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1495
1496 for (level = 0; level < count; level++) {
1497 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1498 hw_data->vbios_boot_state.sclk_bootup_value) {
1499 smu_data->smc_state_table.GraphicsBootLevel = level;
1500 break;
1501 }
1502 }
1503
1504 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1505 for (level = 0; level < count; level++) {
1506 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1507 hw_data->vbios_boot_state.mclk_bootup_value) {
1508 smu_data->smc_state_table.MemoryBootLevel = level;
1509 break;
1510 }
1511 }
1512
1513 return 0;
1514 }
1515
polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr * hwmgr)1516 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1517 {
1518 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1519 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1520
1521 uint8_t i, stretch_amount, volt_offset = 0;
1522 struct phm_ppt_v1_information *table_info =
1523 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1524 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1525 table_info->vdd_dep_on_sclk;
1526
1527 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1528
1529 /* Read SMU_Eefuse to read and calculate RO and determine
1530 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1531 */
1532 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1533 ixSMU_EFUSE_0 + (67 * 4));
1534 efuse &= 0xFF000000;
1535 efuse = efuse >> 24;
1536
1537 if (hwmgr->chip_id == CHIP_POLARIS10) {
1538 if (hwmgr->is_kicker) {
1539 min = 1200;
1540 max = 2500;
1541 } else {
1542 min = 1000;
1543 max = 2300;
1544 }
1545 } else if (hwmgr->chip_id == CHIP_POLARIS11) {
1546 if (hwmgr->is_kicker) {
1547 min = 900;
1548 max = 2100;
1549 } else {
1550 min = 1100;
1551 max = 2100;
1552 }
1553 } else {
1554 min = 1100;
1555 max = 2100;
1556 }
1557
1558 ro = efuse * (max - min) / 255 + min;
1559
1560 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1561 for (i = 0; i < sclk_table->count; i++) {
1562 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1563 sclk_table->entries[i].cks_enable << i;
1564 if (hwmgr->chip_id == CHIP_POLARIS10) {
1565 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
1566 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1567 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1568 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1569 } else {
1570 volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
1571 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1572 volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1573 (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1574 }
1575
1576 if (volt_without_cks >= volt_with_cks)
1577 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1578 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1579
1580 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1581 }
1582
1583 smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 6;
1584 /* Populate CKS Lookup Table */
1585 if (stretch_amount == 0 || stretch_amount > 5) {
1586 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1587 PHM_PlatformCaps_ClockStretcher);
1588 PP_ASSERT_WITH_CODE(false,
1589 "Stretch Amount in PPTable not supported",
1590 return -EINVAL);
1591 }
1592
1593 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1594 value &= 0xFFFFFFFE;
1595 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1596
1597 return 0;
1598 }
1599
polaris10_populate_vr_config(struct pp_hwmgr * hwmgr,struct SMU74_Discrete_DpmTable * table)1600 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1601 struct SMU74_Discrete_DpmTable *table)
1602 {
1603 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1604 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1605 uint16_t config;
1606
1607 config = VR_MERGED_WITH_VDDC;
1608 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1609
1610 /* Set Vddc Voltage Controller */
1611 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1612 config = VR_SVI2_PLANE_1;
1613 table->VRConfig |= config;
1614 } else {
1615 PP_ASSERT_WITH_CODE(false,
1616 "VDDC should be on SVI2 control in merged mode!",
1617 );
1618 }
1619 /* Set Vddci Voltage Controller */
1620 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1621 config = VR_SVI2_PLANE_2; /* only in merged mode */
1622 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1623 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1624 config = VR_SMIO_PATTERN_1;
1625 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1626 } else {
1627 config = VR_STATIC_VOLTAGE;
1628 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1629 }
1630 /* Set Mvdd Voltage Controller */
1631 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1632 config = VR_SVI2_PLANE_2;
1633 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1634 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1635 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1636 } else {
1637 config = VR_STATIC_VOLTAGE;
1638 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1639 }
1640
1641 return 0;
1642 }
1643
1644
polaris10_populate_avfs_parameters(struct pp_hwmgr * hwmgr)1645 static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1646 {
1647 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1648 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1649 struct amdgpu_device *adev = hwmgr->adev;
1650
1651 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1652 int result = 0;
1653 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1654 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1655 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1656 uint32_t tmp, i;
1657
1658 struct phm_ppt_v1_information *table_info =
1659 (struct phm_ppt_v1_information *)hwmgr->pptable;
1660 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1661 table_info->vdd_dep_on_sclk;
1662
1663
1664 if (!hwmgr->avfs_supported)
1665 return 0;
1666
1667 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1668
1669 if (0 == result) {
1670 if (((adev->pdev->device == 0x67ef) &&
1671 ((adev->pdev->revision == 0xe0) ||
1672 (adev->pdev->revision == 0xe5))) ||
1673 ((adev->pdev->device == 0x67ff) &&
1674 ((adev->pdev->revision == 0xcf) ||
1675 (adev->pdev->revision == 0xef) ||
1676 (adev->pdev->revision == 0xff)))) {
1677 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1678 if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) ||
1679 (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) {
1680 if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) &&
1681 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) &&
1682 (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) &&
1683 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) &&
1684 (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) &&
1685 (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) {
1686 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF718F1D4;
1687 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x323FD;
1688 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x1E455;
1689 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1690 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0;
1691 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x23;
1692 }
1693 }
1694 } else if (hwmgr->chip_id == CHIP_POLARIS12 && !hwmgr->is_kicker) {
1695 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1696 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF6B024DD;
1697 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x3005E;
1698 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0x18A5F;
1699 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
1700 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
1701 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x3B;
1702 } else if (((adev->pdev->device == 0x67df) &&
1703 ((adev->pdev->revision == 0xe0) ||
1704 (adev->pdev->revision == 0xe3) ||
1705 (adev->pdev->revision == 0xe4) ||
1706 (adev->pdev->revision == 0xe5) ||
1707 (adev->pdev->revision == 0xe7) ||
1708 (adev->pdev->revision == 0xef))) ||
1709 ((adev->pdev->device == 0x6fdf) &&
1710 ((adev->pdev->revision == 0xef) ||
1711 (adev->pdev->revision == 0xff)))) {
1712 avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1713 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 = 0xF843B66B;
1714 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 = 0x59CB5;
1715 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 = 0xFFFF287F;
1716 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1717 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
1718 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b = 0x58;
1719 }
1720 }
1721
1722 if (0 == result) {
1723 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1724 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1725 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1726 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1727 table->BTCGB_VDROOP_TABLE[1].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1728 table->BTCGB_VDROOP_TABLE[1].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1729 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1730 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1731 table->AVFSGB_VDROOP_TABLE[0].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1732 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1733 table->AVFSGB_VDROOP_TABLE[0].m2_shift = 12;
1734 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1735 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1736 table->AVFSGB_VDROOP_TABLE[1].b = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1737 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1738 table->AVFSGB_VDROOP_TABLE[1].m2_shift = 12;
1739 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1740 AVFS_meanNsigma.Aconstant[0] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1741 AVFS_meanNsigma.Aconstant[1] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1742 AVFS_meanNsigma.Aconstant[2] = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1743 AVFS_meanNsigma.DC_tol_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1744 AVFS_meanNsigma.Platform_mean = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1745 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1746 AVFS_meanNsigma.Platform_sigma = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1747
1748 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1749 AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1750 AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1751 }
1752
1753 result = smu7_read_smc_sram_dword(hwmgr,
1754 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1755 &tmp, SMC_RAM_END);
1756
1757 smu7_copy_bytes_to_smc(hwmgr,
1758 tmp,
1759 (const uint8_t *)&AVFS_meanNsigma,
1760 sizeof(AVFS_meanNsigma_t),
1761 SMC_RAM_END);
1762
1763 result = smu7_read_smc_sram_dword(hwmgr,
1764 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1765 &tmp, SMC_RAM_END);
1766 smu7_copy_bytes_to_smc(hwmgr,
1767 tmp,
1768 (const uint8_t *)&AVFS_SclkOffset,
1769 sizeof(AVFS_Sclk_Offset_t),
1770 SMC_RAM_END);
1771
1772 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1773 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1774 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1775 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1776 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1777 }
1778 return result;
1779 }
1780
polaris10_init_arb_table_index(struct pp_hwmgr * hwmgr)1781 static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
1782 {
1783 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1784 uint32_t tmp;
1785 int result;
1786
1787 /* This is a read-modify-write on the first byte of the ARB table.
1788 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
1789 * is the field 'current'.
1790 * This solution is ugly, but we never write the whole table only
1791 * individual fields in it.
1792 * In reality this field should not be in that structure
1793 * but in a soft register.
1794 */
1795 result = smu7_read_smc_sram_dword(hwmgr,
1796 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1797
1798 if (result)
1799 return result;
1800
1801 tmp &= 0x00FFFFFF;
1802 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1803
1804 return smu7_write_smc_sram_dword(hwmgr,
1805 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END);
1806 }
1807
polaris10_initialize_power_tune_defaults(struct pp_hwmgr * hwmgr)1808 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1809 {
1810 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1811 struct phm_ppt_v1_information *table_info =
1812 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1813
1814 if (table_info &&
1815 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
1816 table_info->cac_dtp_table->usPowerTuneDataSetID)
1817 smu_data->power_tune_defaults =
1818 &polaris10_power_tune_data_set_array
1819 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
1820 else
1821 smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
1822
1823 }
1824
polaris10_init_smc_table(struct pp_hwmgr * hwmgr)1825 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1826 {
1827 int result;
1828 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1829 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1830
1831 struct phm_ppt_v1_information *table_info =
1832 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1833 struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1834 uint8_t i;
1835 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1836 pp_atomctrl_clock_dividers_vi dividers;
1837
1838 polaris10_initialize_power_tune_defaults(hwmgr);
1839
1840 if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1841 polaris10_populate_smc_voltage_tables(hwmgr, table);
1842
1843 table->SystemFlags = 0;
1844 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1845 PHM_PlatformCaps_AutomaticDCTransition))
1846 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1847
1848 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1849 PHM_PlatformCaps_StepVddc))
1850 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1851
1852 if (hw_data->is_memory_gddr5)
1853 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1854
1855 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1856 result = polaris10_populate_ulv_state(hwmgr, table);
1857 PP_ASSERT_WITH_CODE(0 == result,
1858 "Failed to initialize ULV state!", return result);
1859 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1860 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1861 }
1862
1863 result = polaris10_populate_smc_link_level(hwmgr, table);
1864 PP_ASSERT_WITH_CODE(0 == result,
1865 "Failed to initialize Link Level!", return result);
1866
1867 result = polaris10_populate_all_graphic_levels(hwmgr);
1868 PP_ASSERT_WITH_CODE(0 == result,
1869 "Failed to initialize Graphics Level!", return result);
1870
1871 result = polaris10_populate_all_memory_levels(hwmgr);
1872 PP_ASSERT_WITH_CODE(0 == result,
1873 "Failed to initialize Memory Level!", return result);
1874
1875 result = polaris10_populate_smc_acpi_level(hwmgr, table);
1876 PP_ASSERT_WITH_CODE(0 == result,
1877 "Failed to initialize ACPI Level!", return result);
1878
1879 result = polaris10_populate_smc_vce_level(hwmgr, table);
1880 PP_ASSERT_WITH_CODE(0 == result,
1881 "Failed to initialize VCE Level!", return result);
1882
1883 /* Since only the initial state is completely set up at this point
1884 * (the other states are just copies of the boot state) we only
1885 * need to populate the ARB settings for the initial state.
1886 */
1887 result = polaris10_program_memory_timing_parameters(hwmgr);
1888 PP_ASSERT_WITH_CODE(0 == result,
1889 "Failed to Write ARB settings for the initial state.", return result);
1890
1891 result = polaris10_populate_smc_uvd_level(hwmgr, table);
1892 PP_ASSERT_WITH_CODE(0 == result,
1893 "Failed to initialize UVD Level!", return result);
1894
1895 result = polaris10_populate_smc_boot_level(hwmgr, table);
1896 PP_ASSERT_WITH_CODE(0 == result,
1897 "Failed to initialize Boot Level!", return result);
1898
1899 result = polaris10_populate_smc_initailial_state(hwmgr);
1900 PP_ASSERT_WITH_CODE(0 == result,
1901 "Failed to initialize Boot State!", return result);
1902
1903 result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
1904 PP_ASSERT_WITH_CODE(0 == result,
1905 "Failed to populate BAPM Parameters!", return result);
1906
1907 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1908 PHM_PlatformCaps_ClockStretcher)) {
1909 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
1910 PP_ASSERT_WITH_CODE(0 == result,
1911 "Failed to populate Clock Stretcher Data Table!",
1912 return result);
1913 }
1914
1915 result = polaris10_populate_avfs_parameters(hwmgr);
1916 PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
1917
1918 table->CurrSclkPllRange = 0xff;
1919 table->GraphicsVoltageChangeEnable = 1;
1920 table->GraphicsThermThrottleEnable = 1;
1921 table->GraphicsInterval = 1;
1922 table->VoltageInterval = 1;
1923 table->ThermalInterval = 1;
1924 table->TemperatureLimitHigh =
1925 table_info->cac_dtp_table->usTargetOperatingTemp *
1926 SMU7_Q88_FORMAT_CONVERSION_UNIT;
1927 table->TemperatureLimitLow =
1928 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
1929 SMU7_Q88_FORMAT_CONVERSION_UNIT;
1930 table->MemoryVoltageChangeEnable = 1;
1931 table->MemoryInterval = 1;
1932 table->VoltageResponseTime = 0;
1933 table->PhaseResponseTime = 0;
1934 table->MemoryThermThrottleEnable = 1;
1935 table->PCIeBootLinkLevel = 0;
1936 table->PCIeGenInterval = 1;
1937 table->VRConfig = 0;
1938
1939 result = polaris10_populate_vr_config(hwmgr, table);
1940 PP_ASSERT_WITH_CODE(0 == result,
1941 "Failed to populate VRConfig setting!", return result);
1942 hw_data->vr_config = table->VRConfig;
1943 table->ThermGpio = 17;
1944 table->SclkStepSize = 0x4000;
1945
1946 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
1947 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
1948 } else {
1949 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
1950 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1951 PHM_PlatformCaps_RegulatorHot);
1952 }
1953
1954 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
1955 &gpio_pin)) {
1956 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
1957 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1958 PHM_PlatformCaps_AutomaticDCTransition);
1959 } else {
1960 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
1961 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1962 PHM_PlatformCaps_AutomaticDCTransition);
1963 }
1964
1965 /* Thermal Output GPIO */
1966 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
1967 &gpio_pin)) {
1968 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1969 PHM_PlatformCaps_ThermalOutGPIO);
1970
1971 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
1972
1973 /* For porlarity read GPIOPAD_A with assigned Gpio pin
1974 * since VBIOS will program this register to set 'inactive state',
1975 * driver can then determine 'active state' from this and
1976 * program SMU with correct polarity
1977 */
1978 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
1979 & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
1980 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
1981
1982 /* if required, combine VRHot/PCC with thermal out GPIO */
1983 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
1984 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
1985 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
1986 } else {
1987 table->ThermOutGpio = 17;
1988 table->ThermOutPolarity = 1;
1989 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
1990 }
1991
1992 /* Populate BIF_SCLK levels into SMC DPM table */
1993 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
1994 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], ÷rs);
1995 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
1996
1997 if (i == 0)
1998 table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
1999 else
2000 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2001 }
2002
2003 for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2004 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2005
2006 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2007 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2008 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2009 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2010 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2011 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2012 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2013 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2014 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2015 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2016
2017 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2018 result = smu7_copy_bytes_to_smc(hwmgr,
2019 smu_data->smu7_data.dpm_table_start +
2020 offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2021 (const uint8_t *)&(table->SystemFlags),
2022 sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2023 SMC_RAM_END);
2024 PP_ASSERT_WITH_CODE(0 == result,
2025 "Failed to upload dpm data to SMC memory!", return result);
2026
2027 result = polaris10_init_arb_table_index(hwmgr);
2028 PP_ASSERT_WITH_CODE(0 == result,
2029 "Failed to upload arb data to SMC memory!", return result);
2030
2031 result = polaris10_populate_pm_fuses(hwmgr);
2032 PP_ASSERT_WITH_CODE(0 == result,
2033 "Failed to populate PM fuses to SMC memory!", return result);
2034
2035 return 0;
2036 }
2037
polaris10_program_mem_timing_parameters(struct pp_hwmgr * hwmgr)2038 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2039 {
2040 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2041
2042 if (data->need_update_smu7_dpm_table &
2043 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2044 return polaris10_program_memory_timing_parameters(hwmgr);
2045
2046 return 0;
2047 }
2048
polaris10_thermal_avfs_enable(struct pp_hwmgr * hwmgr)2049 int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2050 {
2051 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2052
2053 if (!hwmgr->avfs_supported)
2054 return 0;
2055
2056 smum_send_msg_to_smc_with_parameter(hwmgr,
2057 PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting);
2058
2059 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
2060
2061 /* Apply avfs cks-off voltages to avoid the overshoot
2062 * when switching to the highest sclk frequency
2063 */
2064 if (data->apply_avfs_cks_off_voltage)
2065 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
2066
2067 return 0;
2068 }
2069
polaris10_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)2070 static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2071 {
2072 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2073 SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2074 uint32_t duty100;
2075 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2076 uint16_t fdo_min, slope1, slope2;
2077 uint32_t reference_clock;
2078 int res;
2079 uint64_t tmp64;
2080
2081 if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2082 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2083 PHM_PlatformCaps_MicrocodeFanControl);
2084 return 0;
2085 }
2086
2087 if (smu_data->smu7_data.fan_table_start == 0) {
2088 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2089 PHM_PlatformCaps_MicrocodeFanControl);
2090 return 0;
2091 }
2092
2093 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2094 CG_FDO_CTRL1, FMAX_DUTY100);
2095
2096 if (duty100 == 0) {
2097 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2098 PHM_PlatformCaps_MicrocodeFanControl);
2099 return 0;
2100 }
2101
2102 /* use hardware fan control */
2103 if (hwmgr->thermal_controller.use_hw_fan_control)
2104 return 0;
2105
2106 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2107 usPWMMin * duty100;
2108 do_div(tmp64, 10000);
2109 fdo_min = (uint16_t)tmp64;
2110
2111 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2112 hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2113 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2114 hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2115
2116 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2117 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2118 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2119 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2120
2121 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2122 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2123
2124 fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2125 thermal_controller.advanceFanControlParameters.usTMin) / 100);
2126 fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2127 thermal_controller.advanceFanControlParameters.usTMed) / 100);
2128 fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2129 thermal_controller.advanceFanControlParameters.usTMax) / 100);
2130
2131 fan_table.Slope1 = cpu_to_be16(slope1);
2132 fan_table.Slope2 = cpu_to_be16(slope2);
2133
2134 fan_table.FdoMin = cpu_to_be16(fdo_min);
2135
2136 fan_table.HystDown = cpu_to_be16(hwmgr->
2137 thermal_controller.advanceFanControlParameters.ucTHyst);
2138
2139 fan_table.HystUp = cpu_to_be16(1);
2140
2141 fan_table.HystSlope = cpu_to_be16(1);
2142
2143 fan_table.TempRespLim = cpu_to_be16(5);
2144
2145 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2146
2147 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2148 thermal_controller.advanceFanControlParameters.ulCycleDelay *
2149 reference_clock) / 1600);
2150
2151 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2152
2153 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2154 hwmgr->device, CGS_IND_REG__SMC,
2155 CG_MULT_THERMAL_CTRL, TEMP_SEL);
2156
2157 res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2158 (const uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2159 SMC_RAM_END);
2160
2161 if (!res && hwmgr->thermal_controller.
2162 advanceFanControlParameters.ucMinimumPWMLimit)
2163 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2164 PPSMC_MSG_SetFanMinPwm,
2165 hwmgr->thermal_controller.
2166 advanceFanControlParameters.ucMinimumPWMLimit);
2167
2168 if (!res && hwmgr->thermal_controller.
2169 advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2170 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2171 PPSMC_MSG_SetFanSclkTarget,
2172 hwmgr->thermal_controller.
2173 advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
2174
2175 if (res)
2176 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2177 PHM_PlatformCaps_MicrocodeFanControl);
2178
2179 return 0;
2180 }
2181
polaris10_update_uvd_smc_table(struct pp_hwmgr * hwmgr)2182 static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2183 {
2184 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2185 uint32_t mm_boot_level_offset, mm_boot_level_value;
2186 struct phm_ppt_v1_information *table_info =
2187 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2188
2189 smu_data->smc_state_table.UvdBootLevel = 0;
2190 if (table_info->mm_dep_table->count > 0)
2191 smu_data->smc_state_table.UvdBootLevel =
2192 (uint8_t) (table_info->mm_dep_table->count - 1);
2193 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
2194 UvdBootLevel);
2195 mm_boot_level_offset /= 4;
2196 mm_boot_level_offset *= 4;
2197 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2198 CGS_IND_REG__SMC, mm_boot_level_offset);
2199 mm_boot_level_value &= 0x00FFFFFF;
2200 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2201 cgs_write_ind_register(hwmgr->device,
2202 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2203
2204 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2205 PHM_PlatformCaps_UVDDPM) ||
2206 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2207 PHM_PlatformCaps_StablePState))
2208 smum_send_msg_to_smc_with_parameter(hwmgr,
2209 PPSMC_MSG_UVDDPM_SetEnabledMask,
2210 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
2211 return 0;
2212 }
2213
polaris10_update_vce_smc_table(struct pp_hwmgr * hwmgr)2214 static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2215 {
2216 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2217 uint32_t mm_boot_level_offset, mm_boot_level_value;
2218 struct phm_ppt_v1_information *table_info =
2219 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2220
2221 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2222 PHM_PlatformCaps_StablePState))
2223 smu_data->smc_state_table.VceBootLevel =
2224 (uint8_t) (table_info->mm_dep_table->count - 1);
2225 else
2226 smu_data->smc_state_table.VceBootLevel = 0;
2227
2228 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2229 offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2230 mm_boot_level_offset /= 4;
2231 mm_boot_level_offset *= 4;
2232 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2233 CGS_IND_REG__SMC, mm_boot_level_offset);
2234 mm_boot_level_value &= 0xFF00FFFF;
2235 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2236 cgs_write_ind_register(hwmgr->device,
2237 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2238
2239 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2240 smum_send_msg_to_smc_with_parameter(hwmgr,
2241 PPSMC_MSG_VCEDPM_SetEnabledMask,
2242 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
2243 return 0;
2244 }
2245
polaris10_update_bif_smc_table(struct pp_hwmgr * hwmgr)2246 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2247 {
2248 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2249 struct phm_ppt_v1_information *table_info =
2250 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2251 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2252 int max_entry, i;
2253
2254 max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
2255 SMU74_MAX_LEVELS_LINK :
2256 pcie_table->count;
2257 /* Setup BIF_SCLK levels */
2258 for (i = 0; i < max_entry; i++)
2259 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
2260 return 0;
2261 }
2262
polaris10_update_smc_table(struct pp_hwmgr * hwmgr,uint32_t type)2263 static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2264 {
2265 switch (type) {
2266 case SMU_UVD_TABLE:
2267 polaris10_update_uvd_smc_table(hwmgr);
2268 break;
2269 case SMU_VCE_TABLE:
2270 polaris10_update_vce_smc_table(hwmgr);
2271 break;
2272 case SMU_BIF_TABLE:
2273 polaris10_update_bif_smc_table(hwmgr);
2274 default:
2275 break;
2276 }
2277 return 0;
2278 }
2279
polaris10_update_sclk_threshold(struct pp_hwmgr * hwmgr)2280 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2281 {
2282 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2283 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2284
2285 int result = 0;
2286 uint32_t low_sclk_interrupt_threshold = 0;
2287
2288 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2289 PHM_PlatformCaps_SclkThrottleLowNotification)
2290 && (data->low_sclk_interrupt_threshold != 0)) {
2291 low_sclk_interrupt_threshold =
2292 data->low_sclk_interrupt_threshold;
2293
2294 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2295
2296 result = smu7_copy_bytes_to_smc(
2297 hwmgr,
2298 smu_data->smu7_data.dpm_table_start +
2299 offsetof(SMU74_Discrete_DpmTable,
2300 LowSclkInterruptThreshold),
2301 (const uint8_t *)&low_sclk_interrupt_threshold,
2302 sizeof(uint32_t),
2303 SMC_RAM_END);
2304 }
2305 PP_ASSERT_WITH_CODE((result == 0),
2306 "Failed to update SCLK threshold!", return result);
2307
2308 result = polaris10_program_mem_timing_parameters(hwmgr);
2309 PP_ASSERT_WITH_CODE((result == 0),
2310 "Failed to program memory timing parameters!",
2311 );
2312
2313 return result;
2314 }
2315
polaris10_get_offsetof(uint32_t type,uint32_t member)2316 static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2317 {
2318 switch (type) {
2319 case SMU_SoftRegisters:
2320 switch (member) {
2321 case HandshakeDisables:
2322 return offsetof(SMU74_SoftRegisters, HandshakeDisables);
2323 case VoltageChangeTimeout:
2324 return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
2325 case AverageGraphicsActivity:
2326 return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
2327 case AverageMemoryActivity:
2328 return offsetof(SMU74_SoftRegisters, AverageMemoryActivity);
2329 case PreVBlankGap:
2330 return offsetof(SMU74_SoftRegisters, PreVBlankGap);
2331 case VBlankTimeout:
2332 return offsetof(SMU74_SoftRegisters, VBlankTimeout);
2333 case UcodeLoadStatus:
2334 return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
2335 case DRAM_LOG_ADDR_H:
2336 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
2337 case DRAM_LOG_ADDR_L:
2338 return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
2339 case DRAM_LOG_PHY_ADDR_H:
2340 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2341 case DRAM_LOG_PHY_ADDR_L:
2342 return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2343 case DRAM_LOG_BUFF_SIZE:
2344 return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2345 }
2346 break;
2347 case SMU_Discrete_DpmTable:
2348 switch (member) {
2349 case UvdBootLevel:
2350 return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2351 case VceBootLevel:
2352 return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2353 case LowSclkInterruptThreshold:
2354 return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
2355 }
2356 break;
2357 }
2358 pr_warn("can't get the offset of type %x member %x\n", type, member);
2359 return 0;
2360 }
2361
polaris10_get_mac_definition(uint32_t value)2362 static uint32_t polaris10_get_mac_definition(uint32_t value)
2363 {
2364 switch (value) {
2365 case SMU_MAX_LEVELS_GRAPHICS:
2366 return SMU74_MAX_LEVELS_GRAPHICS;
2367 case SMU_MAX_LEVELS_MEMORY:
2368 return SMU74_MAX_LEVELS_MEMORY;
2369 case SMU_MAX_LEVELS_LINK:
2370 return SMU74_MAX_LEVELS_LINK;
2371 case SMU_MAX_ENTRIES_SMIO:
2372 return SMU74_MAX_ENTRIES_SMIO;
2373 case SMU_MAX_LEVELS_VDDC:
2374 return SMU74_MAX_LEVELS_VDDC;
2375 case SMU_MAX_LEVELS_VDDGFX:
2376 return SMU74_MAX_LEVELS_VDDGFX;
2377 case SMU_MAX_LEVELS_VDDCI:
2378 return SMU74_MAX_LEVELS_VDDCI;
2379 case SMU_MAX_LEVELS_MVDD:
2380 return SMU74_MAX_LEVELS_MVDD;
2381 case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
2382 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2383 }
2384
2385 pr_warn("can't get the mac of %x\n", value);
2386 return 0;
2387 }
2388
polaris10_process_firmware_header(struct pp_hwmgr * hwmgr)2389 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2390 {
2391 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2392 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2393 uint32_t tmp;
2394 int result;
2395 bool error = false;
2396
2397 result = smu7_read_smc_sram_dword(hwmgr,
2398 SMU7_FIRMWARE_HEADER_LOCATION +
2399 offsetof(SMU74_Firmware_Header, DpmTable),
2400 &tmp, SMC_RAM_END);
2401
2402 if (0 == result)
2403 smu_data->smu7_data.dpm_table_start = tmp;
2404
2405 error |= (0 != result);
2406
2407 result = smu7_read_smc_sram_dword(hwmgr,
2408 SMU7_FIRMWARE_HEADER_LOCATION +
2409 offsetof(SMU74_Firmware_Header, SoftRegisters),
2410 &tmp, SMC_RAM_END);
2411
2412 if (!result) {
2413 data->soft_regs_start = tmp;
2414 smu_data->smu7_data.soft_regs_start = tmp;
2415 }
2416
2417 error |= (0 != result);
2418
2419 result = smu7_read_smc_sram_dword(hwmgr,
2420 SMU7_FIRMWARE_HEADER_LOCATION +
2421 offsetof(SMU74_Firmware_Header, mcRegisterTable),
2422 &tmp, SMC_RAM_END);
2423
2424 if (!result)
2425 smu_data->smu7_data.mc_reg_table_start = tmp;
2426
2427 result = smu7_read_smc_sram_dword(hwmgr,
2428 SMU7_FIRMWARE_HEADER_LOCATION +
2429 offsetof(SMU74_Firmware_Header, FanTable),
2430 &tmp, SMC_RAM_END);
2431
2432 if (!result)
2433 smu_data->smu7_data.fan_table_start = tmp;
2434
2435 error |= (0 != result);
2436
2437 result = smu7_read_smc_sram_dword(hwmgr,
2438 SMU7_FIRMWARE_HEADER_LOCATION +
2439 offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
2440 &tmp, SMC_RAM_END);
2441
2442 if (!result)
2443 smu_data->smu7_data.arb_table_start = tmp;
2444
2445 error |= (0 != result);
2446
2447 result = smu7_read_smc_sram_dword(hwmgr,
2448 SMU7_FIRMWARE_HEADER_LOCATION +
2449 offsetof(SMU74_Firmware_Header, Version),
2450 &tmp, SMC_RAM_END);
2451
2452 if (!result)
2453 hwmgr->microcode_version_info.SMC = tmp;
2454
2455 error |= (0 != result);
2456
2457 return error ? -1 : 0;
2458 }
2459
polaris10_is_dpm_running(struct pp_hwmgr * hwmgr)2460 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2461 {
2462 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2463 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2464 ? true : false;
2465 }
2466
polaris10_update_dpm_settings(struct pp_hwmgr * hwmgr,void * profile_setting)2467 static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
2468 void *profile_setting)
2469 {
2470 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2471 struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2472 (hwmgr->smu_backend);
2473 struct profile_mode_setting *setting;
2474 struct SMU74_Discrete_GraphicsLevel *levels =
2475 smu_data->smc_state_table.GraphicsLevel;
2476 uint32_t array = smu_data->smu7_data.dpm_table_start +
2477 offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
2478
2479 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2480 offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
2481 struct SMU74_Discrete_MemoryLevel *mclk_levels =
2482 smu_data->smc_state_table.MemoryLevel;
2483 uint32_t i;
2484 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2485
2486 if (profile_setting == NULL)
2487 return -EINVAL;
2488
2489 setting = (struct profile_mode_setting *)profile_setting;
2490
2491 if (setting->bupdate_sclk) {
2492 if (!data->sclk_dpm_key_disabled)
2493 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
2494 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2495 if (levels[i].ActivityLevel !=
2496 cpu_to_be16(setting->sclk_activity)) {
2497 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2498
2499 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2500 + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
2501 offset = clk_activity_offset & ~0x3;
2502 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2503 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2504 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2505
2506 }
2507 if (levels[i].UpHyst != setting->sclk_up_hyst ||
2508 levels[i].DownHyst != setting->sclk_down_hyst) {
2509 levels[i].UpHyst = setting->sclk_up_hyst;
2510 levels[i].DownHyst = setting->sclk_down_hyst;
2511 up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2512 + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
2513 down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2514 + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
2515 offset = up_hyst_offset & ~0x3;
2516 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2517 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2518 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2519 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2520 }
2521 }
2522 if (!data->sclk_dpm_key_disabled)
2523 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
2524 }
2525
2526 if (setting->bupdate_mclk) {
2527 if (!data->mclk_dpm_key_disabled)
2528 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
2529 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2530 if (mclk_levels[i].ActivityLevel !=
2531 cpu_to_be16(setting->mclk_activity)) {
2532 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2533
2534 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2535 + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
2536 offset = clk_activity_offset & ~0x3;
2537 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2538 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2539 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2540
2541 }
2542 if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2543 mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2544 mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2545 mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2546 up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2547 + offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
2548 down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2549 + offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
2550 offset = up_hyst_offset & ~0x3;
2551 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2552 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2553 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2554 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2555 }
2556 }
2557 if (!data->mclk_dpm_key_disabled)
2558 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
2559 }
2560 return 0;
2561 }
2562
2563 const struct pp_smumgr_func polaris10_smu_funcs = {
2564 .name = "polaris10_smu",
2565 .smu_init = polaris10_smu_init,
2566 .smu_fini = smu7_smu_fini,
2567 .start_smu = polaris10_start_smu,
2568 .check_fw_load_finish = smu7_check_fw_load_finish,
2569 .request_smu_load_fw = smu7_reload_firmware,
2570 .request_smu_load_specific_fw = NULL,
2571 .send_msg_to_smc = smu7_send_msg_to_smc,
2572 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2573 .download_pptable_settings = NULL,
2574 .upload_pptable_settings = NULL,
2575 .update_smc_table = polaris10_update_smc_table,
2576 .get_offsetof = polaris10_get_offsetof,
2577 .process_firmware_header = polaris10_process_firmware_header,
2578 .init_smc_table = polaris10_init_smc_table,
2579 .update_sclk_threshold = polaris10_update_sclk_threshold,
2580 .thermal_avfs_enable = polaris10_thermal_avfs_enable,
2581 .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
2582 .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
2583 .populate_all_memory_levels = polaris10_populate_all_memory_levels,
2584 .get_mac_definition = polaris10_get_mac_definition,
2585 .is_dpm_running = polaris10_is_dpm_running,
2586 .is_hw_avfs_present = polaris10_is_hw_avfs_present,
2587 .update_dpm_settings = polaris10_update_dpm_settings,
2588 };
2589